1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK 3 4; Same as vecreduce-fmul-legalization.ll, but without fmf. 5 6declare half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half, <1 x half>) 7declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float, <1 x float>) 8declare double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double, <1 x double>) 9declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128, <1 x fp128>) 10 11declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float, <3 x float>) 12declare fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128, <2 x fp128>) 13declare float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float, <16 x float>) 14 15define half @test_v1f16(<1 x half> %a) nounwind { 16; CHECK-LABEL: test_v1f16: 17; CHECK: // %bb.0: 18; CHECK-NEXT: fcvt s0, h0 19; CHECK-NEXT: fmov s1, wzr 20; CHECK-NEXT: fmul s0, s0, s1 21; CHECK-NEXT: fcvt h0, s0 22; CHECK-NEXT: ret 23 %b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a) 24 ret half %b 25} 26 27define float @test_v1f32(<1 x float> %a) nounwind { 28; CHECK-LABEL: test_v1f32: 29; CHECK: // %bb.0: 30; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 31; CHECK-NEXT: fmov s1, wzr 32; CHECK-NEXT: fmul s0, s1, v0.s[0] 33; CHECK-NEXT: ret 34 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a) 35 ret float %b 36} 37 38define double @test_v1f64(<1 x double> %a) nounwind { 39; CHECK-LABEL: test_v1f64: 40; CHECK: // %bb.0: 41; CHECK-NEXT: fmov d1, xzr 42; CHECK-NEXT: fmul d0, d0, d1 43; CHECK-NEXT: ret 44 %b = call double @llvm.experimental.vector.reduce.v2.fmul.f64.v1f64(double 0.0, <1 x double> %a) 45 ret double %b 46} 47 48define fp128 @test_v1f128(<1 x fp128> %a) nounwind { 49; CHECK-LABEL: test_v1f128: 50; CHECK: // %bb.0: 51; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill 52; CHECK-NEXT: adrp x8, .LCPI3_0 53; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] 54; CHECK-NEXT: bl __multf3 55; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload 56; CHECK-NEXT: ret 57 %b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v1f128(fp128 zeroinitializer, <1 x fp128> %a) 58 ret fp128 %b 59} 60 61define float @test_v3f32(<3 x float> %a) nounwind { 62; CHECK-LABEL: test_v3f32: 63; CHECK: // %bb.0: 64; CHECK-NEXT: fmov s1, wzr 65; CHECK-NEXT: fmul s1, s1, v0.s[0] 66; CHECK-NEXT: fmul s1, s1, v0.s[1] 67; CHECK-NEXT: fmul s0, s1, v0.s[2] 68; CHECK-NEXT: ret 69 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a) 70 ret float %b 71} 72 73define fp128 @test_v2f128(<2 x fp128> %a) nounwind { 74; CHECK-LABEL: test_v2f128: 75; CHECK: // %bb.0: 76; CHECK-NEXT: sub sp, sp, #32 // =32 77; CHECK-NEXT: adrp x8, .LCPI5_0 78; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill 79; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] 80; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill 81; CHECK-NEXT: bl __multf3 82; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload 83; CHECK-NEXT: bl __multf3 84; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload 85; CHECK-NEXT: add sp, sp, #32 // =32 86; CHECK-NEXT: ret 87 %b = call fp128 @llvm.experimental.vector.reduce.v2.fmul.f128.v2f128(fp128 zeroinitializer, <2 x fp128> %a) 88 ret fp128 %b 89} 90 91define float @test_v16f32(<16 x float> %a) nounwind { 92; CHECK-LABEL: test_v16f32: 93; CHECK: // %bb.0: 94; CHECK-NEXT: fmov s4, wzr 95; CHECK-NEXT: fmul s4, s4, v0.s[0] 96; CHECK-NEXT: fmul s4, s4, v0.s[1] 97; CHECK-NEXT: fmul s4, s4, v0.s[2] 98; CHECK-NEXT: fmul s0, s4, v0.s[3] 99; CHECK-NEXT: fmul s0, s0, v1.s[0] 100; CHECK-NEXT: fmul s0, s0, v1.s[1] 101; CHECK-NEXT: fmul s0, s0, v1.s[2] 102; CHECK-NEXT: fmul s0, s0, v1.s[3] 103; CHECK-NEXT: fmul s0, s0, v2.s[0] 104; CHECK-NEXT: fmul s0, s0, v2.s[1] 105; CHECK-NEXT: fmul s0, s0, v2.s[2] 106; CHECK-NEXT: fmul s0, s0, v2.s[3] 107; CHECK-NEXT: fmul s0, s0, v3.s[0] 108; CHECK-NEXT: fmul s0, s0, v3.s[1] 109; CHECK-NEXT: fmul s0, s0, v3.s[2] 110; CHECK-NEXT: fmul s0, s0, v3.s[3] 111; CHECK-NEXT: ret 112 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a) 113 ret float %b 114} 115