1; Test that compares are omitted if CC already has the right value
2; (z196 version).
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 -no-integrated-as | FileCheck %s
5
6; Addition provides enough for comparisons with zero if we know no
7; signed overflow happens, which is when the "nsw" flag is set.
8; First test the EQ case with LOC.
9define i32 @f1(i32 %a, i32 %b, i32 *%cptr) {
10; CHECK-LABEL: f1:
11; CHECK: afi %r2, 1000000
12; CHECK-NEXT: loce %r3, 0(%r4)
13; CHECK: br %r14
14  %add = add nsw i32 %a, 1000000
15  %cmp = icmp eq i32 %add, 0
16  %c = load i32, i32 *%cptr
17  %arg = select i1 %cmp, i32 %c, i32 %b
18  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
19  ret i32 %add
20}
21
22; ...and again with STOC.
23define i32 @f2(i32 %a, i32 %b, i32 *%cptr) {
24; CHECK-LABEL: f2:
25; CHECK: afi %r2, 1000000
26; CHECK-NEXT: stoce %r3, 0(%r4)
27; CHECK: br %r14
28  %add = add nsw i32 %a, 1000000
29  %cmp = icmp eq i32 %add, 0
30  %c = load i32, i32 *%cptr
31  %newval = select i1 %cmp, i32 %b, i32 %c
32  store i32 %newval, i32 *%cptr
33  ret i32 %add
34}
35
36; Reverse the select order and test with LOCR.
37define i32 @f3(i32 %a, i32 %b, i32 %c) {
38; CHECK-LABEL: f3:
39; CHECK: afi %r2, 1000000
40; CHECK-NEXT: locrlh %r3, %r4
41; CHECK: br %r14
42  %add = add nsw i32 %a, 1000000
43  %cmp = icmp eq i32 %add, 0
44  %arg = select i1 %cmp, i32 %b, i32 %c
45  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
46  ret i32 %add
47}
48
49; ...and again with LOC.
50define i32 @f4(i32 %a, i32 %b, i32 *%cptr) {
51; CHECK-LABEL: f4:
52; CHECK: afi %r2, 1000000
53; CHECK-NEXT: loclh %r3, 0(%r4)
54; CHECK: br %r14
55  %add = add nsw i32 %a, 1000000
56  %cmp = icmp eq i32 %add, 0
57  %c = load i32, i32 *%cptr
58  %arg = select i1 %cmp, i32 %b, i32 %c
59  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
60  ret i32 %add
61}
62
63; ...and again with STOC.
64define i32 @f5(i32 %a, i32 %b, i32 *%cptr) {
65; CHECK-LABEL: f5:
66; CHECK: afi %r2, 1000000
67; CHECK-NEXT: stoclh %r3, 0(%r4)
68; CHECK: br %r14
69  %add = add nsw i32 %a, 1000000
70  %cmp = icmp eq i32 %add, 0
71  %c = load i32, i32 *%cptr
72  %newval = select i1 %cmp, i32 %c, i32 %b
73  store i32 %newval, i32 *%cptr
74  ret i32 %add
75}
76
77; Change the EQ in f3 to NE.
78define i32 @f6(i32 %a, i32 %b, i32 %c) {
79; CHECK-LABEL: f6:
80; CHECK: afi %r2, 1000000
81; CHECK-NEXT: locre %r3, %r4
82; CHECK: br %r14
83  %add = add nsw i32 %a, 1000000
84  %cmp = icmp ne i32 %add, 0
85  %arg = select i1 %cmp, i32 %b, i32 %c
86  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
87  ret i32 %add
88}
89
90; ...and again with LOC.
91define i32 @f7(i32 %a, i32 %b, i32 *%cptr) {
92; CHECK-LABEL: f7:
93; CHECK: afi %r2, 1000000
94; CHECK-NEXT: loce %r3, 0(%r4)
95; CHECK: br %r14
96  %add = add nsw i32 %a, 1000000
97  %cmp = icmp ne i32 %add, 0
98  %c = load i32, i32 *%cptr
99  %arg = select i1 %cmp, i32 %b, i32 %c
100  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
101  ret i32 %add
102}
103
104; ...and again with STOC.
105define i32 @f8(i32 %a, i32 %b, i32 *%cptr) {
106; CHECK-LABEL: f8:
107; CHECK: afi %r2, 1000000
108; CHECK-NEXT: stoce %r3, 0(%r4)
109; CHECK: br %r14
110  %add = add nsw i32 %a, 1000000
111  %cmp = icmp ne i32 %add, 0
112  %c = load i32, i32 *%cptr
113  %newval = select i1 %cmp, i32 %c, i32 %b
114  store i32 %newval, i32 *%cptr
115  ret i32 %add
116}
117