1 //===-- NativeRegisterContextLinux_arm64.h ---------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #if defined(__arm64__) || defined(__aarch64__) 10 11 #ifndef lldb_NativeRegisterContextLinux_arm64_h 12 #define lldb_NativeRegisterContextLinux_arm64_h 13 14 #include "Plugins/Process/Linux/NativeRegisterContextLinux.h" 15 #include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h" 16 17 #include <asm/ptrace.h> 18 19 namespace lldb_private { 20 namespace process_linux { 21 22 class NativeProcessLinux; 23 24 class NativeRegisterContextLinux_arm64 : public NativeRegisterContextLinux { 25 public: 26 NativeRegisterContextLinux_arm64(const ArchSpec &target_arch, 27 NativeThreadProtocol &native_thread); 28 29 uint32_t GetRegisterSetCount() const override; 30 31 uint32_t GetUserRegisterCount() const override; 32 33 const RegisterSet *GetRegisterSet(uint32_t set_index) const override; 34 35 Status ReadRegister(const RegisterInfo *reg_info, 36 RegisterValue ®_value) override; 37 38 Status WriteRegister(const RegisterInfo *reg_info, 39 const RegisterValue ®_value) override; 40 41 Status ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override; 42 43 Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override; 44 45 void InvalidateAllRegisters() override; 46 47 std::vector<uint32_t> 48 GetExpeditedRegisters(ExpeditedRegs expType) const override; 49 RegisterOffsetIsDynamic()50 bool RegisterOffsetIsDynamic() const override { return true; } 51 52 // Hardware breakpoints/watchpoint management functions 53 54 uint32_t NumSupportedHardwareBreakpoints() override; 55 56 uint32_t SetHardwareBreakpoint(lldb::addr_t addr, size_t size) override; 57 58 bool ClearHardwareBreakpoint(uint32_t hw_idx) override; 59 60 Status ClearAllHardwareBreakpoints() override; 61 62 Status GetHardwareBreakHitIndex(uint32_t &bp_index, 63 lldb::addr_t trap_addr) override; 64 65 uint32_t NumSupportedHardwareWatchpoints() override; 66 67 uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size, 68 uint32_t watch_flags) override; 69 70 bool ClearHardwareWatchpoint(uint32_t hw_index) override; 71 72 Status ClearAllHardwareWatchpoints() override; 73 74 Status GetWatchpointHitIndex(uint32_t &wp_index, 75 lldb::addr_t trap_addr) override; 76 77 lldb::addr_t GetWatchpointHitAddress(uint32_t wp_index) override; 78 79 lldb::addr_t GetWatchpointAddress(uint32_t wp_index) override; 80 81 uint32_t GetWatchpointSize(uint32_t wp_index); 82 83 bool WatchpointIsEnabled(uint32_t wp_index); 84 85 // Debug register type select 86 enum DREGType { eDREGTypeWATCH = 0, eDREGTypeBREAK }; 87 88 protected: 89 90 Status ReadGPR() override; 91 92 Status WriteGPR() override; 93 94 Status ReadFPR() override; 95 96 Status WriteFPR() override; 97 GetGPRBuffer()98 void *GetGPRBuffer() override { return &m_gpr_arm64; } 99 100 // GetGPRBufferSize returns sizeof arm64 GPR ptrace buffer, it is different 101 // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR. GetGPRBufferSize()102 size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); } 103 GetFPRBuffer()104 void *GetFPRBuffer() override { return &m_fpr; } 105 GetFPRSize()106 size_t GetFPRSize() override { return sizeof(m_fpr); } 107 108 private: 109 bool m_gpr_is_valid; 110 bool m_fpu_is_valid; 111 bool m_sve_buffer_is_valid; 112 113 bool m_sve_header_is_valid; 114 115 struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers. 116 117 RegisterInfoPOSIX_arm64::FPU 118 m_fpr; // floating-point registers including extended register sets. 119 120 SVEState m_sve_state; 121 struct user_sve_header m_sve_header; 122 std::vector<uint8_t> m_sve_ptrace_payload; 123 124 // Debug register info for hardware breakpoints and watchpoints management. 125 struct DREG { 126 lldb::addr_t address; // Breakpoint/watchpoint address value. 127 lldb::addr_t hit_addr; // Address at which last watchpoint trigger exception 128 // occurred. 129 lldb::addr_t real_addr; // Address value that should cause target to stop. 130 uint32_t control; // Breakpoint/watchpoint control value. 131 uint32_t refcount; // Serves as enable/disable and reference counter. 132 }; 133 134 struct DREG m_hbr_regs[16]; // Arm native linux hardware breakpoints 135 struct DREG m_hwp_regs[16]; // Arm native linux hardware watchpoints 136 137 uint32_t m_max_hwp_supported; 138 uint32_t m_max_hbp_supported; 139 bool m_refresh_hwdebug_info; 140 141 bool IsGPR(unsigned reg) const; 142 143 bool IsFPR(unsigned reg) const; 144 145 Status ReadAllSVE(); 146 147 Status WriteAllSVE(); 148 149 Status ReadSVEHeader(); 150 151 Status WriteSVEHeader(); 152 153 bool IsSVE(unsigned reg) const; 154 GetSVERegVG()155 uint64_t GetSVERegVG() { return m_sve_header.vl / 8; } 156 SetSVERegVG(uint64_t vg)157 void SetSVERegVG(uint64_t vg) { m_sve_header.vl = vg * 8; } 158 GetSVEHeader()159 void *GetSVEHeader() { return &m_sve_header; } 160 161 void *GetSVEBuffer(); 162 GetSVEHeaderSize()163 size_t GetSVEHeaderSize() { return sizeof(m_sve_header); } 164 GetSVEBufferSize()165 size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); } 166 167 Status ReadHardwareDebugInfo(); 168 169 Status WriteHardwareDebugRegs(int hwbType); 170 171 uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const; 172 173 RegisterInfoPOSIX_arm64 &GetRegisterInfo() const; 174 175 void ConfigureRegisterContext(); 176 177 uint32_t CalculateSVEOffset(const RegisterInfo *reg_info) const; 178 }; 179 180 } // namespace process_linux 181 } // namespace lldb_private 182 183 #endif // #ifndef lldb_NativeRegisterContextLinux_arm64_h 184 185 #endif // defined (__arm64__) || defined (__aarch64__) 186