1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Methods common to all machine instructions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/FoldingSet.h"
17 #include "llvm/ADT/Hashing.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallBitVector.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/Analysis/Loads.h"
25 #include "llvm/Analysis/MemoryLocation.h"
26 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrBundle.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/TargetInstrInfo.h"
39 #include "llvm/CodeGen/TargetRegisterInfo.h"
40 #include "llvm/CodeGen/TargetSubtargetInfo.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugInfoMetadata.h"
44 #include "llvm/IR/DebugLoc.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/InlineAsm.h"
48 #include "llvm/IR/InstrTypes.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Module.h"
53 #include "llvm/IR/ModuleSlotTracker.h"
54 #include "llvm/IR/Operator.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/Value.h"
57 #include "llvm/MC/MCInstrDesc.h"
58 #include "llvm/MC/MCRegisterInfo.h"
59 #include "llvm/MC/MCSymbol.h"
60 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/CommandLine.h"
62 #include "llvm/Support/Compiler.h"
63 #include "llvm/Support/Debug.h"
64 #include "llvm/Support/ErrorHandling.h"
65 #include "llvm/Support/FormattedStream.h"
66 #include "llvm/Support/LowLevelTypeImpl.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Support/raw_ostream.h"
69 #include "llvm/Target/TargetIntrinsicInfo.h"
70 #include "llvm/Target/TargetMachine.h"
71 #include <algorithm>
72 #include <cassert>
73 #include <cstddef>
74 #include <cstdint>
75 #include <cstring>
76 #include <iterator>
77 #include <utility>
78
79 using namespace llvm;
80
getMFIfAvailable(const MachineInstr & MI)81 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86 }
87
88 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89 // it.
tryToGetTargetInfo(const MachineInstr & MI,const TargetRegisterInfo * & TRI,const MachineRegisterInfo * & MRI,const TargetIntrinsicInfo * & IntrinsicInfo,const TargetInstrInfo * & TII)90 static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102 }
103
addImplicitDefUseOperands(MachineFunction & MF)104 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113 }
114
115 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116 /// implicit operands. It reserves space for the number of operands specified by
117 /// the MCInstrDesc.
MachineInstr(MachineFunction & MF,const MCInstrDesc & tid,DebugLoc dl,bool NoImp)118 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119 DebugLoc dl, bool NoImp)
120 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132 }
133
134 /// MachineInstr ctor - Copies MachineInstr arg exactly.
135 /// Does not copy the number from debug instruction numbering, to preserve
136 /// uniqueness.
MachineInstr(MachineFunction & MF,const MachineInstr & MI)137 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151 }
152
moveBefore(MachineInstr * MovePos)153 void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155 }
156
157 /// getRegInfo - If this instruction is embedded into a MachineFunction,
158 /// return the MachineRegisterInfo object for the current function, otherwise
159 /// return null.
getRegInfo()160 MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164 }
165
166 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167 /// this instruction from their respective use lists. This requires that the
168 /// operands already be on their use lists.
RemoveRegOperandsFromUseLists(MachineRegisterInfo & MRI)169 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173 }
174
175 /// AddRegOperandsToUseLists - Add all of the register operands in
176 /// this instruction from their respective use lists. This requires that the
177 /// operands not be on their use lists yet.
AddRegOperandsToUseLists(MachineRegisterInfo & MRI)178 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182 }
183
addOperand(const MachineOperand & Op)184 void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
189 addOperand(*MF, Op);
190 }
191
192 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193 /// ranges. If MRI is non-null also update use-def chains.
moveOperands(MachineOperand * Dst,MachineOperand * Src,unsigned NumOps,MachineRegisterInfo * MRI)194 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI)
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands");
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201 }
202
203 /// addOperand - Add the specified operand to the instruction. If it is an
204 /// implicit operand, it is added to the end of the operand list. If it is
205 /// an explicit operand it is added at the end of the explicit operand list
206 /// (before the first implicit operand).
addOperand(MachineFunction & MF,const MachineOperand & Op)207 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor");
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg && !isInlineAsm()) {
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
232 }
233 }
234
235 #ifndef NDEBUG
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
242 OpNo < MCID->getNumOperands() || isDebugOp) &&
243 "Trying to add an operand to a machine instr that is already done!");
244 #endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
257 moveOperands(Operands, OldOperands, OpNo, MRI);
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 }
298 }
299
300 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
301 /// fewer operand than it started with.
302 ///
RemoveOperand(unsigned OpNo)303 void MachineInstr::RemoveOperand(unsigned OpNo) {
304 assert(OpNo < getNumOperands() && "Invalid operand number");
305 untieRegOperand(OpNo);
306
307 #ifndef NDEBUG
308 // Moving tied operands would break the ties.
309 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
310 if (Operands[i].isReg())
311 assert(!Operands[i].isTied() && "Cannot move tied operands");
312 #endif
313
314 MachineRegisterInfo *MRI = getRegInfo();
315 if (MRI && Operands[OpNo].isReg())
316 MRI->removeRegOperandFromUseList(Operands + OpNo);
317
318 // Don't call the MachineOperand destructor. A lot of this code depends on
319 // MachineOperand having a trivial destructor anyway, and adding a call here
320 // wouldn't make it 'destructor-correct'.
321
322 if (unsigned N = NumOperands - 1 - OpNo)
323 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
324 --NumOperands;
325 }
326
setExtraInfo(MachineFunction & MF,ArrayRef<MachineMemOperand * > MMOs,MCSymbol * PreInstrSymbol,MCSymbol * PostInstrSymbol,MDNode * HeapAllocMarker)327 void MachineInstr::setExtraInfo(MachineFunction &MF,
328 ArrayRef<MachineMemOperand *> MMOs,
329 MCSymbol *PreInstrSymbol,
330 MCSymbol *PostInstrSymbol,
331 MDNode *HeapAllocMarker) {
332 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
333 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
334 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
335 int NumPointers =
336 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
337
338 // Drop all extra info if there is none.
339 if (NumPointers <= 0) {
340 Info.clear();
341 return;
342 }
343
344 // If more than one pointer, then store out of line. Store heap alloc markers
345 // out of line because PointerSumType cannot hold more than 4 tag types with
346 // 32-bit pointers.
347 // FIXME: Maybe we should make the symbols in the extra info mutable?
348 else if (NumPointers > 1 || HasHeapAllocMarker) {
349 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
350 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
351 return;
352 }
353
354 // Otherwise store the single pointer inline.
355 if (HasPreInstrSymbol)
356 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
357 else if (HasPostInstrSymbol)
358 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
359 else
360 Info.set<EIIK_MMO>(MMOs[0]);
361 }
362
dropMemRefs(MachineFunction & MF)363 void MachineInstr::dropMemRefs(MachineFunction &MF) {
364 if (memoperands_empty())
365 return;
366
367 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
368 getHeapAllocMarker());
369 }
370
setMemRefs(MachineFunction & MF,ArrayRef<MachineMemOperand * > MMOs)371 void MachineInstr::setMemRefs(MachineFunction &MF,
372 ArrayRef<MachineMemOperand *> MMOs) {
373 if (MMOs.empty()) {
374 dropMemRefs(MF);
375 return;
376 }
377
378 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
379 getHeapAllocMarker());
380 }
381
addMemOperand(MachineFunction & MF,MachineMemOperand * MO)382 void MachineInstr::addMemOperand(MachineFunction &MF,
383 MachineMemOperand *MO) {
384 SmallVector<MachineMemOperand *, 2> MMOs;
385 MMOs.append(memoperands_begin(), memoperands_end());
386 MMOs.push_back(MO);
387 setMemRefs(MF, MMOs);
388 }
389
cloneMemRefs(MachineFunction & MF,const MachineInstr & MI)390 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
391 if (this == &MI)
392 // Nothing to do for a self-clone!
393 return;
394
395 assert(&MF == MI.getMF() &&
396 "Invalid machine functions when cloning memory refrences!");
397 // See if we can just steal the extra info already allocated for the
398 // instruction. We can do this whenever the pre- and post-instruction symbols
399 // are the same (including null).
400 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
401 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
402 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
403 Info = MI.Info;
404 return;
405 }
406
407 // Otherwise, fall back on a copy-based clone.
408 setMemRefs(MF, MI.memoperands());
409 }
410
411 /// Check to see if the MMOs pointed to by the two MemRefs arrays are
412 /// identical.
hasIdenticalMMOs(ArrayRef<MachineMemOperand * > LHS,ArrayRef<MachineMemOperand * > RHS)413 static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
414 ArrayRef<MachineMemOperand *> RHS) {
415 if (LHS.size() != RHS.size())
416 return false;
417
418 auto LHSPointees = make_pointee_range(LHS);
419 auto RHSPointees = make_pointee_range(RHS);
420 return std::equal(LHSPointees.begin(), LHSPointees.end(),
421 RHSPointees.begin());
422 }
423
cloneMergedMemRefs(MachineFunction & MF,ArrayRef<const MachineInstr * > MIs)424 void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
425 ArrayRef<const MachineInstr *> MIs) {
426 // Try handling easy numbers of MIs with simpler mechanisms.
427 if (MIs.empty()) {
428 dropMemRefs(MF);
429 return;
430 }
431 if (MIs.size() == 1) {
432 cloneMemRefs(MF, *MIs[0]);
433 return;
434 }
435 // Because an empty memoperands list provides *no* information and must be
436 // handled conservatively (assuming the instruction can do anything), the only
437 // way to merge with it is to drop all other memoperands.
438 if (MIs[0]->memoperands_empty()) {
439 dropMemRefs(MF);
440 return;
441 }
442
443 // Handle the general case.
444 SmallVector<MachineMemOperand *, 2> MergedMMOs;
445 // Start with the first instruction.
446 assert(&MF == MIs[0]->getMF() &&
447 "Invalid machine functions when cloning memory references!");
448 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
449 // Now walk all the other instructions and accumulate any different MMOs.
450 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
451 assert(&MF == MI.getMF() &&
452 "Invalid machine functions when cloning memory references!");
453
454 // Skip MIs with identical operands to the first. This is a somewhat
455 // arbitrary hack but will catch common cases without being quadratic.
456 // TODO: We could fully implement merge semantics here if needed.
457 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
458 continue;
459
460 // Because an empty memoperands list provides *no* information and must be
461 // handled conservatively (assuming the instruction can do anything), the
462 // only way to merge with it is to drop all other memoperands.
463 if (MI.memoperands_empty()) {
464 dropMemRefs(MF);
465 return;
466 }
467
468 // Otherwise accumulate these into our temporary buffer of the merged state.
469 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
470 }
471
472 setMemRefs(MF, MergedMMOs);
473 }
474
setPreInstrSymbol(MachineFunction & MF,MCSymbol * Symbol)475 void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
476 // Do nothing if old and new symbols are the same.
477 if (Symbol == getPreInstrSymbol())
478 return;
479
480 // If there was only one symbol and we're removing it, just clear info.
481 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
482 Info.clear();
483 return;
484 }
485
486 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
487 getHeapAllocMarker());
488 }
489
setPostInstrSymbol(MachineFunction & MF,MCSymbol * Symbol)490 void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
491 // Do nothing if old and new symbols are the same.
492 if (Symbol == getPostInstrSymbol())
493 return;
494
495 // If there was only one symbol and we're removing it, just clear info.
496 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
497 Info.clear();
498 return;
499 }
500
501 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
502 getHeapAllocMarker());
503 }
504
setHeapAllocMarker(MachineFunction & MF,MDNode * Marker)505 void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
506 // Do nothing if old and new symbols are the same.
507 if (Marker == getHeapAllocMarker())
508 return;
509
510 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
511 Marker);
512 }
513
cloneInstrSymbols(MachineFunction & MF,const MachineInstr & MI)514 void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
515 const MachineInstr &MI) {
516 if (this == &MI)
517 // Nothing to do for a self-clone!
518 return;
519
520 assert(&MF == MI.getMF() &&
521 "Invalid machine functions when cloning instruction symbols!");
522
523 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
524 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
525 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
526 }
527
mergeFlagsWith(const MachineInstr & Other) const528 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
529 // For now, the just return the union of the flags. If the flags get more
530 // complicated over time, we might need more logic here.
531 return getFlags() | Other.getFlags();
532 }
533
copyFlagsFromInstruction(const Instruction & I)534 uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
535 uint16_t MIFlags = 0;
536 // Copy the wrapping flags.
537 if (const OverflowingBinaryOperator *OB =
538 dyn_cast<OverflowingBinaryOperator>(&I)) {
539 if (OB->hasNoSignedWrap())
540 MIFlags |= MachineInstr::MIFlag::NoSWrap;
541 if (OB->hasNoUnsignedWrap())
542 MIFlags |= MachineInstr::MIFlag::NoUWrap;
543 }
544
545 // Copy the exact flag.
546 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
547 if (PE->isExact())
548 MIFlags |= MachineInstr::MIFlag::IsExact;
549
550 // Copy the fast-math flags.
551 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
552 const FastMathFlags Flags = FP->getFastMathFlags();
553 if (Flags.noNaNs())
554 MIFlags |= MachineInstr::MIFlag::FmNoNans;
555 if (Flags.noInfs())
556 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
557 if (Flags.noSignedZeros())
558 MIFlags |= MachineInstr::MIFlag::FmNsz;
559 if (Flags.allowReciprocal())
560 MIFlags |= MachineInstr::MIFlag::FmArcp;
561 if (Flags.allowContract())
562 MIFlags |= MachineInstr::MIFlag::FmContract;
563 if (Flags.approxFunc())
564 MIFlags |= MachineInstr::MIFlag::FmAfn;
565 if (Flags.allowReassoc())
566 MIFlags |= MachineInstr::MIFlag::FmReassoc;
567 }
568
569 return MIFlags;
570 }
571
copyIRFlags(const Instruction & I)572 void MachineInstr::copyIRFlags(const Instruction &I) {
573 Flags = copyFlagsFromInstruction(I);
574 }
575
hasPropertyInBundle(uint64_t Mask,QueryType Type) const576 bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
577 assert(!isBundledWithPred() && "Must be called on bundle header");
578 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
579 if (MII->getDesc().getFlags() & Mask) {
580 if (Type == AnyInBundle)
581 return true;
582 } else {
583 if (Type == AllInBundle && !MII->isBundle())
584 return false;
585 }
586 // This was the last instruction in the bundle.
587 if (!MII->isBundledWithSucc())
588 return Type == AllInBundle;
589 }
590 }
591
isIdenticalTo(const MachineInstr & Other,MICheckType Check) const592 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
593 MICheckType Check) const {
594 // If opcodes or number of operands are not the same then the two
595 // instructions are obviously not identical.
596 if (Other.getOpcode() != getOpcode() ||
597 Other.getNumOperands() != getNumOperands())
598 return false;
599
600 if (isBundle()) {
601 // We have passed the test above that both instructions have the same
602 // opcode, so we know that both instructions are bundles here. Let's compare
603 // MIs inside the bundle.
604 assert(Other.isBundle() && "Expected that both instructions are bundles.");
605 MachineBasicBlock::const_instr_iterator I1 = getIterator();
606 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
607 // Loop until we analysed the last intruction inside at least one of the
608 // bundles.
609 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
610 ++I1;
611 ++I2;
612 if (!I1->isIdenticalTo(*I2, Check))
613 return false;
614 }
615 // If we've reached the end of just one of the two bundles, but not both,
616 // the instructions are not identical.
617 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
618 return false;
619 }
620
621 // Check operands to make sure they match.
622 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
623 const MachineOperand &MO = getOperand(i);
624 const MachineOperand &OMO = Other.getOperand(i);
625 if (!MO.isReg()) {
626 if (!MO.isIdenticalTo(OMO))
627 return false;
628 continue;
629 }
630
631 // Clients may or may not want to ignore defs when testing for equality.
632 // For example, machine CSE pass only cares about finding common
633 // subexpressions, so it's safe to ignore virtual register defs.
634 if (MO.isDef()) {
635 if (Check == IgnoreDefs)
636 continue;
637 else if (Check == IgnoreVRegDefs) {
638 if (!Register::isVirtualRegister(MO.getReg()) ||
639 !Register::isVirtualRegister(OMO.getReg()))
640 if (!MO.isIdenticalTo(OMO))
641 return false;
642 } else {
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
646 return false;
647 }
648 } else {
649 if (!MO.isIdenticalTo(OMO))
650 return false;
651 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
652 return false;
653 }
654 }
655 // If DebugLoc does not match then two debug instructions are not identical.
656 if (isDebugInstr())
657 if (getDebugLoc() && Other.getDebugLoc() &&
658 getDebugLoc() != Other.getDebugLoc())
659 return false;
660 return true;
661 }
662
getMF() const663 const MachineFunction *MachineInstr::getMF() const {
664 return getParent()->getParent();
665 }
666
removeFromParent()667 MachineInstr *MachineInstr::removeFromParent() {
668 assert(getParent() && "Not embedded in a basic block!");
669 return getParent()->remove(this);
670 }
671
removeFromBundle()672 MachineInstr *MachineInstr::removeFromBundle() {
673 assert(getParent() && "Not embedded in a basic block!");
674 return getParent()->remove_instr(this);
675 }
676
eraseFromParent()677 void MachineInstr::eraseFromParent() {
678 assert(getParent() && "Not embedded in a basic block!");
679 getParent()->erase(this);
680 }
681
eraseFromParentAndMarkDBGValuesForRemoval()682 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
683 assert(getParent() && "Not embedded in a basic block!");
684 MachineBasicBlock *MBB = getParent();
685 MachineFunction *MF = MBB->getParent();
686 assert(MF && "Not embedded in a function!");
687
688 MachineInstr *MI = (MachineInstr *)this;
689 MachineRegisterInfo &MRI = MF->getRegInfo();
690
691 for (const MachineOperand &MO : MI->operands()) {
692 if (!MO.isReg() || !MO.isDef())
693 continue;
694 Register Reg = MO.getReg();
695 if (!Reg.isVirtual())
696 continue;
697 MRI.markUsesInDebugValueAsUndef(Reg);
698 }
699 MI->eraseFromParent();
700 }
701
eraseFromBundle()702 void MachineInstr::eraseFromBundle() {
703 assert(getParent() && "Not embedded in a basic block!");
704 getParent()->erase_instr(this);
705 }
706
isCandidateForCallSiteEntry(QueryType Type) const707 bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
708 if (!isCall(Type))
709 return false;
710 switch (getOpcode()) {
711 case TargetOpcode::PATCHPOINT:
712 case TargetOpcode::STACKMAP:
713 case TargetOpcode::STATEPOINT:
714 case TargetOpcode::FENTRY_CALL:
715 return false;
716 }
717 return true;
718 }
719
shouldUpdateCallSiteInfo() const720 bool MachineInstr::shouldUpdateCallSiteInfo() const {
721 if (isBundle())
722 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
723 return isCandidateForCallSiteEntry();
724 }
725
getNumExplicitOperands() const726 unsigned MachineInstr::getNumExplicitOperands() const {
727 unsigned NumOperands = MCID->getNumOperands();
728 if (!MCID->isVariadic())
729 return NumOperands;
730
731 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
732 const MachineOperand &MO = getOperand(I);
733 // The operands must always be in the following order:
734 // - explicit reg defs,
735 // - other explicit operands (reg uses, immediates, etc.),
736 // - implicit reg defs
737 // - implicit reg uses
738 if (MO.isReg() && MO.isImplicit())
739 break;
740 ++NumOperands;
741 }
742 return NumOperands;
743 }
744
getNumExplicitDefs() const745 unsigned MachineInstr::getNumExplicitDefs() const {
746 unsigned NumDefs = MCID->getNumDefs();
747 if (!MCID->isVariadic())
748 return NumDefs;
749
750 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
751 const MachineOperand &MO = getOperand(I);
752 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
753 break;
754 ++NumDefs;
755 }
756 return NumDefs;
757 }
758
bundleWithPred()759 void MachineInstr::bundleWithPred() {
760 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
761 setFlag(BundledPred);
762 MachineBasicBlock::instr_iterator Pred = getIterator();
763 --Pred;
764 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
765 Pred->setFlag(BundledSucc);
766 }
767
bundleWithSucc()768 void MachineInstr::bundleWithSucc() {
769 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
770 setFlag(BundledSucc);
771 MachineBasicBlock::instr_iterator Succ = getIterator();
772 ++Succ;
773 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
774 Succ->setFlag(BundledPred);
775 }
776
unbundleFromPred()777 void MachineInstr::unbundleFromPred() {
778 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
779 clearFlag(BundledPred);
780 MachineBasicBlock::instr_iterator Pred = getIterator();
781 --Pred;
782 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
783 Pred->clearFlag(BundledSucc);
784 }
785
unbundleFromSucc()786 void MachineInstr::unbundleFromSucc() {
787 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
788 clearFlag(BundledSucc);
789 MachineBasicBlock::instr_iterator Succ = getIterator();
790 ++Succ;
791 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
792 Succ->clearFlag(BundledPred);
793 }
794
isStackAligningInlineAsm() const795 bool MachineInstr::isStackAligningInlineAsm() const {
796 if (isInlineAsm()) {
797 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
798 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
799 return true;
800 }
801 return false;
802 }
803
getInlineAsmDialect() const804 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
805 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
806 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
807 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
808 }
809
findInlineAsmFlagIdx(unsigned OpIdx,unsigned * GroupNo) const810 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
811 unsigned *GroupNo) const {
812 assert(isInlineAsm() && "Expected an inline asm instruction");
813 assert(OpIdx < getNumOperands() && "OpIdx out of range");
814
815 // Ignore queries about the initial operands.
816 if (OpIdx < InlineAsm::MIOp_FirstOperand)
817 return -1;
818
819 unsigned Group = 0;
820 unsigned NumOps;
821 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
822 i += NumOps) {
823 const MachineOperand &FlagMO = getOperand(i);
824 // If we reach the implicit register operands, stop looking.
825 if (!FlagMO.isImm())
826 return -1;
827 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
828 if (i + NumOps > OpIdx) {
829 if (GroupNo)
830 *GroupNo = Group;
831 return i;
832 }
833 ++Group;
834 }
835 return -1;
836 }
837
getDebugLabel() const838 const DILabel *MachineInstr::getDebugLabel() const {
839 assert(isDebugLabel() && "not a DBG_LABEL");
840 return cast<DILabel>(getOperand(0).getMetadata());
841 }
842
getDebugVariableOp() const843 const MachineOperand &MachineInstr::getDebugVariableOp() const {
844 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
845 return getOperand(2);
846 }
847
getDebugVariableOp()848 MachineOperand &MachineInstr::getDebugVariableOp() {
849 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
850 return getOperand(2);
851 }
852
getDebugVariable() const853 const DILocalVariable *MachineInstr::getDebugVariable() const {
854 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
855 return cast<DILocalVariable>(getOperand(2).getMetadata());
856 }
857
getDebugExpressionOp()858 MachineOperand &MachineInstr::getDebugExpressionOp() {
859 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
860 return getOperand(3);
861 }
862
getDebugExpression() const863 const DIExpression *MachineInstr::getDebugExpression() const {
864 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE");
865 return cast<DIExpression>(getOperand(3).getMetadata());
866 }
867
isDebugEntryValue() const868 bool MachineInstr::isDebugEntryValue() const {
869 return isDebugValue() && getDebugExpression()->isEntryValue();
870 }
871
872 const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const873 MachineInstr::getRegClassConstraint(unsigned OpIdx,
874 const TargetInstrInfo *TII,
875 const TargetRegisterInfo *TRI) const {
876 assert(getParent() && "Can't have an MBB reference here!");
877 assert(getMF() && "Can't have an MF reference here!");
878 const MachineFunction &MF = *getMF();
879
880 // Most opcodes have fixed constraints in their MCInstrDesc.
881 if (!isInlineAsm())
882 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
883
884 if (!getOperand(OpIdx).isReg())
885 return nullptr;
886
887 // For tied uses on inline asm, get the constraint from the def.
888 unsigned DefIdx;
889 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
890 OpIdx = DefIdx;
891
892 // Inline asm stores register class constraints in the flag word.
893 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
894 if (FlagIdx < 0)
895 return nullptr;
896
897 unsigned Flag = getOperand(FlagIdx).getImm();
898 unsigned RCID;
899 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
900 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
901 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
902 InlineAsm::hasRegClassConstraint(Flag, RCID))
903 return TRI->getRegClass(RCID);
904
905 // Assume that all registers in a memory operand are pointers.
906 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
907 return TRI->getPointerRegClass(MF);
908
909 return nullptr;
910 }
911
getRegClassConstraintEffectForVReg(Register Reg,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI,bool ExploreBundle) const912 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
913 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
914 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
915 // Check every operands inside the bundle if we have
916 // been asked to.
917 if (ExploreBundle)
918 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
919 ++OpndIt)
920 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
921 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
922 else
923 // Otherwise, just check the current operands.
924 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
925 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
926 return CurRC;
927 }
928
getRegClassConstraintEffectForVRegImpl(unsigned OpIdx,Register Reg,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const929 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
930 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
931 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
932 assert(CurRC && "Invalid initial register class");
933 // Check if Reg is constrained by some of its use/def from MI.
934 const MachineOperand &MO = getOperand(OpIdx);
935 if (!MO.isReg() || MO.getReg() != Reg)
936 return CurRC;
937 // If yes, accumulate the constraints through the operand.
938 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
939 }
940
getRegClassConstraintEffect(unsigned OpIdx,const TargetRegisterClass * CurRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI) const941 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
942 unsigned OpIdx, const TargetRegisterClass *CurRC,
943 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
944 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
945 const MachineOperand &MO = getOperand(OpIdx);
946 assert(MO.isReg() &&
947 "Cannot get register constraints for non-register operand");
948 assert(CurRC && "Invalid initial register class");
949 if (unsigned SubIdx = MO.getSubReg()) {
950 if (OpRC)
951 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
952 else
953 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
954 } else if (OpRC)
955 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
956 return CurRC;
957 }
958
959 /// Return the number of instructions inside the MI bundle, not counting the
960 /// header instruction.
getBundleSize() const961 unsigned MachineInstr::getBundleSize() const {
962 MachineBasicBlock::const_instr_iterator I = getIterator();
963 unsigned Size = 0;
964 while (I->isBundledWithSucc()) {
965 ++Size;
966 ++I;
967 }
968 return Size;
969 }
970
971 /// Returns true if the MachineInstr has an implicit-use operand of exactly
972 /// the given register (not considering sub/super-registers).
hasRegisterImplicitUseOperand(Register Reg) const973 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
974 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
975 const MachineOperand &MO = getOperand(i);
976 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
977 return true;
978 }
979 return false;
980 }
981
982 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
983 /// the specific register or -1 if it is not found. It further tightens
984 /// the search criteria to a use that kills the register if isKill is true.
findRegisterUseOperandIdx(Register Reg,bool isKill,const TargetRegisterInfo * TRI) const985 int MachineInstr::findRegisterUseOperandIdx(
986 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
987 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
988 const MachineOperand &MO = getOperand(i);
989 if (!MO.isReg() || !MO.isUse())
990 continue;
991 Register MOReg = MO.getReg();
992 if (!MOReg)
993 continue;
994 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
995 if (!isKill || MO.isKill())
996 return i;
997 }
998 return -1;
999 }
1000
1001 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1002 /// indicating if this instruction reads or writes Reg. This also considers
1003 /// partial defines.
1004 std::pair<bool,bool>
readsWritesVirtualRegister(Register Reg,SmallVectorImpl<unsigned> * Ops) const1005 MachineInstr::readsWritesVirtualRegister(Register Reg,
1006 SmallVectorImpl<unsigned> *Ops) const {
1007 bool PartDef = false; // Partial redefine.
1008 bool FullDef = false; // Full define.
1009 bool Use = false;
1010
1011 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1012 const MachineOperand &MO = getOperand(i);
1013 if (!MO.isReg() || MO.getReg() != Reg)
1014 continue;
1015 if (Ops)
1016 Ops->push_back(i);
1017 if (MO.isUse())
1018 Use |= !MO.isUndef();
1019 else if (MO.getSubReg() && !MO.isUndef())
1020 // A partial def undef doesn't count as reading the register.
1021 PartDef = true;
1022 else
1023 FullDef = true;
1024 }
1025 // A partial redefine uses Reg unless there is also a full define.
1026 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1027 }
1028
1029 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1030 /// the specified register or -1 if it is not found. If isDead is true, defs
1031 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1032 /// also checks if there is a def of a super-register.
1033 int
findRegisterDefOperandIdx(Register Reg,bool isDead,bool Overlap,const TargetRegisterInfo * TRI) const1034 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1035 const TargetRegisterInfo *TRI) const {
1036 bool isPhys = Register::isPhysicalRegister(Reg);
1037 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1038 const MachineOperand &MO = getOperand(i);
1039 // Accept regmask operands when Overlap is set.
1040 // Ignore them when looking for a specific def operand (Overlap == false).
1041 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1042 return i;
1043 if (!MO.isReg() || !MO.isDef())
1044 continue;
1045 Register MOReg = MO.getReg();
1046 bool Found = (MOReg == Reg);
1047 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1048 if (Overlap)
1049 Found = TRI->regsOverlap(MOReg, Reg);
1050 else
1051 Found = TRI->isSubRegister(MOReg, Reg);
1052 }
1053 if (Found && (!isDead || MO.isDead()))
1054 return i;
1055 }
1056 return -1;
1057 }
1058
1059 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1060 /// operand list that is used to represent the predicate. It returns -1 if
1061 /// none is found.
findFirstPredOperandIdx() const1062 int MachineInstr::findFirstPredOperandIdx() const {
1063 // Don't call MCID.findFirstPredOperandIdx() because this variant
1064 // is sometimes called on an instruction that's not yet complete, and
1065 // so the number of operands is less than the MCID indicates. In
1066 // particular, the PTX target does this.
1067 const MCInstrDesc &MCID = getDesc();
1068 if (MCID.isPredicable()) {
1069 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1070 if (MCID.OpInfo[i].isPredicate())
1071 return i;
1072 }
1073
1074 return -1;
1075 }
1076
1077 // MachineOperand::TiedTo is 4 bits wide.
1078 const unsigned TiedMax = 15;
1079
1080 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1081 ///
1082 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1083 /// field. TiedTo can have these values:
1084 ///
1085 /// 0: Operand is not tied to anything.
1086 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1087 /// TiedMax: Tied to an operand >= TiedMax-1.
1088 ///
1089 /// The tied def must be one of the first TiedMax operands on a normal
1090 /// instruction. INLINEASM instructions allow more tied defs.
1091 ///
tieOperands(unsigned DefIdx,unsigned UseIdx)1092 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1093 MachineOperand &DefMO = getOperand(DefIdx);
1094 MachineOperand &UseMO = getOperand(UseIdx);
1095 assert(DefMO.isDef() && "DefIdx must be a def operand");
1096 assert(UseMO.isUse() && "UseIdx must be a use operand");
1097 assert(!DefMO.isTied() && "Def is already tied to another use");
1098 assert(!UseMO.isTied() && "Use is already tied to another def");
1099
1100 if (DefIdx < TiedMax)
1101 UseMO.TiedTo = DefIdx + 1;
1102 else {
1103 // Inline asm can use the group descriptors to find tied operands,
1104 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1105 // but on normal instruction, the tied def must be within the first TiedMax
1106 // operands.
1107 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1108 "DefIdx out of range");
1109 UseMO.TiedTo = TiedMax;
1110 }
1111
1112 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1113 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1114 }
1115
1116 /// Given the index of a tied register operand, find the operand it is tied to.
1117 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1118 /// which must exist.
findTiedOperandIdx(unsigned OpIdx) const1119 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1120 const MachineOperand &MO = getOperand(OpIdx);
1121 assert(MO.isTied() && "Operand isn't tied");
1122
1123 // Normally TiedTo is in range.
1124 if (MO.TiedTo < TiedMax)
1125 return MO.TiedTo - 1;
1126
1127 // Uses on normal instructions can be out of range.
1128 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1129 // Normal tied defs must be in the 0..TiedMax-1 range.
1130 if (MO.isUse())
1131 return TiedMax - 1;
1132 // MO is a def. Search for the tied use.
1133 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1134 const MachineOperand &UseMO = getOperand(i);
1135 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1136 return i;
1137 }
1138 llvm_unreachable("Can't find tied use");
1139 }
1140
1141 if (getOpcode() == TargetOpcode::STATEPOINT) {
1142 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1143 // on registers.
1144 StatepointOpers SO(this);
1145 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1146 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1147 unsigned NumDefs = getNumDefs();
1148 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1149 while (!getOperand(CurUseIdx).isReg())
1150 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1151 if (OpIdx == CurDefIdx)
1152 return CurUseIdx;
1153 if (OpIdx == CurUseIdx)
1154 return CurDefIdx;
1155 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1156 }
1157 llvm_unreachable("Can't find tied use");
1158 }
1159
1160 // Now deal with inline asm by parsing the operand group descriptor flags.
1161 // Find the beginning of each operand group.
1162 SmallVector<unsigned, 8> GroupIdx;
1163 unsigned OpIdxGroup = ~0u;
1164 unsigned NumOps;
1165 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1166 i += NumOps) {
1167 const MachineOperand &FlagMO = getOperand(i);
1168 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1169 unsigned CurGroup = GroupIdx.size();
1170 GroupIdx.push_back(i);
1171 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1172 // OpIdx belongs to this operand group.
1173 if (OpIdx > i && OpIdx < i + NumOps)
1174 OpIdxGroup = CurGroup;
1175 unsigned TiedGroup;
1176 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1177 continue;
1178 // Operands in this group are tied to operands in TiedGroup which must be
1179 // earlier. Find the number of operands between the two groups.
1180 unsigned Delta = i - GroupIdx[TiedGroup];
1181
1182 // OpIdx is a use tied to TiedGroup.
1183 if (OpIdxGroup == CurGroup)
1184 return OpIdx - Delta;
1185
1186 // OpIdx is a def tied to this use group.
1187 if (OpIdxGroup == TiedGroup)
1188 return OpIdx + Delta;
1189 }
1190 llvm_unreachable("Invalid tied operand on inline asm");
1191 }
1192
1193 /// clearKillInfo - Clears kill flags on all operands.
1194 ///
clearKillInfo()1195 void MachineInstr::clearKillInfo() {
1196 for (MachineOperand &MO : operands()) {
1197 if (MO.isReg() && MO.isUse())
1198 MO.setIsKill(false);
1199 }
1200 }
1201
substituteRegister(Register FromReg,Register ToReg,unsigned SubIdx,const TargetRegisterInfo & RegInfo)1202 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1203 unsigned SubIdx,
1204 const TargetRegisterInfo &RegInfo) {
1205 if (Register::isPhysicalRegister(ToReg)) {
1206 if (SubIdx)
1207 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1208 for (MachineOperand &MO : operands()) {
1209 if (!MO.isReg() || MO.getReg() != FromReg)
1210 continue;
1211 MO.substPhysReg(ToReg, RegInfo);
1212 }
1213 } else {
1214 for (MachineOperand &MO : operands()) {
1215 if (!MO.isReg() || MO.getReg() != FromReg)
1216 continue;
1217 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1218 }
1219 }
1220 }
1221
1222 /// isSafeToMove - Return true if it is safe to move this instruction. If
1223 /// SawStore is set to true, it means that there is a store (or call) between
1224 /// the instruction's location and its intended destination.
isSafeToMove(AAResults * AA,bool & SawStore) const1225 bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1226 // Ignore stuff that we obviously can't move.
1227 //
1228 // Treat volatile loads as stores. This is not strictly necessary for
1229 // volatiles, but it is required for atomic loads. It is not allowed to move
1230 // a load across an atomic load with Ordering > Monotonic.
1231 if (mayStore() || isCall() || isPHI() ||
1232 (mayLoad() && hasOrderedMemoryRef())) {
1233 SawStore = true;
1234 return false;
1235 }
1236
1237 if (isPosition() || isDebugInstr() || isTerminator() ||
1238 mayRaiseFPException() || hasUnmodeledSideEffects())
1239 return false;
1240
1241 // See if this instruction does a load. If so, we have to guarantee that the
1242 // loaded value doesn't change between the load and the its intended
1243 // destination. The check for isInvariantLoad gives the target the chance to
1244 // classify the load as always returning a constant, e.g. a constant pool
1245 // load.
1246 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1247 // Otherwise, this is a real load. If there is a store between the load and
1248 // end of block, we can't move it.
1249 return !SawStore;
1250
1251 return true;
1252 }
1253
MemOperandsHaveAlias(const MachineFrameInfo & MFI,AAResults * AA,bool UseTBAA,const MachineMemOperand * MMOa,const MachineMemOperand * MMOb)1254 static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1255 bool UseTBAA, const MachineMemOperand *MMOa,
1256 const MachineMemOperand *MMOb) {
1257 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1258 // operates with MachineMemOperand offset with some important assumptions:
1259 // - LLVM fundamentally assumes flat address spaces.
1260 // - MachineOperand offset can *only* result from legalization and cannot
1261 // affect queries other than the trivial case of overlap checking.
1262 // - These offsets never wrap and never step outside of allocated objects.
1263 // - There should never be any negative offsets here.
1264 //
1265 // FIXME: Modify API to hide this math from "user"
1266 // Even before we go to AA we can reason locally about some memory objects. It
1267 // can save compile time, and possibly catch some corner cases not currently
1268 // covered.
1269
1270 int64_t OffsetA = MMOa->getOffset();
1271 int64_t OffsetB = MMOb->getOffset();
1272 int64_t MinOffset = std::min(OffsetA, OffsetB);
1273
1274 uint64_t WidthA = MMOa->getSize();
1275 uint64_t WidthB = MMOb->getSize();
1276 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1277 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1278
1279 const Value *ValA = MMOa->getValue();
1280 const Value *ValB = MMOb->getValue();
1281 bool SameVal = (ValA && ValB && (ValA == ValB));
1282 if (!SameVal) {
1283 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1284 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1285 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1286 return false;
1287 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1288 return false;
1289 if (PSVa && PSVb && (PSVa == PSVb))
1290 SameVal = true;
1291 }
1292
1293 if (SameVal) {
1294 if (!KnownWidthA || !KnownWidthB)
1295 return true;
1296 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1297 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1298 return (MinOffset + LowWidth > MaxOffset);
1299 }
1300
1301 if (!AA)
1302 return true;
1303
1304 if (!ValA || !ValB)
1305 return true;
1306
1307 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1308 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1309
1310 int64_t OverlapA =
1311 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1312 int64_t OverlapB =
1313 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1314
1315 AliasResult AAResult = AA->alias(
1316 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1317 MemoryLocation(ValB, OverlapB,
1318 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1319
1320 return (AAResult != NoAlias);
1321 }
1322
mayAlias(AAResults * AA,const MachineInstr & Other,bool UseTBAA) const1323 bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1324 bool UseTBAA) const {
1325 const MachineFunction *MF = getMF();
1326 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1327 const MachineFrameInfo &MFI = MF->getFrameInfo();
1328
1329 // Exclude call instruction which may alter the memory but can not be handled
1330 // by this function.
1331 if (isCall() || Other.isCall())
1332 return true;
1333
1334 // If neither instruction stores to memory, they can't alias in any
1335 // meaningful way, even if they read from the same address.
1336 if (!mayStore() && !Other.mayStore())
1337 return false;
1338
1339 // Both instructions must be memory operations to be able to alias.
1340 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1341 return false;
1342
1343 // Let the target decide if memory accesses cannot possibly overlap.
1344 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1345 return false;
1346
1347 // Memory operations without memory operands may access anything. Be
1348 // conservative and assume `MayAlias`.
1349 if (memoperands_empty() || Other.memoperands_empty())
1350 return true;
1351
1352 // Skip if there are too many memory operands.
1353 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1354 if (NumChecks > TII->getMemOperandAACheckLimit())
1355 return true;
1356
1357 // Check each pair of memory operands from both instructions, which can't
1358 // alias only if all pairs won't alias.
1359 for (auto *MMOa : memoperands())
1360 for (auto *MMOb : Other.memoperands())
1361 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1362 return true;
1363
1364 return false;
1365 }
1366
1367 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1368 /// or volatile memory reference, or if the information describing the memory
1369 /// reference is not available. Return false if it is known to have no ordered
1370 /// memory references.
hasOrderedMemoryRef() const1371 bool MachineInstr::hasOrderedMemoryRef() const {
1372 // An instruction known never to access memory won't have a volatile access.
1373 if (!mayStore() &&
1374 !mayLoad() &&
1375 !isCall() &&
1376 !hasUnmodeledSideEffects())
1377 return false;
1378
1379 // Otherwise, if the instruction has no memory reference information,
1380 // conservatively assume it wasn't preserved.
1381 if (memoperands_empty())
1382 return true;
1383
1384 // Check if any of our memory operands are ordered.
1385 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1386 return !MMO->isUnordered();
1387 });
1388 }
1389
1390 /// isDereferenceableInvariantLoad - Return true if this instruction will never
1391 /// trap and is loading from a location whose value is invariant across a run of
1392 /// this function.
isDereferenceableInvariantLoad(AAResults * AA) const1393 bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1394 // If the instruction doesn't load at all, it isn't an invariant load.
1395 if (!mayLoad())
1396 return false;
1397
1398 // If the instruction has lost its memoperands, conservatively assume that
1399 // it may not be an invariant load.
1400 if (memoperands_empty())
1401 return false;
1402
1403 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1404
1405 for (MachineMemOperand *MMO : memoperands()) {
1406 if (!MMO->isUnordered())
1407 // If the memory operand has ordering side effects, we can't move the
1408 // instruction. Such an instruction is technically an invariant load,
1409 // but the caller code would need updated to expect that.
1410 return false;
1411 if (MMO->isStore()) return false;
1412 if (MMO->isInvariant() && MMO->isDereferenceable())
1413 continue;
1414
1415 // A load from a constant PseudoSourceValue is invariant.
1416 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1417 if (PSV->isConstant(&MFI))
1418 continue;
1419
1420 if (const Value *V = MMO->getValue()) {
1421 // If we have an AliasAnalysis, ask it whether the memory is constant.
1422 if (AA &&
1423 AA->pointsToConstantMemory(
1424 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1425 continue;
1426 }
1427
1428 // Otherwise assume conservatively.
1429 return false;
1430 }
1431
1432 // Everything checks out.
1433 return true;
1434 }
1435
1436 /// isConstantValuePHI - If the specified instruction is a PHI that always
1437 /// merges together the same virtual register, return the register, otherwise
1438 /// return 0.
isConstantValuePHI() const1439 unsigned MachineInstr::isConstantValuePHI() const {
1440 if (!isPHI())
1441 return 0;
1442 assert(getNumOperands() >= 3 &&
1443 "It's illegal to have a PHI without source operands");
1444
1445 Register Reg = getOperand(1).getReg();
1446 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1447 if (getOperand(i).getReg() != Reg)
1448 return 0;
1449 return Reg;
1450 }
1451
hasUnmodeledSideEffects() const1452 bool MachineInstr::hasUnmodeledSideEffects() const {
1453 if (hasProperty(MCID::UnmodeledSideEffects))
1454 return true;
1455 if (isInlineAsm()) {
1456 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1457 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1458 return true;
1459 }
1460
1461 return false;
1462 }
1463
isLoadFoldBarrier() const1464 bool MachineInstr::isLoadFoldBarrier() const {
1465 return mayStore() || isCall() ||
1466 (hasUnmodeledSideEffects() && !isPseudoProbe());
1467 }
1468
1469 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1470 ///
allDefsAreDead() const1471 bool MachineInstr::allDefsAreDead() const {
1472 for (const MachineOperand &MO : operands()) {
1473 if (!MO.isReg() || MO.isUse())
1474 continue;
1475 if (!MO.isDead())
1476 return false;
1477 }
1478 return true;
1479 }
1480
1481 /// copyImplicitOps - Copy implicit register operands from specified
1482 /// instruction to this instruction.
copyImplicitOps(MachineFunction & MF,const MachineInstr & MI)1483 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1484 const MachineInstr &MI) {
1485 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1486 i != e; ++i) {
1487 const MachineOperand &MO = MI.getOperand(i);
1488 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1489 addOperand(MF, MO);
1490 }
1491 }
1492
hasComplexRegisterTies() const1493 bool MachineInstr::hasComplexRegisterTies() const {
1494 const MCInstrDesc &MCID = getDesc();
1495 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1496 return true;
1497 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1498 const auto &Operand = getOperand(I);
1499 if (!Operand.isReg() || Operand.isDef())
1500 // Ignore the defined registers as MCID marks only the uses as tied.
1501 continue;
1502 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1503 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1504 if (ExpectedTiedIdx != TiedIdx)
1505 return true;
1506 }
1507 return false;
1508 }
1509
getTypeToPrint(unsigned OpIdx,SmallBitVector & PrintedTypes,const MachineRegisterInfo & MRI) const1510 LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1511 const MachineRegisterInfo &MRI) const {
1512 const MachineOperand &Op = getOperand(OpIdx);
1513 if (!Op.isReg())
1514 return LLT{};
1515
1516 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1517 return MRI.getType(Op.getReg());
1518
1519 auto &OpInfo = getDesc().OpInfo[OpIdx];
1520 if (!OpInfo.isGenericType())
1521 return MRI.getType(Op.getReg());
1522
1523 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1524 return LLT{};
1525
1526 LLT TypeToPrint = MRI.getType(Op.getReg());
1527 // Don't mark the type index printed if it wasn't actually printed: maybe
1528 // another operand with the same type index has an actual type attached:
1529 if (TypeToPrint.isValid())
1530 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1531 return TypeToPrint;
1532 }
1533
1534 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump() const1535 LLVM_DUMP_METHOD void MachineInstr::dump() const {
1536 dbgs() << " ";
1537 print(dbgs());
1538 }
1539
dumprImpl(const MachineRegisterInfo & MRI,unsigned Depth,unsigned MaxDepth,SmallPtrSetImpl<const MachineInstr * > & AlreadySeenInstrs) const1540 LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1541 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1542 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1543 if (Depth >= MaxDepth)
1544 return;
1545 if (!AlreadySeenInstrs.insert(this).second)
1546 return;
1547 // PadToColumn always inserts at least one space.
1548 // Don't mess up the alignment if we don't want any space.
1549 if (Depth)
1550 fdbgs().PadToColumn(Depth * 2);
1551 print(fdbgs());
1552 for (const MachineOperand &MO : operands()) {
1553 if (!MO.isReg() || MO.isDef())
1554 continue;
1555 Register Reg = MO.getReg();
1556 if (Reg.isPhysical())
1557 continue;
1558 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1559 if (NewMI == nullptr)
1560 continue;
1561 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1562 }
1563 }
1564
dumpr(const MachineRegisterInfo & MRI,unsigned MaxDepth) const1565 LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1566 unsigned MaxDepth) const {
1567 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1568 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1569 }
1570 #endif
1571
print(raw_ostream & OS,bool IsStandalone,bool SkipOpers,bool SkipDebugLoc,bool AddNewLine,const TargetInstrInfo * TII) const1572 void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1573 bool SkipDebugLoc, bool AddNewLine,
1574 const TargetInstrInfo *TII) const {
1575 const Module *M = nullptr;
1576 const Function *F = nullptr;
1577 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1578 F = &MF->getFunction();
1579 M = F->getParent();
1580 if (!TII)
1581 TII = MF->getSubtarget().getInstrInfo();
1582 }
1583
1584 ModuleSlotTracker MST(M);
1585 if (F)
1586 MST.incorporateFunction(*F);
1587 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1588 }
1589
print(raw_ostream & OS,ModuleSlotTracker & MST,bool IsStandalone,bool SkipOpers,bool SkipDebugLoc,bool AddNewLine,const TargetInstrInfo * TII) const1590 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1591 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1592 bool AddNewLine, const TargetInstrInfo *TII) const {
1593 // We can be a bit tidier if we know the MachineFunction.
1594 const TargetRegisterInfo *TRI = nullptr;
1595 const MachineRegisterInfo *MRI = nullptr;
1596 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1597 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1598
1599 if (isCFIInstruction())
1600 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1601
1602 SmallBitVector PrintedTypes(8);
1603 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1604 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1605 if (!ShouldPrintRegisterTies)
1606 return 0U;
1607 const MachineOperand &MO = getOperand(OpIdx);
1608 if (MO.isReg() && MO.isTied() && !MO.isDef())
1609 return findTiedOperandIdx(OpIdx);
1610 return 0U;
1611 };
1612 unsigned StartOp = 0;
1613 unsigned e = getNumOperands();
1614
1615 // Print explicitly defined operands on the left of an assignment syntax.
1616 while (StartOp < e) {
1617 const MachineOperand &MO = getOperand(StartOp);
1618 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1619 break;
1620
1621 if (StartOp != 0)
1622 OS << ", ";
1623
1624 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1625 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1626 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1627 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1628 ++StartOp;
1629 }
1630
1631 if (StartOp != 0)
1632 OS << " = ";
1633
1634 if (getFlag(MachineInstr::FrameSetup))
1635 OS << "frame-setup ";
1636 if (getFlag(MachineInstr::FrameDestroy))
1637 OS << "frame-destroy ";
1638 if (getFlag(MachineInstr::FmNoNans))
1639 OS << "nnan ";
1640 if (getFlag(MachineInstr::FmNoInfs))
1641 OS << "ninf ";
1642 if (getFlag(MachineInstr::FmNsz))
1643 OS << "nsz ";
1644 if (getFlag(MachineInstr::FmArcp))
1645 OS << "arcp ";
1646 if (getFlag(MachineInstr::FmContract))
1647 OS << "contract ";
1648 if (getFlag(MachineInstr::FmAfn))
1649 OS << "afn ";
1650 if (getFlag(MachineInstr::FmReassoc))
1651 OS << "reassoc ";
1652 if (getFlag(MachineInstr::NoUWrap))
1653 OS << "nuw ";
1654 if (getFlag(MachineInstr::NoSWrap))
1655 OS << "nsw ";
1656 if (getFlag(MachineInstr::IsExact))
1657 OS << "exact ";
1658 if (getFlag(MachineInstr::NoFPExcept))
1659 OS << "nofpexcept ";
1660 if (getFlag(MachineInstr::NoMerge))
1661 OS << "nomerge ";
1662
1663 // Print the opcode name.
1664 if (TII)
1665 OS << TII->getName(getOpcode());
1666 else
1667 OS << "UNKNOWN";
1668
1669 if (SkipOpers)
1670 return;
1671
1672 // Print the rest of the operands.
1673 bool FirstOp = true;
1674 unsigned AsmDescOp = ~0u;
1675 unsigned AsmOpCount = 0;
1676
1677 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1678 // Print asm string.
1679 OS << " ";
1680 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1681 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1682 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1683 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1684 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1685 IntrinsicInfo);
1686
1687 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1688 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1689 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1690 OS << " [sideeffect]";
1691 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1692 OS << " [mayload]";
1693 if (ExtraInfo & InlineAsm::Extra_MayStore)
1694 OS << " [maystore]";
1695 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1696 OS << " [isconvergent]";
1697 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1698 OS << " [alignstack]";
1699 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1700 OS << " [attdialect]";
1701 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1702 OS << " [inteldialect]";
1703
1704 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1705 FirstOp = false;
1706 }
1707
1708 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1709 const MachineOperand &MO = getOperand(i);
1710
1711 if (FirstOp) FirstOp = false; else OS << ",";
1712 OS << " ";
1713
1714 if (isDebugValue() && MO.isMetadata()) {
1715 // Pretty print DBG_VALUE instructions.
1716 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1717 if (DIV && !DIV->getName().empty())
1718 OS << "!\"" << DIV->getName() << '\"';
1719 else {
1720 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1721 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1722 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1723 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1724 }
1725 } else if (isDebugLabel() && MO.isMetadata()) {
1726 // Pretty print DBG_LABEL instructions.
1727 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1728 if (DIL && !DIL->getName().empty())
1729 OS << "\"" << DIL->getName() << '\"';
1730 else {
1731 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1732 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1733 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1734 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1735 }
1736 } else if (i == AsmDescOp && MO.isImm()) {
1737 // Pretty print the inline asm operand descriptor.
1738 OS << '$' << AsmOpCount++;
1739 unsigned Flag = MO.getImm();
1740 OS << ":[";
1741 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1742
1743 unsigned RCID = 0;
1744 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1745 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1746 if (TRI) {
1747 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1748 } else
1749 OS << ":RC" << RCID;
1750 }
1751
1752 if (InlineAsm::isMemKind(Flag)) {
1753 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1754 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1755 }
1756
1757 unsigned TiedTo = 0;
1758 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1759 OS << " tiedto:$" << TiedTo;
1760
1761 OS << ']';
1762
1763 // Compute the index of the next operand descriptor.
1764 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1765 } else {
1766 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1767 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1768 if (MO.isImm() && isOperandSubregIdx(i))
1769 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1770 else
1771 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1772 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1773 }
1774 }
1775
1776 // Print any optional symbols attached to this instruction as-if they were
1777 // operands.
1778 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1779 if (!FirstOp) {
1780 FirstOp = false;
1781 OS << ',';
1782 }
1783 OS << " pre-instr-symbol ";
1784 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1785 }
1786 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1787 if (!FirstOp) {
1788 FirstOp = false;
1789 OS << ',';
1790 }
1791 OS << " post-instr-symbol ";
1792 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1793 }
1794 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1795 if (!FirstOp) {
1796 FirstOp = false;
1797 OS << ',';
1798 }
1799 OS << " heap-alloc-marker ";
1800 HeapAllocMarker->printAsOperand(OS, MST);
1801 }
1802
1803 if (DebugInstrNum) {
1804 if (!FirstOp)
1805 OS << ",";
1806 OS << " debug-instr-number " << DebugInstrNum;
1807 }
1808
1809 if (!SkipDebugLoc) {
1810 if (const DebugLoc &DL = getDebugLoc()) {
1811 if (!FirstOp)
1812 OS << ',';
1813 OS << " debug-location ";
1814 DL->printAsOperand(OS, MST);
1815 }
1816 }
1817
1818 if (!memoperands_empty()) {
1819 SmallVector<StringRef, 0> SSNs;
1820 const LLVMContext *Context = nullptr;
1821 std::unique_ptr<LLVMContext> CtxPtr;
1822 const MachineFrameInfo *MFI = nullptr;
1823 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1824 MFI = &MF->getFrameInfo();
1825 Context = &MF->getFunction().getContext();
1826 } else {
1827 CtxPtr = std::make_unique<LLVMContext>();
1828 Context = CtxPtr.get();
1829 }
1830
1831 OS << " :: ";
1832 bool NeedComma = false;
1833 for (const MachineMemOperand *Op : memoperands()) {
1834 if (NeedComma)
1835 OS << ", ";
1836 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1837 NeedComma = true;
1838 }
1839 }
1840
1841 if (SkipDebugLoc)
1842 return;
1843
1844 bool HaveSemi = false;
1845
1846 // Print debug location information.
1847 if (const DebugLoc &DL = getDebugLoc()) {
1848 if (!HaveSemi) {
1849 OS << ';';
1850 HaveSemi = true;
1851 }
1852 OS << ' ';
1853 DL.print(OS);
1854 }
1855
1856 // Print extra comments for DEBUG_VALUE.
1857 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1858 if (!HaveSemi) {
1859 OS << ";";
1860 HaveSemi = true;
1861 }
1862 auto *DV = getDebugVariable();
1863 OS << " line no:" << DV->getLine();
1864 if (isIndirectDebugValue())
1865 OS << " indirect";
1866 }
1867 // TODO: DBG_LABEL
1868
1869 if (AddNewLine)
1870 OS << '\n';
1871 }
1872
addRegisterKilled(Register IncomingReg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1873 bool MachineInstr::addRegisterKilled(Register IncomingReg,
1874 const TargetRegisterInfo *RegInfo,
1875 bool AddIfNotFound) {
1876 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1877 bool hasAliases = isPhysReg &&
1878 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1879 bool Found = false;
1880 SmallVector<unsigned,4> DeadOps;
1881 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1882 MachineOperand &MO = getOperand(i);
1883 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1884 continue;
1885
1886 // DEBUG_VALUE nodes do not contribute to code generation and should
1887 // always be ignored. Failure to do so may result in trying to modify
1888 // KILL flags on DEBUG_VALUE nodes.
1889 if (MO.isDebug())
1890 continue;
1891
1892 Register Reg = MO.getReg();
1893 if (!Reg)
1894 continue;
1895
1896 if (Reg == IncomingReg) {
1897 if (!Found) {
1898 if (MO.isKill())
1899 // The register is already marked kill.
1900 return true;
1901 if (isPhysReg && isRegTiedToDefOperand(i))
1902 // Two-address uses of physregs must not be marked kill.
1903 return true;
1904 MO.setIsKill();
1905 Found = true;
1906 }
1907 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1908 // A super-register kill already exists.
1909 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1910 return true;
1911 if (RegInfo->isSubRegister(IncomingReg, Reg))
1912 DeadOps.push_back(i);
1913 }
1914 }
1915
1916 // Trim unneeded kill operands.
1917 while (!DeadOps.empty()) {
1918 unsigned OpIdx = DeadOps.back();
1919 if (getOperand(OpIdx).isImplicit() &&
1920 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1921 RemoveOperand(OpIdx);
1922 else
1923 getOperand(OpIdx).setIsKill(false);
1924 DeadOps.pop_back();
1925 }
1926
1927 // If not found, this means an alias of one of the operands is killed. Add a
1928 // new implicit operand if required.
1929 if (!Found && AddIfNotFound) {
1930 addOperand(MachineOperand::CreateReg(IncomingReg,
1931 false /*IsDef*/,
1932 true /*IsImp*/,
1933 true /*IsKill*/));
1934 return true;
1935 }
1936 return Found;
1937 }
1938
clearRegisterKills(Register Reg,const TargetRegisterInfo * RegInfo)1939 void MachineInstr::clearRegisterKills(Register Reg,
1940 const TargetRegisterInfo *RegInfo) {
1941 if (!Register::isPhysicalRegister(Reg))
1942 RegInfo = nullptr;
1943 for (MachineOperand &MO : operands()) {
1944 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1945 continue;
1946 Register OpReg = MO.getReg();
1947 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1948 MO.setIsKill(false);
1949 }
1950 }
1951
addRegisterDead(Register Reg,const TargetRegisterInfo * RegInfo,bool AddIfNotFound)1952 bool MachineInstr::addRegisterDead(Register Reg,
1953 const TargetRegisterInfo *RegInfo,
1954 bool AddIfNotFound) {
1955 bool isPhysReg = Register::isPhysicalRegister(Reg);
1956 bool hasAliases = isPhysReg &&
1957 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1958 bool Found = false;
1959 SmallVector<unsigned,4> DeadOps;
1960 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1961 MachineOperand &MO = getOperand(i);
1962 if (!MO.isReg() || !MO.isDef())
1963 continue;
1964 Register MOReg = MO.getReg();
1965 if (!MOReg)
1966 continue;
1967
1968 if (MOReg == Reg) {
1969 MO.setIsDead();
1970 Found = true;
1971 } else if (hasAliases && MO.isDead() &&
1972 Register::isPhysicalRegister(MOReg)) {
1973 // There exists a super-register that's marked dead.
1974 if (RegInfo->isSuperRegister(Reg, MOReg))
1975 return true;
1976 if (RegInfo->isSubRegister(Reg, MOReg))
1977 DeadOps.push_back(i);
1978 }
1979 }
1980
1981 // Trim unneeded dead operands.
1982 while (!DeadOps.empty()) {
1983 unsigned OpIdx = DeadOps.back();
1984 if (getOperand(OpIdx).isImplicit() &&
1985 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1986 RemoveOperand(OpIdx);
1987 else
1988 getOperand(OpIdx).setIsDead(false);
1989 DeadOps.pop_back();
1990 }
1991
1992 // If not found, this means an alias of one of the operands is dead. Add a
1993 // new implicit operand if required.
1994 if (Found || !AddIfNotFound)
1995 return Found;
1996
1997 addOperand(MachineOperand::CreateReg(Reg,
1998 true /*IsDef*/,
1999 true /*IsImp*/,
2000 false /*IsKill*/,
2001 true /*IsDead*/));
2002 return true;
2003 }
2004
clearRegisterDeads(Register Reg)2005 void MachineInstr::clearRegisterDeads(Register Reg) {
2006 for (MachineOperand &MO : operands()) {
2007 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2008 continue;
2009 MO.setIsDead(false);
2010 }
2011 }
2012
setRegisterDefReadUndef(Register Reg,bool IsUndef)2013 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2014 for (MachineOperand &MO : operands()) {
2015 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2016 continue;
2017 MO.setIsUndef(IsUndef);
2018 }
2019 }
2020
addRegisterDefined(Register Reg,const TargetRegisterInfo * RegInfo)2021 void MachineInstr::addRegisterDefined(Register Reg,
2022 const TargetRegisterInfo *RegInfo) {
2023 if (Register::isPhysicalRegister(Reg)) {
2024 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2025 if (MO)
2026 return;
2027 } else {
2028 for (const MachineOperand &MO : operands()) {
2029 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2030 MO.getSubReg() == 0)
2031 return;
2032 }
2033 }
2034 addOperand(MachineOperand::CreateReg(Reg,
2035 true /*IsDef*/,
2036 true /*IsImp*/));
2037 }
2038
setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,const TargetRegisterInfo & TRI)2039 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2040 const TargetRegisterInfo &TRI) {
2041 bool HasRegMask = false;
2042 for (MachineOperand &MO : operands()) {
2043 if (MO.isRegMask()) {
2044 HasRegMask = true;
2045 continue;
2046 }
2047 if (!MO.isReg() || !MO.isDef()) continue;
2048 Register Reg = MO.getReg();
2049 if (!Reg.isPhysical())
2050 continue;
2051 // If there are no uses, including partial uses, the def is dead.
2052 if (llvm::none_of(UsedRegs,
2053 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2054 MO.setIsDead();
2055 }
2056
2057 // This is a call with a register mask operand.
2058 // Mask clobbers are always dead, so add defs for the non-dead defines.
2059 if (HasRegMask)
2060 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2061 I != E; ++I)
2062 addRegisterDefined(*I, &TRI);
2063 }
2064
2065 unsigned
getHashValue(const MachineInstr * const & MI)2066 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2067 // Build up a buffer of hash code components.
2068 SmallVector<size_t, 16> HashComponents;
2069 HashComponents.reserve(MI->getNumOperands() + 1);
2070 HashComponents.push_back(MI->getOpcode());
2071 for (const MachineOperand &MO : MI->operands()) {
2072 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2073 continue; // Skip virtual register defs.
2074
2075 HashComponents.push_back(hash_value(MO));
2076 }
2077 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2078 }
2079
emitError(StringRef Msg) const2080 void MachineInstr::emitError(StringRef Msg) const {
2081 // Find the source location cookie.
2082 unsigned LocCookie = 0;
2083 const MDNode *LocMD = nullptr;
2084 for (unsigned i = getNumOperands(); i != 0; --i) {
2085 if (getOperand(i-1).isMetadata() &&
2086 (LocMD = getOperand(i-1).getMetadata()) &&
2087 LocMD->getNumOperands() != 0) {
2088 if (const ConstantInt *CI =
2089 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2090 LocCookie = CI->getZExtValue();
2091 break;
2092 }
2093 }
2094 }
2095
2096 if (const MachineBasicBlock *MBB = getParent())
2097 if (const MachineFunction *MF = MBB->getParent())
2098 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2099 report_fatal_error(Msg);
2100 }
2101
BuildMI(MachineFunction & MF,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,Register Reg,const MDNode * Variable,const MDNode * Expr)2102 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2103 const MCInstrDesc &MCID, bool IsIndirect,
2104 Register Reg, const MDNode *Variable,
2105 const MDNode *Expr) {
2106 assert(isa<DILocalVariable>(Variable) && "not a variable");
2107 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2108 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2109 "Expected inlined-at fields to agree");
2110 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2111 if (IsIndirect)
2112 MIB.addImm(0U);
2113 else
2114 MIB.addReg(0U, RegState::Debug);
2115 return MIB.addMetadata(Variable).addMetadata(Expr);
2116 }
2117
BuildMI(MachineFunction & MF,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,MachineOperand & MO,const MDNode * Variable,const MDNode * Expr)2118 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2119 const MCInstrDesc &MCID, bool IsIndirect,
2120 MachineOperand &MO, const MDNode *Variable,
2121 const MDNode *Expr) {
2122 assert(isa<DILocalVariable>(Variable) && "not a variable");
2123 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2124 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2125 "Expected inlined-at fields to agree");
2126 if (MO.isReg())
2127 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2128
2129 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2130 if (IsIndirect)
2131 MIB.addImm(0U);
2132 else
2133 MIB.addReg(0U, RegState::Debug);
2134 return MIB.addMetadata(Variable).addMetadata(Expr);
2135 }
2136
BuildMI(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,Register Reg,const MDNode * Variable,const MDNode * Expr)2137 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2138 MachineBasicBlock::iterator I,
2139 const DebugLoc &DL, const MCInstrDesc &MCID,
2140 bool IsIndirect, Register Reg,
2141 const MDNode *Variable, const MDNode *Expr) {
2142 MachineFunction &MF = *BB.getParent();
2143 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2144 BB.insert(I, MI);
2145 return MachineInstrBuilder(MF, MI);
2146 }
2147
BuildMI(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const DebugLoc & DL,const MCInstrDesc & MCID,bool IsIndirect,MachineOperand & MO,const MDNode * Variable,const MDNode * Expr)2148 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2149 MachineBasicBlock::iterator I,
2150 const DebugLoc &DL, const MCInstrDesc &MCID,
2151 bool IsIndirect, MachineOperand &MO,
2152 const MDNode *Variable, const MDNode *Expr) {
2153 MachineFunction &MF = *BB.getParent();
2154 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2155 BB.insert(I, MI);
2156 return MachineInstrBuilder(MF, *MI);
2157 }
2158
2159 /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2160 /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
computeExprForSpill(const MachineInstr & MI)2161 static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2162 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2163 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2164 "Expected inlined-at fields to agree");
2165
2166 const DIExpression *Expr = MI.getDebugExpression();
2167 if (MI.isIndirectDebugValue()) {
2168 assert(MI.getDebugOffset().getImm() == 0 &&
2169 "DBG_VALUE with nonzero offset");
2170 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2171 }
2172 return Expr;
2173 }
2174
buildDbgValueForSpill(MachineBasicBlock & BB,MachineBasicBlock::iterator I,const MachineInstr & Orig,int FrameIndex)2175 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2176 MachineBasicBlock::iterator I,
2177 const MachineInstr &Orig,
2178 int FrameIndex) {
2179 const DIExpression *Expr = computeExprForSpill(Orig);
2180 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2181 .addFrameIndex(FrameIndex)
2182 .addImm(0U)
2183 .addMetadata(Orig.getDebugVariable())
2184 .addMetadata(Expr);
2185 }
2186
updateDbgValueForSpill(MachineInstr & Orig,int FrameIndex)2187 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2188 const DIExpression *Expr = computeExprForSpill(Orig);
2189 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
2190 Orig.getDebugOffset().ChangeToImmediate(0U);
2191 Orig.getDebugExpressionOp().setMetadata(Expr);
2192 }
2193
collectDebugValues(SmallVectorImpl<MachineInstr * > & DbgValues)2194 void MachineInstr::collectDebugValues(
2195 SmallVectorImpl<MachineInstr *> &DbgValues) {
2196 MachineInstr &MI = *this;
2197 if (!MI.getOperand(0).isReg())
2198 return;
2199
2200 MachineBasicBlock::iterator DI = MI; ++DI;
2201 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2202 DI != DE; ++DI) {
2203 if (!DI->isDebugValue())
2204 return;
2205 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
2206 DbgValues.push_back(&*DI);
2207 }
2208 }
2209
changeDebugValuesDefReg(Register Reg)2210 void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2211 // Collect matching debug values.
2212 SmallVector<MachineInstr *, 2> DbgValues;
2213
2214 if (!getOperand(0).isReg())
2215 return;
2216
2217 Register DefReg = getOperand(0).getReg();
2218 auto *MRI = getRegInfo();
2219 for (auto &MO : MRI->use_operands(DefReg)) {
2220 auto *DI = MO.getParent();
2221 if (!DI->isDebugValue())
2222 continue;
2223 if (DI->getDebugOperandForReg(DefReg)) {
2224 DbgValues.push_back(DI);
2225 }
2226 }
2227
2228 // Propagate Reg to debug value instructions.
2229 for (auto *DBI : DbgValues)
2230 DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
2231 }
2232
2233 using MMOList = SmallVector<const MachineMemOperand *, 2>;
2234
getSpillSlotSize(const MMOList & Accesses,const MachineFrameInfo & MFI)2235 static unsigned getSpillSlotSize(const MMOList &Accesses,
2236 const MachineFrameInfo &MFI) {
2237 unsigned Size = 0;
2238 for (auto A : Accesses)
2239 if (MFI.isSpillSlotObjectIndex(
2240 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2241 ->getFrameIndex()))
2242 Size += A->getSize();
2243 return Size;
2244 }
2245
2246 Optional<unsigned>
getSpillSize(const TargetInstrInfo * TII) const2247 MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2248 int FI;
2249 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2250 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2251 if (MFI.isSpillSlotObjectIndex(FI))
2252 return (*memoperands_begin())->getSize();
2253 }
2254 return None;
2255 }
2256
2257 Optional<unsigned>
getFoldedSpillSize(const TargetInstrInfo * TII) const2258 MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2259 MMOList Accesses;
2260 if (TII->hasStoreToStackSlot(*this, Accesses))
2261 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2262 return None;
2263 }
2264
2265 Optional<unsigned>
getRestoreSize(const TargetInstrInfo * TII) const2266 MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2267 int FI;
2268 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2269 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2270 if (MFI.isSpillSlotObjectIndex(FI))
2271 return (*memoperands_begin())->getSize();
2272 }
2273 return None;
2274 }
2275
2276 Optional<unsigned>
getFoldedRestoreSize(const TargetInstrInfo * TII) const2277 MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2278 MMOList Accesses;
2279 if (TII->hasLoadFromStackSlot(*this, Accesses))
2280 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2281 return None;
2282 }
2283
getDebugInstrNum()2284 unsigned MachineInstr::getDebugInstrNum() {
2285 if (DebugInstrNum == 0)
2286 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2287 return DebugInstrNum;
2288 }
2289