1//=----- AArch64InstrGISel.td - AArch64 GISel target pseudos -*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// AArch64 GlobalISel target pseudo instruction definitions. This is kept
10// separately from the other tablegen files for organizational purposes, but
11// share the same infrastructure.
12//
13//===----------------------------------------------------------------------===//
14
15
16class AArch64GenericInstruction : GenericInstruction {
17  let Namespace = "AArch64";
18}
19
20// A pseudo to represent a relocatable add instruction as part of address
21// computation.
22def G_ADD_LOW : AArch64GenericInstruction {
23  let OutOperandList = (outs type0:$dst);
24  let InOperandList = (ins type1:$src, type2:$imm);
25  let hasSideEffects = 0;
26}
27
28// Pseudo for a rev16 instruction. Produced post-legalization from
29// G_SHUFFLE_VECTORs with appropriate masks.
30def G_REV16 : AArch64GenericInstruction {
31  let OutOperandList = (outs type0:$dst);
32  let InOperandList = (ins type0:$src);
33  let hasSideEffects = 0;
34}
35
36// Pseudo for a rev32 instruction. Produced post-legalization from
37// G_SHUFFLE_VECTORs with appropriate masks.
38def G_REV32 : AArch64GenericInstruction {
39  let OutOperandList = (outs type0:$dst);
40  let InOperandList = (ins type0:$src);
41  let hasSideEffects = 0;
42}
43
44// Pseudo for a rev64 instruction. Produced post-legalization from
45// G_SHUFFLE_VECTORs with appropriate masks.
46def G_REV64 : AArch64GenericInstruction {
47  let OutOperandList = (outs type0:$dst);
48  let InOperandList = (ins type0:$src);
49  let hasSideEffects = 0;
50}
51
52// Represents an uzp1 instruction. Produced post-legalization from
53// G_SHUFFLE_VECTORs with appropriate masks.
54def G_UZP1 : AArch64GenericInstruction {
55  let OutOperandList = (outs type0:$dst);
56  let InOperandList = (ins type0:$v1, type0:$v2);
57  let hasSideEffects = 0;
58}
59
60// Represents an uzp2 instruction. Produced post-legalization from
61// G_SHUFFLE_VECTORs with appropriate masks.
62def G_UZP2 : AArch64GenericInstruction {
63  let OutOperandList = (outs type0:$dst);
64  let InOperandList = (ins type0:$v1, type0:$v2);
65  let hasSideEffects = 0;
66}
67
68// Represents a zip1 instruction. Produced post-legalization from
69// G_SHUFFLE_VECTORs with appropriate masks.
70def G_ZIP1 : AArch64GenericInstruction {
71  let OutOperandList = (outs type0:$dst);
72  let InOperandList = (ins type0:$v1, type0:$v2);
73  let hasSideEffects = 0;
74}
75
76// Represents a zip2 instruction. Produced post-legalization from
77// G_SHUFFLE_VECTORs with appropriate masks.
78def G_ZIP2 : AArch64GenericInstruction {
79  let OutOperandList = (outs type0:$dst);
80  let InOperandList = (ins type0:$v1, type0:$v2);
81  let hasSideEffects = 0;
82}
83
84// Represents a dup instruction. Produced post-legalization from
85// G_SHUFFLE_VECTORs with appropriate masks.
86def G_DUP: AArch64GenericInstruction {
87  let OutOperandList = (outs type0:$dst);
88  let InOperandList = (ins type1:$lane);
89  let hasSideEffects = 0;
90}
91
92// Represents a lane duplicate operation.
93def G_DUPLANE8 : AArch64GenericInstruction {
94  let OutOperandList = (outs type0:$dst);
95  let InOperandList = (ins type0:$src, type1:$lane);
96  let hasSideEffects = 0;
97}
98def G_DUPLANE16 : AArch64GenericInstruction {
99  let OutOperandList = (outs type0:$dst);
100  let InOperandList = (ins type0:$src, type1:$lane);
101  let hasSideEffects = 0;
102}
103def G_DUPLANE32 : AArch64GenericInstruction {
104  let OutOperandList = (outs type0:$dst);
105  let InOperandList = (ins type0:$src, type1:$lane);
106  let hasSideEffects = 0;
107}
108def G_DUPLANE64 : AArch64GenericInstruction {
109  let OutOperandList = (outs type0:$dst);
110  let InOperandList = (ins type0:$src, type1:$lane);
111  let hasSideEffects = 0;
112}
113
114// Represents a trn1 instruction. Produced post-legalization from
115// G_SHUFFLE_VECTORs with appropriate masks.
116def G_TRN1 : AArch64GenericInstruction {
117  let OutOperandList = (outs type0:$dst);
118  let InOperandList = (ins type0:$v1, type0:$v2);
119  let hasSideEffects = 0;
120}
121
122// Represents a trn2 instruction. Produced post-legalization from
123// G_SHUFFLE_VECTORs with appropriate masks.
124def G_TRN2 : AArch64GenericInstruction {
125  let OutOperandList = (outs type0:$dst);
126  let InOperandList = (ins type0:$v1, type0:$v2);
127  let hasSideEffects = 0;
128}
129
130// Represents an ext instruction. Produced post-legalization from
131// G_SHUFFLE_VECTORs with appropriate masks.
132def G_EXT: AArch64GenericInstruction {
133  let OutOperandList = (outs type0:$dst);
134  let InOperandList = (ins type0:$v1, type0:$v2, untyped_imm_0:$imm);
135}
136
137// Represents a vector G_ASHR with an immediate.
138def G_VASHR : AArch64GenericInstruction {
139  let OutOperandList = (outs type0:$dst);
140  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
141}
142
143// Represents a vector G_LSHR with an immediate.
144def G_VLSHR : AArch64GenericInstruction {
145  let OutOperandList = (outs type0:$dst);
146  let InOperandList = (ins type0:$src1, untyped_imm_0:$imm);
147}
148
149// Represents an integer to FP conversion on the FPR bank.
150def G_SITOF : AArch64GenericInstruction {
151  let OutOperandList = (outs type0:$dst);
152  let InOperandList = (ins type0:$src);
153}
154def G_UITOF : AArch64GenericInstruction {
155  let OutOperandList = (outs type0:$dst);
156  let InOperandList = (ins type0:$src);
157}
158
159def : GINodeEquiv<G_REV16, AArch64rev16>;
160def : GINodeEquiv<G_REV32, AArch64rev32>;
161def : GINodeEquiv<G_REV64, AArch64rev64>;
162def : GINodeEquiv<G_UZP1, AArch64uzp1>;
163def : GINodeEquiv<G_UZP2, AArch64uzp2>;
164def : GINodeEquiv<G_ZIP1, AArch64zip1>;
165def : GINodeEquiv<G_ZIP2, AArch64zip2>;
166def : GINodeEquiv<G_DUP, AArch64dup>;
167def : GINodeEquiv<G_DUPLANE8, AArch64duplane8>;
168def : GINodeEquiv<G_DUPLANE16, AArch64duplane16>;
169def : GINodeEquiv<G_DUPLANE32, AArch64duplane32>;
170def : GINodeEquiv<G_DUPLANE64, AArch64duplane64>;
171def : GINodeEquiv<G_TRN1, AArch64trn1>;
172def : GINodeEquiv<G_TRN2, AArch64trn2>;
173def : GINodeEquiv<G_EXT, AArch64ext>;
174def : GINodeEquiv<G_VASHR, AArch64vashr>;
175def : GINodeEquiv<G_VLSHR, AArch64vlshr>;
176def : GINodeEquiv<G_SITOF, AArch64sitof>;
177def : GINodeEquiv<G_UITOF, AArch64uitof>;
178
179def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, vector_extract>;
180
181// These are patterns that we only use for GlobalISel via the importer.
182def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
183                     (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
184           (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
185