1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an AArch64 MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AArch64InstPrinter.h"
14 #include "MCTargetDesc/AArch64AddressingModes.h"
15 #include "Utils/AArch64BaseInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Casting.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/Format.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <string>
32
33 using namespace llvm;
34
35 #define DEBUG_TYPE "asm-printer"
36
37 #define GET_INSTRUCTION_NAME
38 #define PRINT_ALIAS_INSTR
39 #include "AArch64GenAsmWriter.inc"
40 #define GET_INSTRUCTION_NAME
41 #define PRINT_ALIAS_INSTR
42 #include "AArch64GenAsmWriter1.inc"
43
AArch64InstPrinter(const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)44 AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
45 const MCInstrInfo &MII,
46 const MCRegisterInfo &MRI)
47 : MCInstPrinter(MAI, MII, MRI) {}
48
AArch64AppleInstPrinter(const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)49 AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
50 const MCInstrInfo &MII,
51 const MCRegisterInfo &MRI)
52 : AArch64InstPrinter(MAI, MII, MRI) {}
53
printRegName(raw_ostream & OS,unsigned RegNo) const54 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
55 // This is for .cfi directives.
56 OS << getRegisterName(RegNo);
57 }
58
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)59 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
60 StringRef Annot, const MCSubtargetInfo &STI,
61 raw_ostream &O) {
62 // Check for special encodings and print the canonical alias instead.
63
64 unsigned Opcode = MI->getOpcode();
65
66 if (Opcode == AArch64::SYSxt)
67 if (printSysAlias(MI, STI, O)) {
68 printAnnotation(O, Annot);
69 return;
70 }
71
72 // SBFM/UBFM should print to a nicer aliased form if possible.
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
75 const MCOperand &Op0 = MI->getOperand(0);
76 const MCOperand &Op1 = MI->getOperand(1);
77 const MCOperand &Op2 = MI->getOperand(2);
78 const MCOperand &Op3 = MI->getOperand(3);
79
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
83 const char *AsmMnemonic = nullptr;
84
85 switch (Op3.getImm()) {
86 default:
87 break;
88 case 7:
89 if (IsSigned)
90 AsmMnemonic = "sxtb";
91 else if (!Is64Bit)
92 AsmMnemonic = "uxtb";
93 break;
94 case 15:
95 if (IsSigned)
96 AsmMnemonic = "sxth";
97 else if (!Is64Bit)
98 AsmMnemonic = "uxth";
99 break;
100 case 31:
101 // *xtw is only valid for signed 64-bit operations.
102 if (Is64Bit && IsSigned)
103 AsmMnemonic = "sxtw";
104 break;
105 }
106
107 if (AsmMnemonic) {
108 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
109 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
110 printAnnotation(O, Annot);
111 return;
112 }
113 }
114
115 // All immediate shifts are aliases, implemented using the Bitfield
116 // instruction. In all cases the immediate shift amount shift must be in
117 // the range 0 to (reg.size -1).
118 if (Op2.isImm() && Op3.isImm()) {
119 const char *AsmMnemonic = nullptr;
120 int shift = 0;
121 int64_t immr = Op2.getImm();
122 int64_t imms = Op3.getImm();
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
124 AsmMnemonic = "lsl";
125 shift = 31 - imms;
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
127 ((imms + 1 == immr))) {
128 AsmMnemonic = "lsl";
129 shift = 63 - imms;
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
131 AsmMnemonic = "lsr";
132 shift = immr;
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
134 AsmMnemonic = "lsr";
135 shift = immr;
136 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
137 AsmMnemonic = "asr";
138 shift = immr;
139 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
140 AsmMnemonic = "asr";
141 shift = immr;
142 }
143 if (AsmMnemonic) {
144 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
145 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
146 printAnnotation(O, Annot);
147 return;
148 }
149 }
150
151 // SBFIZ/UBFIZ aliases
152 if (Op2.getImm() > Op3.getImm()) {
153 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
154 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
156 printAnnotation(O, Annot);
157 return;
158 }
159
160 // Otherwise SBFX/UBFX is the preferred form
161 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
162 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
164 printAnnotation(O, Annot);
165 return;
166 }
167
168 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
169 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
170 const MCOperand &Op2 = MI->getOperand(2);
171 int ImmR = MI->getOperand(3).getImm();
172 int ImmS = MI->getOperand(4).getImm();
173
174 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
175 (ImmR == 0 || ImmS < ImmR) &&
176 STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
177 // BFC takes precedence over its entire range, sligtly differently to BFI.
178 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
179 int LSB = (BitWidth - ImmR) % BitWidth;
180 int Width = ImmS + 1;
181
182 O << "\tbfc\t" << getRegisterName(Op0.getReg())
183 << ", #" << LSB << ", #" << Width;
184 printAnnotation(O, Annot);
185 return;
186 } else if (ImmS < ImmR) {
187 // BFI alias
188 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
189 int LSB = (BitWidth - ImmR) % BitWidth;
190 int Width = ImmS + 1;
191
192 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
193 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
194 printAnnotation(O, Annot);
195 return;
196 }
197
198 int LSB = ImmR;
199 int Width = ImmS - ImmR + 1;
200 // Otherwise BFXIL the preferred form
201 O << "\tbfxil\t"
202 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
203 << ", #" << LSB << ", #" << Width;
204 printAnnotation(O, Annot);
205 return;
206 }
207
208 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
209 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
210 // printed.
211 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
212 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
213 MI->getOperand(1).isExpr()) {
214 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
215 O << "\tmovz\t";
216 else
217 O << "\tmovn\t";
218
219 O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
220 MI->getOperand(1).getExpr()->print(O, &MAI);
221 return;
222 }
223
224 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
225 MI->getOperand(2).isExpr()) {
226 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
227 MI->getOperand(2).getExpr()->print(O, &MAI);
228 return;
229 }
230
231 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
232 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
233 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
234 // that can represent the move is the MOV alias, and the rest get printed
235 // normally.
236 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
237 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
239 int Shift = MI->getOperand(2).getImm();
240 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
241
242 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
243 Opcode == AArch64::MOVZXi ? 64 : 32)) {
244 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
245 << formatImm(SignExtend64(Value, RegWidth));
246 return;
247 }
248 }
249
250 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
251 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
253 int Shift = MI->getOperand(2).getImm();
254 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
255 if (RegWidth == 32)
256 Value = Value & 0xffffffff;
257
258 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
259 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
260 << formatImm(SignExtend64(Value, RegWidth));
261 return;
262 }
263 }
264
265 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
266 (MI->getOperand(1).getReg() == AArch64::XZR ||
267 MI->getOperand(1).getReg() == AArch64::WZR) &&
268 MI->getOperand(2).isImm()) {
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
270 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
271 MI->getOperand(2).getImm(), RegWidth);
272 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
273 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
274 << formatImm(SignExtend64(Value, RegWidth));
275 return;
276 }
277 }
278
279 if (Opcode == AArch64::CompilerBarrier) {
280 O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
281 printAnnotation(O, Annot);
282 return;
283 }
284
285 if (Opcode == AArch64::SPACE) {
286 O << '\t' << MAI.getCommentString() << " SPACE "
287 << MI->getOperand(1).getImm();
288 printAnnotation(O, Annot);
289 return;
290 }
291
292 // Instruction TSB is specified as a one operand instruction, but 'csync' is
293 // not encoded, so for printing it is treated as a special case here:
294 if (Opcode == AArch64::TSB) {
295 O << "\ttsb\tcsync";
296 return;
297 }
298
299 if (!printAliasInstr(MI, Address, STI, O))
300 printInstruction(MI, Address, STI, O);
301
302 printAnnotation(O, Annot);
303
304 if (atomicBarrierDroppedOnZero(Opcode) &&
305 (MI->getOperand(0).getReg() == AArch64::XZR ||
306 MI->getOperand(0).getReg() == AArch64::WZR)) {
307 printAnnotation(O, "acquire semantics dropped since destination is zero");
308 }
309 }
310
isTblTbxInstruction(unsigned Opcode,StringRef & Layout,bool & IsTbx)311 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
312 bool &IsTbx) {
313 switch (Opcode) {
314 case AArch64::TBXv8i8One:
315 case AArch64::TBXv8i8Two:
316 case AArch64::TBXv8i8Three:
317 case AArch64::TBXv8i8Four:
318 IsTbx = true;
319 Layout = ".8b";
320 return true;
321 case AArch64::TBLv8i8One:
322 case AArch64::TBLv8i8Two:
323 case AArch64::TBLv8i8Three:
324 case AArch64::TBLv8i8Four:
325 IsTbx = false;
326 Layout = ".8b";
327 return true;
328 case AArch64::TBXv16i8One:
329 case AArch64::TBXv16i8Two:
330 case AArch64::TBXv16i8Three:
331 case AArch64::TBXv16i8Four:
332 IsTbx = true;
333 Layout = ".16b";
334 return true;
335 case AArch64::TBLv16i8One:
336 case AArch64::TBLv16i8Two:
337 case AArch64::TBLv16i8Three:
338 case AArch64::TBLv16i8Four:
339 IsTbx = false;
340 Layout = ".16b";
341 return true;
342 default:
343 return false;
344 }
345 }
346
347 struct LdStNInstrDesc {
348 unsigned Opcode;
349 const char *Mnemonic;
350 const char *Layout;
351 int ListOperand;
352 bool HasLane;
353 int NaturalOffset;
354 };
355
356 static const LdStNInstrDesc LdStNInstInfo[] = {
357 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
358 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
359 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
360 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
361 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
362 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
363 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
364 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
365 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
366 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
367 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
368 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
369 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
370 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
371 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
372 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
373 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
374 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
375 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
376 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
377 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
378 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
379 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
380 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
381 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
382 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
383 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
384 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
385 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
386 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
387 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
388 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
389 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
390 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
391 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
392 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
393 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
394 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
395 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
396 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
397 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
398 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
399 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
400 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
401 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
402 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
403 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
404 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
405 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
406 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
407 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
408 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
409 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
410 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
411 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
412 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
413 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
414 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
415 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
416 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
417 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
418 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
419 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
420 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
421 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
422 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
423 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
424 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
425 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
426 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
427 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
428 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
429 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
430 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
431 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
432 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
433 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
434 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
435 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
436 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
437 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
438 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
439 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
440 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
441 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
442 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
443 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
444 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
445 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
446 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
447 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
448 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
449 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
450 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
451 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
452 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
453 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
454 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
455 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
456 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
457 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
458 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
459 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
460 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
461 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
462 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
463 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
464 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
465 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
466 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
467 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
468 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
469 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
470 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
471 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
472 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
473 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
474 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
475 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
476 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
477 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
478 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
479 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
480 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
481 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
482 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
483 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
484 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
485 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
486 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
487 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
488 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
489 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
490 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
491 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
492 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
493 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
494 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
495 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
496 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
497 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
498 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
499 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
500 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
501 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
502 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
503 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
504 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
505 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
506 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
507 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
508 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
509 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
510 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
511 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
512 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
513 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
514 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
515 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
516 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
517 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
518 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
519 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
520 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
521 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
522 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
523 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
524 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
525 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
526 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
527 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
528 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
529 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
530 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
531 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
532 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
533 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
534 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
535 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
536 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
537 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
538 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
539 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
540 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
541 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
542 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
543 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
544 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
545 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
546 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
547 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
548 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
549 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
550 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
551 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
552 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
553 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
554 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
555 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
556 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
557 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
558 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
559 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
560 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
561 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
562 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
563 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
564 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
565 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
566 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
567 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
568 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
569 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
570 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
571 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
572 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
573 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
574 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
575 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
576 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
577 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
578 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
579 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
580 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
581 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
582 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
583 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
584 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
585 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
586 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
587 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
588 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
589 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
590 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
591 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
592 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
593 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
594 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
595 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
596 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
597 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
598 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
599 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
600 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
601 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
602 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
603 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
604 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
605 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
606 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
607 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
608 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
609 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
610 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
611 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
612 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
613 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
614 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
615 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
616 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
617 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
618 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
619 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
620 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
621 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
622 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
623 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
624 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
625 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
626 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
627 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
628 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
629 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
630 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
631 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
632 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
633 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
634 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
635 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
636 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
637 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
638 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
639 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
640 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
641 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
642 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
643 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
644 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
645 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
646 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
647 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
648 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
649 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
650 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
651 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
652 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
653 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
654 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
655 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
656 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
657 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
658 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
659 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
660 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
661 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
662 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
663 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
664 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
665 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
666 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
667 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
668 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
669 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
670 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
671 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
672 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
673 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
674 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
675 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
676 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
677 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
678 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
679 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
680 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
681 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
682 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
683 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
684 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
685 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
686 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
687 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
688 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
689 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
690 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
691 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
692 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
693 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
694 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
695 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
696 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
697 };
698
getLdStNInstrDesc(unsigned Opcode)699 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
700 unsigned Idx;
701 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
702 if (LdStNInstInfo[Idx].Opcode == Opcode)
703 return &LdStNInstInfo[Idx];
704
705 return nullptr;
706 }
707
printInst(const MCInst * MI,uint64_t Address,StringRef Annot,const MCSubtargetInfo & STI,raw_ostream & O)708 void AArch64AppleInstPrinter::printInst(const MCInst *MI, uint64_t Address,
709 StringRef Annot,
710 const MCSubtargetInfo &STI,
711 raw_ostream &O) {
712 unsigned Opcode = MI->getOpcode();
713 StringRef Layout;
714
715 bool IsTbx;
716 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
717 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
718 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
719
720 unsigned ListOpNum = IsTbx ? 2 : 1;
721 printVectorList(MI, ListOpNum, STI, O, "");
722
723 O << ", "
724 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
725 printAnnotation(O, Annot);
726 return;
727 }
728
729 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
730 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
731
732 // Now onto the operands: first a vector list with possible lane
733 // specifier. E.g. { v0 }[2]
734 int OpNum = LdStDesc->ListOperand;
735 printVectorList(MI, OpNum++, STI, O, "");
736
737 if (LdStDesc->HasLane)
738 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
739
740 // Next the address: [xN]
741 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
742 O << ", [" << getRegisterName(AddrReg) << ']';
743
744 // Finally, there might be a post-indexed offset.
745 if (LdStDesc->NaturalOffset != 0) {
746 unsigned Reg = MI->getOperand(OpNum++).getReg();
747 if (Reg != AArch64::XZR)
748 O << ", " << getRegisterName(Reg);
749 else {
750 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
751 O << ", #" << LdStDesc->NaturalOffset;
752 }
753 }
754
755 printAnnotation(O, Annot);
756 return;
757 }
758
759 AArch64InstPrinter::printInst(MI, Address, Annot, STI, O);
760 }
761
printSysAlias(const MCInst * MI,const MCSubtargetInfo & STI,raw_ostream & O)762 bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
763 const MCSubtargetInfo &STI,
764 raw_ostream &O) {
765 #ifndef NDEBUG
766 unsigned Opcode = MI->getOpcode();
767 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
768 #endif
769
770 const MCOperand &Op1 = MI->getOperand(0);
771 const MCOperand &Cn = MI->getOperand(1);
772 const MCOperand &Cm = MI->getOperand(2);
773 const MCOperand &Op2 = MI->getOperand(3);
774
775 unsigned Op1Val = Op1.getImm();
776 unsigned CnVal = Cn.getImm();
777 unsigned CmVal = Cm.getImm();
778 unsigned Op2Val = Op2.getImm();
779
780 uint16_t Encoding = Op2Val;
781 Encoding |= CmVal << 3;
782 Encoding |= CnVal << 7;
783 Encoding |= Op1Val << 11;
784
785 bool NeedsReg;
786 std::string Ins;
787 std::string Name;
788
789 if (CnVal == 7) {
790 switch (CmVal) {
791 default: return false;
792 // Maybe IC, maybe Prediction Restriction
793 case 1:
794 switch (Op1Val) {
795 default: return false;
796 case 0: goto Search_IC;
797 case 3: goto Search_PRCTX;
798 }
799 // Prediction Restriction aliases
800 case 3: {
801 Search_PRCTX:
802 const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByEncoding(Encoding >> 3);
803 if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits()))
804 return false;
805
806 NeedsReg = PRCTX->NeedsReg;
807 switch (Op2Val) {
808 default: return false;
809 case 4: Ins = "cfp\t"; break;
810 case 5: Ins = "dvp\t"; break;
811 case 7: Ins = "cpp\t"; break;
812 }
813 Name = std::string(PRCTX->Name);
814 }
815 break;
816 // IC aliases
817 case 5: {
818 Search_IC:
819 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
820 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
821 return false;
822
823 NeedsReg = IC->NeedsReg;
824 Ins = "ic\t";
825 Name = std::string(IC->Name);
826 }
827 break;
828 // DC aliases
829 case 4: case 6: case 10: case 11: case 12: case 13: case 14:
830 {
831 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
832 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
833 return false;
834
835 NeedsReg = true;
836 Ins = "dc\t";
837 Name = std::string(DC->Name);
838 }
839 break;
840 // AT aliases
841 case 8: case 9: {
842 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
843 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
844 return false;
845
846 NeedsReg = true;
847 Ins = "at\t";
848 Name = std::string(AT->Name);
849 }
850 break;
851 }
852 } else if (CnVal == 8 || CnVal == 9) {
853 // TLBI aliases
854 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
855 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
856 return false;
857
858 NeedsReg = TLBI->NeedsReg;
859 Ins = "tlbi\t";
860 Name = std::string(TLBI->Name);
861 }
862 else
863 return false;
864
865 std::string Str = Ins + Name;
866 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
867
868 O << '\t' << Str;
869 if (NeedsReg)
870 O << ", " << getRegisterName(MI->getOperand(4).getReg());
871
872 return true;
873 }
874
printOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)875 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
876 const MCSubtargetInfo &STI,
877 raw_ostream &O) {
878 const MCOperand &Op = MI->getOperand(OpNo);
879 if (Op.isReg()) {
880 unsigned Reg = Op.getReg();
881 O << getRegisterName(Reg);
882 } else if (Op.isImm()) {
883 printImm(MI, OpNo, STI, O);
884 } else {
885 assert(Op.isExpr() && "unknown operand kind in printOperand");
886 Op.getExpr()->print(O, &MAI);
887 }
888 }
889
printImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)890 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
891 const MCSubtargetInfo &STI,
892 raw_ostream &O) {
893 const MCOperand &Op = MI->getOperand(OpNo);
894 O << "#" << formatImm(Op.getImm());
895 }
896
printImmHex(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)897 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
898 const MCSubtargetInfo &STI,
899 raw_ostream &O) {
900 const MCOperand &Op = MI->getOperand(OpNo);
901 O << format("#%#llx", Op.getImm());
902 }
903
904 template<int Size>
printSImm(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)905 void AArch64InstPrinter::printSImm(const MCInst *MI, unsigned OpNo,
906 const MCSubtargetInfo &STI,
907 raw_ostream &O) {
908 const MCOperand &Op = MI->getOperand(OpNo);
909 if (Size == 8)
910 O << "#" << formatImm((signed char)Op.getImm());
911 else if (Size == 16)
912 O << "#" << formatImm((signed short)Op.getImm());
913 else
914 O << "#" << formatImm(Op.getImm());
915 }
916
printPostIncOperand(const MCInst * MI,unsigned OpNo,unsigned Imm,raw_ostream & O)917 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
918 unsigned Imm, raw_ostream &O) {
919 const MCOperand &Op = MI->getOperand(OpNo);
920 if (Op.isReg()) {
921 unsigned Reg = Op.getReg();
922 if (Reg == AArch64::XZR)
923 O << "#" << Imm;
924 else
925 O << getRegisterName(Reg);
926 } else
927 llvm_unreachable("unknown operand kind in printPostIncOperand64");
928 }
929
printVRegOperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)930 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
931 const MCSubtargetInfo &STI,
932 raw_ostream &O) {
933 const MCOperand &Op = MI->getOperand(OpNo);
934 assert(Op.isReg() && "Non-register vreg operand!");
935 unsigned Reg = Op.getReg();
936 O << getRegisterName(Reg, AArch64::vreg);
937 }
938
printSysCROperand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)939 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
940 const MCSubtargetInfo &STI,
941 raw_ostream &O) {
942 const MCOperand &Op = MI->getOperand(OpNo);
943 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
944 O << "c" << Op.getImm();
945 }
946
printAddSubImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)947 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
948 const MCSubtargetInfo &STI,
949 raw_ostream &O) {
950 const MCOperand &MO = MI->getOperand(OpNum);
951 if (MO.isImm()) {
952 unsigned Val = (MO.getImm() & 0xfff);
953 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
954 unsigned Shift =
955 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
956 O << '#' << formatImm(Val);
957 if (Shift != 0)
958 printShifter(MI, OpNum + 1, STI, O);
959
960 if (CommentStream)
961 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
962 } else {
963 assert(MO.isExpr() && "Unexpected operand type!");
964 MO.getExpr()->print(O, &MAI);
965 printShifter(MI, OpNum + 1, STI, O);
966 }
967 }
968
969 template <typename T>
printLogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)970 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
971 const MCSubtargetInfo &STI,
972 raw_ostream &O) {
973 uint64_t Val = MI->getOperand(OpNum).getImm();
974 O << "#0x";
975 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
976 }
977
printShifter(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)978 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
979 const MCSubtargetInfo &STI,
980 raw_ostream &O) {
981 unsigned Val = MI->getOperand(OpNum).getImm();
982 // LSL #0 should not be printed.
983 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
984 AArch64_AM::getShiftValue(Val) == 0)
985 return;
986 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
987 << " #" << AArch64_AM::getShiftValue(Val);
988 }
989
printShiftedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)990 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
991 const MCSubtargetInfo &STI,
992 raw_ostream &O) {
993 O << getRegisterName(MI->getOperand(OpNum).getReg());
994 printShifter(MI, OpNum + 1, STI, O);
995 }
996
printExtendedRegister(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)997 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
998 const MCSubtargetInfo &STI,
999 raw_ostream &O) {
1000 O << getRegisterName(MI->getOperand(OpNum).getReg());
1001 printArithExtend(MI, OpNum + 1, STI, O);
1002 }
1003
printArithExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1004 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1005 const MCSubtargetInfo &STI,
1006 raw_ostream &O) {
1007 unsigned Val = MI->getOperand(OpNum).getImm();
1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1009 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1010
1011 // If the destination or first source register operand is [W]SP, print
1012 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1013 // all.
1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1015 unsigned Dest = MI->getOperand(0).getReg();
1016 unsigned Src1 = MI->getOperand(1).getReg();
1017 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1018 ExtType == AArch64_AM::UXTX) ||
1019 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1020 ExtType == AArch64_AM::UXTW) ) {
1021 if (ShiftVal != 0)
1022 O << ", lsl #" << ShiftVal;
1023 return;
1024 }
1025 }
1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1027 if (ShiftVal != 0)
1028 O << " #" << ShiftVal;
1029 }
1030
printMemExtendImpl(bool SignExtend,bool DoShift,unsigned Width,char SrcRegKind,raw_ostream & O)1031 static void printMemExtendImpl(bool SignExtend, bool DoShift,
1032 unsigned Width, char SrcRegKind,
1033 raw_ostream &O) {
1034 // sxtw, sxtx, uxtw or lsl (== uxtx)
1035 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1036 if (IsLSL)
1037 O << "lsl";
1038 else
1039 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1040
1041 if (DoShift || IsLSL)
1042 O << " #" << Log2_32(Width / 8);
1043 }
1044
printMemExtend(const MCInst * MI,unsigned OpNum,raw_ostream & O,char SrcRegKind,unsigned Width)1045 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1046 raw_ostream &O, char SrcRegKind,
1047 unsigned Width) {
1048 bool SignExtend = MI->getOperand(OpNum).getImm();
1049 bool DoShift = MI->getOperand(OpNum + 1).getImm();
1050 printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
1051 }
1052
1053 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
printRegWithShiftExtend(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1054 void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
1055 unsigned OpNum,
1056 const MCSubtargetInfo &STI,
1057 raw_ostream &O) {
1058 printOperand(MI, OpNum, STI, O);
1059 if (Suffix == 's' || Suffix == 'd')
1060 O << '.' << Suffix;
1061 else
1062 assert(Suffix == 0 && "Unsupported suffix size");
1063
1064 bool DoShift = ExtWidth != 8;
1065 if (SignExtend || DoShift || SrcRegKind == 'w') {
1066 O << ", ";
1067 printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1068 }
1069 }
1070
printCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1071 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1072 const MCSubtargetInfo &STI,
1073 raw_ostream &O) {
1074 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1075 O << AArch64CC::getCondCodeName(CC);
1076 }
1077
printInverseCondCode(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1078 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1079 const MCSubtargetInfo &STI,
1080 raw_ostream &O) {
1081 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1082 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1083 }
1084
printAMNoIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1085 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1086 const MCSubtargetInfo &STI,
1087 raw_ostream &O) {
1088 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1089 }
1090
1091 template<int Scale>
printImmScale(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1092 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1093 const MCSubtargetInfo &STI,
1094 raw_ostream &O) {
1095 O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1096 }
1097
printUImm12Offset(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O)1098 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1099 unsigned Scale, raw_ostream &O) {
1100 const MCOperand MO = MI->getOperand(OpNum);
1101 if (MO.isImm()) {
1102 O << "#" << formatImm(MO.getImm() * Scale);
1103 } else {
1104 assert(MO.isExpr() && "Unexpected operand type!");
1105 MO.getExpr()->print(O, &MAI);
1106 }
1107 }
1108
printAMIndexedWB(const MCInst * MI,unsigned OpNum,unsigned Scale,raw_ostream & O)1109 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1110 unsigned Scale, raw_ostream &O) {
1111 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1112 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1113 if (MO1.isImm()) {
1114 O << ", #" << formatImm(MO1.getImm() * Scale);
1115 } else {
1116 assert(MO1.isExpr() && "Unexpected operand type!");
1117 O << ", ";
1118 MO1.getExpr()->print(O, &MAI);
1119 }
1120 O << ']';
1121 }
1122
1123 template <bool IsSVEPrefetch>
printPrefetchOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1124 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1125 const MCSubtargetInfo &STI,
1126 raw_ostream &O) {
1127 unsigned prfop = MI->getOperand(OpNum).getImm();
1128 if (IsSVEPrefetch) {
1129 if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1130 O << PRFM->Name;
1131 return;
1132 }
1133 } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
1134 O << PRFM->Name;
1135 return;
1136 }
1137
1138 O << '#' << formatImm(prfop);
1139 }
1140
printPSBHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1141 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1142 const MCSubtargetInfo &STI,
1143 raw_ostream &O) {
1144 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1145 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1146 if (PSB)
1147 O << PSB->Name;
1148 else
1149 O << '#' << formatImm(psbhintop);
1150 }
1151
printBTIHintOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1152 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1153 const MCSubtargetInfo &STI,
1154 raw_ostream &O) {
1155 unsigned btihintop = (MI->getOperand(OpNum).getImm() ^ 32) >> 1;
1156 auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1157 if (BTI)
1158 O << BTI->Name;
1159 else
1160 O << '#' << formatImm(btihintop);
1161 }
1162
printFPImmOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1163 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1164 const MCSubtargetInfo &STI,
1165 raw_ostream &O) {
1166 const MCOperand &MO = MI->getOperand(OpNum);
1167 float FPImm =
1168 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1169
1170 // 8 decimal places are enough to perfectly represent permitted floats.
1171 O << format("#%.8f", FPImm);
1172 }
1173
getNextVectorRegister(unsigned Reg,unsigned Stride=1)1174 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1175 while (Stride--) {
1176 switch (Reg) {
1177 default:
1178 llvm_unreachable("Vector register expected!");
1179 case AArch64::Q0: Reg = AArch64::Q1; break;
1180 case AArch64::Q1: Reg = AArch64::Q2; break;
1181 case AArch64::Q2: Reg = AArch64::Q3; break;
1182 case AArch64::Q3: Reg = AArch64::Q4; break;
1183 case AArch64::Q4: Reg = AArch64::Q5; break;
1184 case AArch64::Q5: Reg = AArch64::Q6; break;
1185 case AArch64::Q6: Reg = AArch64::Q7; break;
1186 case AArch64::Q7: Reg = AArch64::Q8; break;
1187 case AArch64::Q8: Reg = AArch64::Q9; break;
1188 case AArch64::Q9: Reg = AArch64::Q10; break;
1189 case AArch64::Q10: Reg = AArch64::Q11; break;
1190 case AArch64::Q11: Reg = AArch64::Q12; break;
1191 case AArch64::Q12: Reg = AArch64::Q13; break;
1192 case AArch64::Q13: Reg = AArch64::Q14; break;
1193 case AArch64::Q14: Reg = AArch64::Q15; break;
1194 case AArch64::Q15: Reg = AArch64::Q16; break;
1195 case AArch64::Q16: Reg = AArch64::Q17; break;
1196 case AArch64::Q17: Reg = AArch64::Q18; break;
1197 case AArch64::Q18: Reg = AArch64::Q19; break;
1198 case AArch64::Q19: Reg = AArch64::Q20; break;
1199 case AArch64::Q20: Reg = AArch64::Q21; break;
1200 case AArch64::Q21: Reg = AArch64::Q22; break;
1201 case AArch64::Q22: Reg = AArch64::Q23; break;
1202 case AArch64::Q23: Reg = AArch64::Q24; break;
1203 case AArch64::Q24: Reg = AArch64::Q25; break;
1204 case AArch64::Q25: Reg = AArch64::Q26; break;
1205 case AArch64::Q26: Reg = AArch64::Q27; break;
1206 case AArch64::Q27: Reg = AArch64::Q28; break;
1207 case AArch64::Q28: Reg = AArch64::Q29; break;
1208 case AArch64::Q29: Reg = AArch64::Q30; break;
1209 case AArch64::Q30: Reg = AArch64::Q31; break;
1210 // Vector lists can wrap around.
1211 case AArch64::Q31:
1212 Reg = AArch64::Q0;
1213 break;
1214 case AArch64::Z0: Reg = AArch64::Z1; break;
1215 case AArch64::Z1: Reg = AArch64::Z2; break;
1216 case AArch64::Z2: Reg = AArch64::Z3; break;
1217 case AArch64::Z3: Reg = AArch64::Z4; break;
1218 case AArch64::Z4: Reg = AArch64::Z5; break;
1219 case AArch64::Z5: Reg = AArch64::Z6; break;
1220 case AArch64::Z6: Reg = AArch64::Z7; break;
1221 case AArch64::Z7: Reg = AArch64::Z8; break;
1222 case AArch64::Z8: Reg = AArch64::Z9; break;
1223 case AArch64::Z9: Reg = AArch64::Z10; break;
1224 case AArch64::Z10: Reg = AArch64::Z11; break;
1225 case AArch64::Z11: Reg = AArch64::Z12; break;
1226 case AArch64::Z12: Reg = AArch64::Z13; break;
1227 case AArch64::Z13: Reg = AArch64::Z14; break;
1228 case AArch64::Z14: Reg = AArch64::Z15; break;
1229 case AArch64::Z15: Reg = AArch64::Z16; break;
1230 case AArch64::Z16: Reg = AArch64::Z17; break;
1231 case AArch64::Z17: Reg = AArch64::Z18; break;
1232 case AArch64::Z18: Reg = AArch64::Z19; break;
1233 case AArch64::Z19: Reg = AArch64::Z20; break;
1234 case AArch64::Z20: Reg = AArch64::Z21; break;
1235 case AArch64::Z21: Reg = AArch64::Z22; break;
1236 case AArch64::Z22: Reg = AArch64::Z23; break;
1237 case AArch64::Z23: Reg = AArch64::Z24; break;
1238 case AArch64::Z24: Reg = AArch64::Z25; break;
1239 case AArch64::Z25: Reg = AArch64::Z26; break;
1240 case AArch64::Z26: Reg = AArch64::Z27; break;
1241 case AArch64::Z27: Reg = AArch64::Z28; break;
1242 case AArch64::Z28: Reg = AArch64::Z29; break;
1243 case AArch64::Z29: Reg = AArch64::Z30; break;
1244 case AArch64::Z30: Reg = AArch64::Z31; break;
1245 // Vector lists can wrap around.
1246 case AArch64::Z31:
1247 Reg = AArch64::Z0;
1248 break;
1249 }
1250 }
1251 return Reg;
1252 }
1253
1254 template<unsigned size>
printGPRSeqPairsClassOperand(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1255 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1256 unsigned OpNum,
1257 const MCSubtargetInfo &STI,
1258 raw_ostream &O) {
1259 static_assert(size == 64 || size == 32,
1260 "Template parameter must be either 32 or 64");
1261 unsigned Reg = MI->getOperand(OpNum).getReg();
1262
1263 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1264 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1265
1266 unsigned Even = MRI.getSubReg(Reg, Sube);
1267 unsigned Odd = MRI.getSubReg(Reg, Subo);
1268 O << getRegisterName(Even) << ", " << getRegisterName(Odd);
1269 }
1270
printVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O,StringRef LayoutSuffix)1271 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1272 const MCSubtargetInfo &STI,
1273 raw_ostream &O,
1274 StringRef LayoutSuffix) {
1275 unsigned Reg = MI->getOperand(OpNum).getReg();
1276
1277 O << "{ ";
1278
1279 // Work out how many registers there are in the list (if there is an actual
1280 // list).
1281 unsigned NumRegs = 1;
1282 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1283 MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1284 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1285 NumRegs = 2;
1286 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1287 MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1288 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1289 NumRegs = 3;
1290 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1291 MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1292 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1293 NumRegs = 4;
1294
1295 // Now forget about the list and find out what the first register is.
1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1297 Reg = FirstReg;
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1299 Reg = FirstReg;
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1301 Reg = FirstReg;
1302
1303 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1304 // printing (otherwise getRegisterName fails).
1305 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1306 const MCRegisterClass &FPR128RC =
1307 MRI.getRegClass(AArch64::FPR128RegClassID);
1308 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1309 }
1310
1311 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1312 if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1313 O << getRegisterName(Reg) << LayoutSuffix;
1314 else
1315 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1316
1317 if (i + 1 != NumRegs)
1318 O << ", ";
1319 }
1320
1321 O << " }";
1322 }
1323
1324 void
printImplicitlyTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1325 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1326 unsigned OpNum,
1327 const MCSubtargetInfo &STI,
1328 raw_ostream &O) {
1329 printVectorList(MI, OpNum, STI, O, "");
1330 }
1331
1332 template <unsigned NumLanes, char LaneKind>
printTypedVectorList(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1333 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1334 const MCSubtargetInfo &STI,
1335 raw_ostream &O) {
1336 std::string Suffix(".");
1337 if (NumLanes)
1338 Suffix += itostr(NumLanes) + LaneKind;
1339 else
1340 Suffix += LaneKind;
1341
1342 printVectorList(MI, OpNum, STI, O, Suffix);
1343 }
1344
printVectorIndex(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1345 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1346 const MCSubtargetInfo &STI,
1347 raw_ostream &O) {
1348 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1349 }
1350
printAlignedLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1351 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, uint64_t Address,
1352 unsigned OpNum,
1353 const MCSubtargetInfo &STI,
1354 raw_ostream &O) {
1355 const MCOperand &Op = MI->getOperand(OpNum);
1356
1357 // If the label has already been resolved to an immediate offset (say, when
1358 // we're running the disassembler), just print the immediate.
1359 if (Op.isImm()) {
1360 int64_t Offset = Op.getImm() * 4;
1361 if (PrintBranchImmAsAddress)
1362 O << formatHex(Address + Offset);
1363 else
1364 O << "#" << formatImm(Offset);
1365 return;
1366 }
1367
1368 // If the branch target is simply an address then print it in hex.
1369 const MCConstantExpr *BranchTarget =
1370 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1371 int64_t TargetAddress;
1372 if (BranchTarget && BranchTarget->evaluateAsAbsolute(TargetAddress)) {
1373 O << formatHex(TargetAddress);
1374 } else {
1375 // Otherwise, just print the expression.
1376 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1377 }
1378 }
1379
printAdrpLabel(const MCInst * MI,uint64_t Address,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1380 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, uint64_t Address,
1381 unsigned OpNum,
1382 const MCSubtargetInfo &STI,
1383 raw_ostream &O) {
1384 const MCOperand &Op = MI->getOperand(OpNum);
1385
1386 // If the label has already been resolved to an immediate offset (say, when
1387 // we're running the disassembler), just print the immediate.
1388 if (Op.isImm()) {
1389 const int64_t Offset = Op.getImm() * 4096;
1390 if (PrintBranchImmAsAddress)
1391 O << formatHex((Address & -4096) + Offset);
1392 else
1393 O << "#" << Offset;
1394 return;
1395 }
1396
1397 // Otherwise, just print the expression.
1398 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1399 }
1400
printBarrierOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1401 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1402 const MCSubtargetInfo &STI,
1403 raw_ostream &O) {
1404 unsigned Val = MI->getOperand(OpNo).getImm();
1405 unsigned Opcode = MI->getOpcode();
1406
1407 StringRef Name;
1408 if (Opcode == AArch64::ISB) {
1409 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1410 Name = ISB ? ISB->Name : "";
1411 } else if (Opcode == AArch64::TSB) {
1412 auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1413 Name = TSB ? TSB->Name : "";
1414 } else {
1415 auto DB = AArch64DB::lookupDBByEncoding(Val);
1416 Name = DB ? DB->Name : "";
1417 }
1418 if (!Name.empty())
1419 O << Name;
1420 else
1421 O << "#" << Val;
1422 }
1423
printBarriernXSOption(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1424 void AArch64InstPrinter::printBarriernXSOption(const MCInst *MI, unsigned OpNo,
1425 const MCSubtargetInfo &STI,
1426 raw_ostream &O) {
1427 unsigned Val = MI->getOperand(OpNo).getImm();
1428 assert(MI->getOpcode() == AArch64::DSBnXS);
1429
1430 StringRef Name;
1431 auto DB = AArch64DBnXS::lookupDBnXSByEncoding(Val);
1432 Name = DB ? DB->Name : "";
1433
1434 if (!Name.empty())
1435 O << Name;
1436 else
1437 O << "#" << Val;
1438 }
1439
printMRSSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1440 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1441 const MCSubtargetInfo &STI,
1442 raw_ostream &O) {
1443 unsigned Val = MI->getOperand(OpNo).getImm();
1444
1445 // Horrible hack for the one register that has identical encodings but
1446 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1447 // going to get the wrong entry
1448 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1449 O << "DBGDTRRX_EL0";
1450 return;
1451 }
1452
1453 // Horrible hack for two different registers having the same encoding.
1454 if (Val == AArch64SysReg::TRCEXTINSELR) {
1455 O << "TRCEXTINSELR";
1456 return;
1457 }
1458
1459 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1460 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
1461 O << Reg->Name;
1462 else
1463 O << AArch64SysReg::genericRegisterString(Val);
1464 }
1465
printMSRSystemRegister(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1466 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1467 const MCSubtargetInfo &STI,
1468 raw_ostream &O) {
1469 unsigned Val = MI->getOperand(OpNo).getImm();
1470
1471 // Horrible hack for the one register that has identical encodings but
1472 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1473 // going to get the wrong entry
1474 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1475 O << "DBGDTRTX_EL0";
1476 return;
1477 }
1478
1479 // Horrible hack for two different registers having the same encoding.
1480 if (Val == AArch64SysReg::TRCEXTINSELR) {
1481 O << "TRCEXTINSELR";
1482 return;
1483 }
1484
1485 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1486 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
1487 O << Reg->Name;
1488 else
1489 O << AArch64SysReg::genericRegisterString(Val);
1490 }
1491
printSystemPStateField(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1492 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1493 const MCSubtargetInfo &STI,
1494 raw_ostream &O) {
1495 unsigned Val = MI->getOperand(OpNo).getImm();
1496
1497 auto PState = AArch64PState::lookupPStateByEncoding(Val);
1498 if (PState && PState->haveFeatures(STI.getFeatureBits()))
1499 O << PState->Name;
1500 else
1501 O << "#" << formatImm(Val);
1502 }
1503
printSIMDType10Operand(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1504 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1505 const MCSubtargetInfo &STI,
1506 raw_ostream &O) {
1507 unsigned RawVal = MI->getOperand(OpNo).getImm();
1508 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1509 O << format("#%#016llx", Val);
1510 }
1511
1512 template<int64_t Angle, int64_t Remainder>
printComplexRotationOp(const MCInst * MI,unsigned OpNo,const MCSubtargetInfo & STI,raw_ostream & O)1513 void AArch64InstPrinter::printComplexRotationOp(const MCInst *MI, unsigned OpNo,
1514 const MCSubtargetInfo &STI,
1515 raw_ostream &O) {
1516 unsigned Val = MI->getOperand(OpNo).getImm();
1517 O << "#" << (Val * Angle) + Remainder;
1518 }
1519
printSVEPattern(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1520 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1521 const MCSubtargetInfo &STI,
1522 raw_ostream &O) {
1523 unsigned Val = MI->getOperand(OpNum).getImm();
1524 if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1525 O << Pat->Name;
1526 else
1527 O << '#' << formatImm(Val);
1528 }
1529
1530 template <char suffix>
printSVERegOp(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1531 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1532 const MCSubtargetInfo &STI,
1533 raw_ostream &O) {
1534 switch (suffix) {
1535 case 0:
1536 case 'b':
1537 case 'h':
1538 case 's':
1539 case 'd':
1540 case 'q':
1541 break;
1542 default: llvm_unreachable("Invalid kind specifier.");
1543 }
1544
1545 unsigned Reg = MI->getOperand(OpNum).getReg();
1546 O << getRegisterName(Reg);
1547 if (suffix != 0)
1548 O << '.' << suffix;
1549 }
1550
1551 template <typename T>
printImmSVE(T Value,raw_ostream & O)1552 void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) {
1553 std::make_unsigned_t<T> HexValue = Value;
1554
1555 if (getPrintImmHex())
1556 O << '#' << formatHex((uint64_t)HexValue);
1557 else
1558 O << '#' << formatDec(Value);
1559
1560 if (CommentStream) {
1561 // Do the opposite to that used for instruction operands.
1562 if (getPrintImmHex())
1563 *CommentStream << '=' << formatDec(HexValue) << '\n';
1564 else
1565 *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
1566 }
1567 }
1568
1569 template <typename T>
printImm8OptLsl(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1570 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
1571 const MCSubtargetInfo &STI,
1572 raw_ostream &O) {
1573 unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
1574 unsigned Shift = MI->getOperand(OpNum + 1).getImm();
1575 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL &&
1576 "Unexepected shift type!");
1577
1578 // #0 lsl #8 is never pretty printed
1579 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
1580 O << '#' << formatImm(UnscaledVal);
1581 printShifter(MI, OpNum + 1, STI, O);
1582 return;
1583 }
1584
1585 T Val;
1586 if (std::is_signed<T>())
1587 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1588 else
1589 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1590
1591 printImmSVE(Val, O);
1592 }
1593
1594 template <typename T>
printSVELogicalImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1595 void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum,
1596 const MCSubtargetInfo &STI,
1597 raw_ostream &O) {
1598 typedef std::make_signed_t<T> SignedT;
1599 typedef std::make_unsigned_t<T> UnsignedT;
1600
1601 uint64_t Val = MI->getOperand(OpNum).getImm();
1602 UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
1603
1604 // Prefer the default format for 16bit values, hex otherwise.
1605 if ((int16_t)PrintVal == (SignedT)PrintVal)
1606 printImmSVE((T)PrintVal, O);
1607 else if ((uint16_t)PrintVal == PrintVal)
1608 printImmSVE(PrintVal, O);
1609 else
1610 O << '#' << formatHex((uint64_t)PrintVal);
1611 }
1612
1613 template <int Width>
printZPRasFPR(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1614 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
1615 const MCSubtargetInfo &STI,
1616 raw_ostream &O) {
1617 unsigned Base;
1618 switch (Width) {
1619 case 8: Base = AArch64::B0; break;
1620 case 16: Base = AArch64::H0; break;
1621 case 32: Base = AArch64::S0; break;
1622 case 64: Base = AArch64::D0; break;
1623 case 128: Base = AArch64::Q0; break;
1624 default:
1625 llvm_unreachable("Unsupported width");
1626 }
1627 unsigned Reg = MI->getOperand(OpNum).getReg();
1628 O << getRegisterName(Reg - AArch64::Z0 + Base);
1629 }
1630
1631 template <unsigned ImmIs0, unsigned ImmIs1>
printExactFPImm(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1632 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
1633 const MCSubtargetInfo &STI,
1634 raw_ostream &O) {
1635 auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
1636 auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
1637 unsigned Val = MI->getOperand(OpNum).getImm();
1638 O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
1639 }
1640
printGPR64as32(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1641 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
1642 const MCSubtargetInfo &STI,
1643 raw_ostream &O) {
1644 unsigned Reg = MI->getOperand(OpNum).getReg();
1645 O << getRegisterName(getWRegFromXReg(Reg));
1646 }
1647
printGPR64x8(const MCInst * MI,unsigned OpNum,const MCSubtargetInfo & STI,raw_ostream & O)1648 void AArch64InstPrinter::printGPR64x8(const MCInst *MI, unsigned OpNum,
1649 const MCSubtargetInfo &STI,
1650 raw_ostream &O) {
1651 unsigned Reg = MI->getOperand(OpNum).getReg();
1652 O << getRegisterName(MRI.getSubReg(Reg, AArch64::x8sub_0));
1653 }
1654