1//=- HexagonScheduleV67T.td - Hexagon V67 Tiny Core Scheduling Definitions --=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class HexagonV67TPseudoItin {
10  list<InstrItinData> V67TPseudoItin_list = [
11    InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
12                          [Hex_FWD, Hex_FWD, Hex_FWD]>,
13    InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
14                            InstrStage<1, [SLOT2, SLOT3]>],
15                           [2, 1, 1],
16                           [Hex_FWD, Hex_FWD, Hex_FWD]>,
17    InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
18                          [2, 1, 1]>,
19    InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
20  ];
21}
22
23// V67TItin_list and HVXItin contain some old itineraries
24// still used by a handful of instructions. Hopefully, we will be able to
25// get rid of them soon.
26def HexagonV67TItinList : DepScalarItinV67T,
27                          DepHVXItinV67, HVXItin, HexagonV67TPseudoItin {
28  list<InstrItinData> V67TItin_list = [
29    InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
30                                   [3, 1, 1],
31                                   [Hex_FWD, Hex_FWD, Hex_FWD]>,
32    InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
33                                   [1, 1, 3, 3],
34                                   [Hex_FWD, Hex_FWD]>
35  ];
36
37  list<InstrItinData> ItinList =
38    !listconcat(DepScalarItinV67T_list,
39                DepHVXItinV67_list, V67TItin_list,
40                HVXItin_list, V67TPseudoItin_list);
41}
42
43def HexagonItinerariesV67T :
44      ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
45                            CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
46                            CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
47                            CVI_ALL_NOMEM, CVI_ZW],
48                            [Hex_FWD, HVX_FWD],
49                            HexagonV67TItinList.ItinList>;
50
51
52def HexagonModelV67T : SchedMachineModel {
53  let IssueWidth = 3;
54  let Itineraries = HexagonItinerariesV67T;
55  let LoadLatency = 1;
56  let CompleteModel = 0;
57}
58
59//===----------------------------------------------------------------------===//
60// Hexagon V67 Tiny Core Resource Definitions -
61//===----------------------------------------------------------------------===//
62