1 //===- HexagonSplitDouble.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #define DEBUG_TYPE "hsdr"
10
11 #include "HexagonInstrInfo.h"
12 #include "HexagonRegisterInfo.h"
13 #include "HexagonSubtarget.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetRegisterInfo.h"
28 #include "llvm/Config/llvm-config.h"
29 #include "llvm/IR/DebugLoc.h"
30 #include "llvm/Pass.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <limits>
40 #include <map>
41 #include <set>
42 #include <utility>
43 #include <vector>
44
45 using namespace llvm;
46
47 namespace llvm {
48
49 FunctionPass *createHexagonSplitDoubleRegs();
50 void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
51
52 } // end namespace llvm
53
54 static cl::opt<int> MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1),
55 cl::desc("Maximum number of split partitions"));
56 static cl::opt<bool> MemRefsFixed("hsdr-no-mem", cl::Hidden, cl::init(true),
57 cl::desc("Do not split loads or stores"));
58 static cl::opt<bool> SplitAll("hsdr-split-all", cl::Hidden, cl::init(false),
59 cl::desc("Split all partitions"));
60
61 namespace {
62
63 class HexagonSplitDoubleRegs : public MachineFunctionPass {
64 public:
65 static char ID;
66
HexagonSplitDoubleRegs()67 HexagonSplitDoubleRegs() : MachineFunctionPass(ID) {}
68
getPassName() const69 StringRef getPassName() const override {
70 return "Hexagon Split Double Registers";
71 }
72
getAnalysisUsage(AnalysisUsage & AU) const73 void getAnalysisUsage(AnalysisUsage &AU) const override {
74 AU.addRequired<MachineLoopInfo>();
75 AU.addPreserved<MachineLoopInfo>();
76 MachineFunctionPass::getAnalysisUsage(AU);
77 }
78
79 bool runOnMachineFunction(MachineFunction &MF) override;
80
81 private:
82 static const TargetRegisterClass *const DoubleRC;
83
84 const HexagonRegisterInfo *TRI = nullptr;
85 const HexagonInstrInfo *TII = nullptr;
86 const MachineLoopInfo *MLI;
87 MachineRegisterInfo *MRI;
88
89 using USet = std::set<unsigned>;
90 using UUSetMap = std::map<unsigned, USet>;
91 using UUPair = std::pair<unsigned, unsigned>;
92 using UUPairMap = std::map<unsigned, UUPair>;
93 using LoopRegMap = std::map<const MachineLoop *, USet>;
94
95 bool isInduction(unsigned Reg, LoopRegMap &IRM) const;
96 bool isVolatileInstr(const MachineInstr *MI) const;
97 bool isFixedInstr(const MachineInstr *MI) const;
98 void partitionRegisters(UUSetMap &P2Rs);
99 int32_t profit(const MachineInstr *MI) const;
100 int32_t profit(Register Reg) const;
101 bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
102
103 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
104 void collectIndRegs(LoopRegMap &IRM);
105
106 void createHalfInstr(unsigned Opc, MachineInstr *MI,
107 const UUPairMap &PairMap, unsigned SubR);
108 void splitMemRef(MachineInstr *MI, const UUPairMap &PairMap);
109 void splitImmediate(MachineInstr *MI, const UUPairMap &PairMap);
110 void splitCombine(MachineInstr *MI, const UUPairMap &PairMap);
111 void splitExt(MachineInstr *MI, const UUPairMap &PairMap);
112 void splitShift(MachineInstr *MI, const UUPairMap &PairMap);
113 void splitAslOr(MachineInstr *MI, const UUPairMap &PairMap);
114 bool splitInstr(MachineInstr *MI, const UUPairMap &PairMap);
115 void replaceSubregUses(MachineInstr *MI, const UUPairMap &PairMap);
116 void collapseRegPairs(MachineInstr *MI, const UUPairMap &PairMap);
117 bool splitPartition(const USet &Part);
118
119 static int Counter;
120
121 static void dump_partition(raw_ostream&, const USet&,
122 const TargetRegisterInfo&);
123 };
124
125 } // end anonymous namespace
126
127 char HexagonSplitDoubleRegs::ID;
128 int HexagonSplitDoubleRegs::Counter = 0;
129 const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
130 &Hexagon::DoubleRegsRegClass;
131
132 INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",
133 "Hexagon Split Double Registers", false, false)
134
135 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dump_partition(raw_ostream & os,const USet & Part,const TargetRegisterInfo & TRI)136 LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,
137 const USet &Part, const TargetRegisterInfo &TRI) {
138 dbgs() << '{';
139 for (auto I : Part)
140 dbgs() << ' ' << printReg(I, &TRI);
141 dbgs() << " }";
142 }
143 #endif
144
isInduction(unsigned Reg,LoopRegMap & IRM) const145 bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const {
146 for (auto I : IRM) {
147 const USet &Rs = I.second;
148 if (Rs.find(Reg) != Rs.end())
149 return true;
150 }
151 return false;
152 }
153
isVolatileInstr(const MachineInstr * MI) const154 bool HexagonSplitDoubleRegs::isVolatileInstr(const MachineInstr *MI) const {
155 for (auto &MO : MI->memoperands())
156 if (MO->isVolatile() || MO->isAtomic())
157 return true;
158 return false;
159 }
160
isFixedInstr(const MachineInstr * MI) const161 bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
162 if (MI->mayLoadOrStore())
163 if (MemRefsFixed || isVolatileInstr(MI))
164 return true;
165 if (MI->isDebugInstr())
166 return false;
167
168 unsigned Opc = MI->getOpcode();
169 switch (Opc) {
170 default:
171 return true;
172
173 case TargetOpcode::PHI:
174 case TargetOpcode::COPY:
175 break;
176
177 case Hexagon::L2_loadrd_io:
178 // Not handling stack stores (only reg-based addresses).
179 if (MI->getOperand(1).isReg())
180 break;
181 return true;
182 case Hexagon::S2_storerd_io:
183 // Not handling stack stores (only reg-based addresses).
184 if (MI->getOperand(0).isReg())
185 break;
186 return true;
187 case Hexagon::L2_loadrd_pi:
188 case Hexagon::S2_storerd_pi:
189
190 case Hexagon::A2_tfrpi:
191 case Hexagon::A2_combineii:
192 case Hexagon::A4_combineir:
193 case Hexagon::A4_combineii:
194 case Hexagon::A4_combineri:
195 case Hexagon::A2_combinew:
196 case Hexagon::CONST64:
197
198 case Hexagon::A2_sxtw:
199
200 case Hexagon::A2_andp:
201 case Hexagon::A2_orp:
202 case Hexagon::A2_xorp:
203 case Hexagon::S2_asl_i_p_or:
204 case Hexagon::S2_asl_i_p:
205 case Hexagon::S2_asr_i_p:
206 case Hexagon::S2_lsr_i_p:
207 break;
208 }
209
210 for (auto &Op : MI->operands()) {
211 if (!Op.isReg())
212 continue;
213 Register R = Op.getReg();
214 if (!R.isVirtual())
215 return true;
216 }
217 return false;
218 }
219
partitionRegisters(UUSetMap & P2Rs)220 void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
221 using UUMap = std::map<unsigned, unsigned>;
222 using UVect = std::vector<unsigned>;
223
224 unsigned NumRegs = MRI->getNumVirtRegs();
225 BitVector DoubleRegs(NumRegs);
226 for (unsigned i = 0; i < NumRegs; ++i) {
227 unsigned R = Register::index2VirtReg(i);
228 if (MRI->getRegClass(R) == DoubleRC)
229 DoubleRegs.set(i);
230 }
231
232 BitVector FixedRegs(NumRegs);
233 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
234 unsigned R = Register::index2VirtReg(x);
235 MachineInstr *DefI = MRI->getVRegDef(R);
236 // In some cases a register may exist, but never be defined or used.
237 // It should never appear anywhere, but mark it as "fixed", just to be
238 // safe.
239 if (!DefI || isFixedInstr(DefI))
240 FixedRegs.set(x);
241 }
242
243 UUSetMap AssocMap;
244 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
245 if (FixedRegs[x])
246 continue;
247 unsigned R = Register::index2VirtReg(x);
248 LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~");
249 USet &Asc = AssocMap[R];
250 for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
251 U != Z; ++U) {
252 MachineOperand &Op = *U;
253 MachineInstr *UseI = Op.getParent();
254 if (isFixedInstr(UseI))
255 continue;
256 for (unsigned i = 0, n = UseI->getNumOperands(); i < n; ++i) {
257 MachineOperand &MO = UseI->getOperand(i);
258 // Skip non-registers or registers with subregisters.
259 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
260 continue;
261 Register T = MO.getReg();
262 if (!T.isVirtual()) {
263 FixedRegs.set(x);
264 continue;
265 }
266 if (MRI->getRegClass(T) != DoubleRC)
267 continue;
268 unsigned u = Register::virtReg2Index(T);
269 if (FixedRegs[u])
270 continue;
271 LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));
272 Asc.insert(T);
273 // Make it symmetric.
274 AssocMap[T].insert(R);
275 }
276 }
277 LLVM_DEBUG(dbgs() << '\n');
278 }
279
280 UUMap R2P;
281 unsigned NextP = 1;
282 USet Visited;
283 for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
284 unsigned R = Register::index2VirtReg(x);
285 if (Visited.count(R))
286 continue;
287 // Create a new partition for R.
288 unsigned ThisP = FixedRegs[x] ? 0 : NextP++;
289 UVect WorkQ;
290 WorkQ.push_back(R);
291 for (unsigned i = 0; i < WorkQ.size(); ++i) {
292 unsigned T = WorkQ[i];
293 if (Visited.count(T))
294 continue;
295 R2P[T] = ThisP;
296 Visited.insert(T);
297 // Add all registers associated with T.
298 USet &Asc = AssocMap[T];
299 for (USet::iterator J = Asc.begin(), F = Asc.end(); J != F; ++J)
300 WorkQ.push_back(*J);
301 }
302 }
303
304 for (auto I : R2P)
305 P2Rs[I.second].insert(I.first);
306 }
307
profitImm(unsigned Imm)308 static inline int32_t profitImm(unsigned Imm) {
309 int32_t P = 0;
310 if (Imm == 0 || Imm == 0xFFFFFFFF)
311 P += 10;
312 return P;
313 }
314
profit(const MachineInstr * MI) const315 int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
316 unsigned ImmX = 0;
317 unsigned Opc = MI->getOpcode();
318 switch (Opc) {
319 case TargetOpcode::PHI:
320 for (const auto &Op : MI->operands())
321 if (!Op.getSubReg())
322 return 0;
323 return 10;
324 case TargetOpcode::COPY:
325 if (MI->getOperand(1).getSubReg() != 0)
326 return 10;
327 return 0;
328
329 case Hexagon::L2_loadrd_io:
330 case Hexagon::S2_storerd_io:
331 return -1;
332 case Hexagon::L2_loadrd_pi:
333 case Hexagon::S2_storerd_pi:
334 return 2;
335
336 case Hexagon::A2_tfrpi:
337 case Hexagon::CONST64: {
338 uint64_t D = MI->getOperand(1).getImm();
339 unsigned Lo = D & 0xFFFFFFFFULL;
340 unsigned Hi = D >> 32;
341 return profitImm(Lo) + profitImm(Hi);
342 }
343 case Hexagon::A2_combineii:
344 case Hexagon::A4_combineii: {
345 const MachineOperand &Op1 = MI->getOperand(1);
346 const MachineOperand &Op2 = MI->getOperand(2);
347 int32_t Prof1 = Op1.isImm() ? profitImm(Op1.getImm()) : 0;
348 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0;
349 return Prof1 + Prof2;
350 }
351 case Hexagon::A4_combineri:
352 ImmX++;
353 // Fall through into A4_combineir.
354 LLVM_FALLTHROUGH;
355 case Hexagon::A4_combineir: {
356 ImmX++;
357 const MachineOperand &OpX = MI->getOperand(ImmX);
358 if (OpX.isImm()) {
359 int64_t V = OpX.getImm();
360 if (V == 0 || V == -1)
361 return 10;
362 }
363 // Fall through into A2_combinew.
364 LLVM_FALLTHROUGH;
365 }
366 case Hexagon::A2_combinew:
367 return 2;
368
369 case Hexagon::A2_sxtw:
370 return 3;
371
372 case Hexagon::A2_andp:
373 case Hexagon::A2_orp:
374 case Hexagon::A2_xorp: {
375 Register Rs = MI->getOperand(1).getReg();
376 Register Rt = MI->getOperand(2).getReg();
377 return profit(Rs) + profit(Rt);
378 }
379
380 case Hexagon::S2_asl_i_p_or: {
381 unsigned S = MI->getOperand(3).getImm();
382 if (S == 0 || S == 32)
383 return 10;
384 return -1;
385 }
386 case Hexagon::S2_asl_i_p:
387 case Hexagon::S2_asr_i_p:
388 case Hexagon::S2_lsr_i_p:
389 unsigned S = MI->getOperand(2).getImm();
390 if (S == 0 || S == 32)
391 return 10;
392 if (S == 16)
393 return 5;
394 if (S == 48)
395 return 7;
396 return -10;
397 }
398
399 return 0;
400 }
401
profit(Register Reg) const402 int32_t HexagonSplitDoubleRegs::profit(Register Reg) const {
403 assert(Reg.isVirtual());
404
405 const MachineInstr *DefI = MRI->getVRegDef(Reg);
406 switch (DefI->getOpcode()) {
407 case Hexagon::A2_tfrpi:
408 case Hexagon::CONST64:
409 case Hexagon::A2_combineii:
410 case Hexagon::A4_combineii:
411 case Hexagon::A4_combineri:
412 case Hexagon::A4_combineir:
413 case Hexagon::A2_combinew:
414 return profit(DefI);
415 default:
416 break;
417 }
418 return 0;
419 }
420
isProfitable(const USet & Part,LoopRegMap & IRM) const421 bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM)
422 const {
423 unsigned FixedNum = 0, LoopPhiNum = 0;
424 int32_t TotalP = 0;
425
426 for (unsigned DR : Part) {
427 MachineInstr *DefI = MRI->getVRegDef(DR);
428 int32_t P = profit(DefI);
429 if (P == std::numeric_limits<int>::min())
430 return false;
431 TotalP += P;
432 // Reduce the profitability of splitting induction registers.
433 if (isInduction(DR, IRM))
434 TotalP -= 30;
435
436 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
437 U != W; ++U) {
438 MachineInstr *UseI = U->getParent();
439 if (isFixedInstr(UseI)) {
440 FixedNum++;
441 // Calculate the cost of generating REG_SEQUENCE instructions.
442 for (auto &Op : UseI->operands()) {
443 if (Op.isReg() && Part.count(Op.getReg()))
444 if (Op.getSubReg())
445 TotalP -= 2;
446 }
447 continue;
448 }
449 // If a register from this partition is used in a fixed instruction,
450 // and there is also a register in this partition that is used in
451 // a loop phi node, then decrease the splitting profit as this can
452 // confuse the modulo scheduler.
453 if (UseI->isPHI()) {
454 const MachineBasicBlock *PB = UseI->getParent();
455 const MachineLoop *L = MLI->getLoopFor(PB);
456 if (L && L->getHeader() == PB)
457 LoopPhiNum++;
458 }
459 // Splittable instruction.
460 int32_t P = profit(UseI);
461 if (P == std::numeric_limits<int>::min())
462 return false;
463 TotalP += P;
464 }
465 }
466
467 if (FixedNum > 0 && LoopPhiNum > 0)
468 TotalP -= 20*LoopPhiNum;
469
470 LLVM_DEBUG(dbgs() << "Partition profit: " << TotalP << '\n');
471 if (SplitAll)
472 return true;
473 return TotalP > 0;
474 }
475
collectIndRegsForLoop(const MachineLoop * L,USet & Rs)476 void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
477 USet &Rs) {
478 const MachineBasicBlock *HB = L->getHeader();
479 const MachineBasicBlock *LB = L->getLoopLatch();
480 if (!HB || !LB)
481 return;
482
483 // Examine the latch branch. Expect it to be a conditional branch to
484 // the header (either "br-cond header" or "br-cond exit; br header").
485 MachineBasicBlock *TB = nullptr, *FB = nullptr;
486 MachineBasicBlock *TmpLB = const_cast<MachineBasicBlock*>(LB);
487 SmallVector<MachineOperand,2> Cond;
488 bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
489 // Only analyzable conditional branches. HII::analyzeBranch will put
490 // the branch opcode as the first element of Cond, and the predicate
491 // operand as the second.
492 if (BadLB || Cond.size() != 2)
493 return;
494 // Only simple jump-conditional (with or without negation).
495 if (!TII->PredOpcodeHasJMP_c(Cond[0].getImm()))
496 return;
497 // Must go to the header.
498 if (TB != HB && FB != HB)
499 return;
500 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");
501 // Expect a predicate register.
502 Register PR = Cond[1].getReg();
503 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
504
505 // Get the registers on which the loop controlling compare instruction
506 // depends.
507 Register CmpR1, CmpR2;
508 const MachineInstr *CmpI = MRI->getVRegDef(PR);
509 while (CmpI->getOpcode() == Hexagon::C2_not)
510 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());
511
512 int Mask = 0, Val = 0;
513 bool OkCI = TII->analyzeCompare(*CmpI, CmpR1, CmpR2, Mask, Val);
514 if (!OkCI)
515 return;
516 // Eliminate non-double input registers.
517 if (CmpR1 && MRI->getRegClass(CmpR1) != DoubleRC)
518 CmpR1 = 0;
519 if (CmpR2 && MRI->getRegClass(CmpR2) != DoubleRC)
520 CmpR2 = 0;
521 if (!CmpR1 && !CmpR2)
522 return;
523
524 // Now examine the top of the loop: the phi nodes that could poten-
525 // tially define loop induction registers. The registers defined by
526 // such a phi node would be used in a 64-bit add, which then would
527 // be used in the loop compare instruction.
528
529 // Get the set of all double registers defined by phi nodes in the
530 // loop header.
531 using UVect = std::vector<unsigned>;
532
533 UVect DP;
534 for (auto &MI : *HB) {
535 if (!MI.isPHI())
536 break;
537 const MachineOperand &MD = MI.getOperand(0);
538 Register R = MD.getReg();
539 if (MRI->getRegClass(R) == DoubleRC)
540 DP.push_back(R);
541 }
542 if (DP.empty())
543 return;
544
545 auto NoIndOp = [this, CmpR1, CmpR2] (unsigned R) -> bool {
546 for (auto I = MRI->use_nodbg_begin(R), E = MRI->use_nodbg_end();
547 I != E; ++I) {
548 const MachineInstr *UseI = I->getParent();
549 if (UseI->getOpcode() != Hexagon::A2_addp)
550 continue;
551 // Get the output from the add. If it is one of the inputs to the
552 // loop-controlling compare instruction, then R is likely an induc-
553 // tion register.
554 Register T = UseI->getOperand(0).getReg();
555 if (T == CmpR1 || T == CmpR2)
556 return false;
557 }
558 return true;
559 };
560 UVect::iterator End = llvm::remove_if(DP, NoIndOp);
561 Rs.insert(DP.begin(), End);
562 Rs.insert(CmpR1);
563 Rs.insert(CmpR2);
564
565 LLVM_DEBUG({
566 dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
567 dump_partition(dbgs(), Rs, *TRI);
568 dbgs() << '\n';
569 });
570 }
571
collectIndRegs(LoopRegMap & IRM)572 void HexagonSplitDoubleRegs::collectIndRegs(LoopRegMap &IRM) {
573 using LoopVector = std::vector<MachineLoop *>;
574
575 LoopVector WorkQ;
576
577 append_range(WorkQ, *MLI);
578 for (unsigned i = 0; i < WorkQ.size(); ++i)
579 append_range(WorkQ, *WorkQ[i]);
580
581 USet Rs;
582 for (unsigned i = 0, n = WorkQ.size(); i < n; ++i) {
583 MachineLoop *L = WorkQ[i];
584 Rs.clear();
585 collectIndRegsForLoop(L, Rs);
586 if (!Rs.empty())
587 IRM.insert(std::make_pair(L, Rs));
588 }
589 }
590
createHalfInstr(unsigned Opc,MachineInstr * MI,const UUPairMap & PairMap,unsigned SubR)591 void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
592 const UUPairMap &PairMap, unsigned SubR) {
593 MachineBasicBlock &B = *MI->getParent();
594 DebugLoc DL = MI->getDebugLoc();
595 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
596
597 for (auto &Op : MI->operands()) {
598 if (!Op.isReg()) {
599 NewI->addOperand(Op);
600 continue;
601 }
602 // For register operands, set the subregister.
603 Register R = Op.getReg();
604 unsigned SR = Op.getSubReg();
605 bool isVirtReg = R.isVirtual();
606 bool isKill = Op.isKill();
607 if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
608 isKill = false;
609 UUPairMap::const_iterator F = PairMap.find(R);
610 if (F == PairMap.end()) {
611 SR = SubR;
612 } else {
613 const UUPair &P = F->second;
614 R = (SubR == Hexagon::isub_lo) ? P.first : P.second;
615 SR = 0;
616 }
617 }
618 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
619 Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
620 Op.isInternalRead());
621 NewI->addOperand(CO);
622 }
623 }
624
splitMemRef(MachineInstr * MI,const UUPairMap & PairMap)625 void HexagonSplitDoubleRegs::splitMemRef(MachineInstr *MI,
626 const UUPairMap &PairMap) {
627 bool Load = MI->mayLoad();
628 unsigned OrigOpc = MI->getOpcode();
629 bool PostInc = (OrigOpc == Hexagon::L2_loadrd_pi ||
630 OrigOpc == Hexagon::S2_storerd_pi);
631 MachineInstr *LowI, *HighI;
632 MachineBasicBlock &B = *MI->getParent();
633 DebugLoc DL = MI->getDebugLoc();
634
635 // Index of the base-address-register operand.
636 unsigned AdrX = PostInc ? (Load ? 2 : 1)
637 : (Load ? 1 : 0);
638 MachineOperand &AdrOp = MI->getOperand(AdrX);
639 unsigned RSA = getRegState(AdrOp);
640 MachineOperand &ValOp = Load ? MI->getOperand(0)
641 : (PostInc ? MI->getOperand(3)
642 : MI->getOperand(2));
643 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg());
644 assert(F != PairMap.end());
645
646 if (Load) {
647 const UUPair &P = F->second;
648 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm();
649 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
650 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
651 .addImm(Off);
652 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
654 .addImm(Off+4);
655 } else {
656 const UUPair &P = F->second;
657 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm();
658 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
659 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
660 .addImm(Off)
661 .addReg(P.first);
662 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
663 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
664 .addImm(Off+4)
665 .addReg(P.second);
666 }
667
668 if (PostInc) {
669 // Create the increment of the address register.
670 int64_t Inc = Load ? MI->getOperand(3).getImm()
671 : MI->getOperand(2).getImm();
672 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
673 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
674 Register NewR = MRI->createVirtualRegister(RC);
675 assert(!UpdOp.getSubReg() && "Def operand with subreg");
676 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
677 .addReg(AdrOp.getReg(), RSA)
678 .addImm(Inc);
679 MRI->replaceRegWith(UpdOp.getReg(), NewR);
680 // The original instruction will be deleted later.
681 }
682
683 // Generate a new pair of memory-operands.
684 MachineFunction &MF = *B.getParent();
685 for (auto &MO : MI->memoperands()) {
686 const MachinePointerInfo &Ptr = MO->getPointerInfo();
687 MachineMemOperand::Flags F = MO->getFlags();
688 Align A = MO->getAlign();
689
690 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A);
691 LowI->addMemOperand(MF, Tmp1);
692 auto *Tmp2 =
693 MF.getMachineMemOperand(Ptr, F, 4 /*size*/, std::min(A, Align(4)));
694 HighI->addMemOperand(MF, Tmp2);
695 }
696 }
697
splitImmediate(MachineInstr * MI,const UUPairMap & PairMap)698 void HexagonSplitDoubleRegs::splitImmediate(MachineInstr *MI,
699 const UUPairMap &PairMap) {
700 MachineOperand &Op0 = MI->getOperand(0);
701 MachineOperand &Op1 = MI->getOperand(1);
702 assert(Op0.isReg() && Op1.isImm());
703 uint64_t V = Op1.getImm();
704
705 MachineBasicBlock &B = *MI->getParent();
706 DebugLoc DL = MI->getDebugLoc();
707 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
708 assert(F != PairMap.end());
709 const UUPair &P = F->second;
710
711 // The operand to A2_tfrsi can only have 32 significant bits. Immediate
712 // values in MachineOperand are stored as 64-bit integers, and so the
713 // value -1 may be represented either as 64-bit -1, or 4294967295. Both
714 // will have the 32 higher bits truncated in the end, but -1 will remain
715 // as -1, while the latter may appear to be a large unsigned value
716 // requiring a constant extender. The casting to int32_t will select the
717 // former representation. (The same reasoning applies to all 32-bit
718 // values.)
719 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
720 .addImm(int32_t(V & 0xFFFFFFFFULL));
721 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
722 .addImm(int32_t(V >> 32));
723 }
724
splitCombine(MachineInstr * MI,const UUPairMap & PairMap)725 void HexagonSplitDoubleRegs::splitCombine(MachineInstr *MI,
726 const UUPairMap &PairMap) {
727 MachineOperand &Op0 = MI->getOperand(0);
728 MachineOperand &Op1 = MI->getOperand(1);
729 MachineOperand &Op2 = MI->getOperand(2);
730 assert(Op0.isReg());
731
732 MachineBasicBlock &B = *MI->getParent();
733 DebugLoc DL = MI->getDebugLoc();
734 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
735 assert(F != PairMap.end());
736 const UUPair &P = F->second;
737
738 if (!Op1.isReg()) {
739 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
740 .add(Op1);
741 } else {
742 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
743 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
744 }
745
746 if (!Op2.isReg()) {
747 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
748 .add(Op2);
749 } else {
750 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
751 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
752 }
753 }
754
splitExt(MachineInstr * MI,const UUPairMap & PairMap)755 void HexagonSplitDoubleRegs::splitExt(MachineInstr *MI,
756 const UUPairMap &PairMap) {
757 MachineOperand &Op0 = MI->getOperand(0);
758 MachineOperand &Op1 = MI->getOperand(1);
759 assert(Op0.isReg() && Op1.isReg());
760
761 MachineBasicBlock &B = *MI->getParent();
762 DebugLoc DL = MI->getDebugLoc();
763 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
764 assert(F != PairMap.end());
765 const UUPair &P = F->second;
766 unsigned RS = getRegState(Op1);
767
768 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
769 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
770 BuildMI(B, MI, DL, TII->get(Hexagon::S2_asr_i_r), P.second)
771 .addReg(Op1.getReg(), RS, Op1.getSubReg())
772 .addImm(31);
773 }
774
splitShift(MachineInstr * MI,const UUPairMap & PairMap)775 void HexagonSplitDoubleRegs::splitShift(MachineInstr *MI,
776 const UUPairMap &PairMap) {
777 using namespace Hexagon;
778
779 MachineOperand &Op0 = MI->getOperand(0);
780 MachineOperand &Op1 = MI->getOperand(1);
781 MachineOperand &Op2 = MI->getOperand(2);
782 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
783 int64_t Sh64 = Op2.getImm();
784 assert(Sh64 >= 0 && Sh64 < 64);
785 unsigned S = Sh64;
786
787 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
788 assert(F != PairMap.end());
789 const UUPair &P = F->second;
790 Register LoR = P.first;
791 Register HiR = P.second;
792
793 unsigned Opc = MI->getOpcode();
794 bool Right = (Opc == S2_lsr_i_p || Opc == S2_asr_i_p);
795 bool Left = !Right;
796 bool Signed = (Opc == S2_asr_i_p);
797
798 MachineBasicBlock &B = *MI->getParent();
799 DebugLoc DL = MI->getDebugLoc();
800 unsigned RS = getRegState(Op1);
801 unsigned ShiftOpc = Left ? S2_asl_i_r
802 : (Signed ? S2_asr_i_r : S2_lsr_i_r);
803 unsigned LoSR = isub_lo;
804 unsigned HiSR = isub_hi;
805
806 if (S == 0) {
807 // No shift, subregister copy.
808 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
809 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
810 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
811 .addReg(Op1.getReg(), RS, HiSR);
812 } else if (S < 32) {
813 const TargetRegisterClass *IntRC = &IntRegsRegClass;
814 Register TmpR = MRI->createVirtualRegister(IntRC);
815 // Expansion:
816 // Shift left: DR = shl R, #s
817 // LoR = shl R.lo, #s
818 // TmpR = extractu R.lo, #s, #32-s
819 // HiR = or (TmpR, asl(R.hi, #s))
820 // Shift right: DR = shr R, #s
821 // HiR = shr R.hi, #s
822 // TmpR = shr R.lo, #s
823 // LoR = insert TmpR, R.hi, #s, #32-s
824
825 // Shift left:
826 // LoR = shl R.lo, #s
827 // Shift right:
828 // TmpR = shr R.lo, #s
829
830 // Make a special case for A2_aslh and A2_asrh (they are predicable as
831 // opposed to S2_asl_i_r/S2_asr_i_r).
832 if (S == 16 && Left)
833 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR)
834 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
835 else if (S == 16 && Signed)
836 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR)
837 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
838 else
839 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
840 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
841 .addImm(S);
842
843 if (Left) {
844 // TmpR = extractu R.lo, #s, #32-s
845 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR)
846 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
847 .addImm(S)
848 .addImm(32-S);
849 // HiR = or (TmpR, asl(R.hi, #s))
850 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
851 .addReg(TmpR)
852 .addReg(Op1.getReg(), RS, HiSR)
853 .addImm(S);
854 } else {
855 // HiR = shr R.hi, #s
856 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
857 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
858 .addImm(S);
859 // LoR = insert TmpR, R.hi, #s, #32-s
860 BuildMI(B, MI, DL, TII->get(S2_insert), LoR)
861 .addReg(TmpR)
862 .addReg(Op1.getReg(), RS, HiSR)
863 .addImm(S)
864 .addImm(32-S);
865 }
866 } else if (S == 32) {
867 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
868 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
869 if (!Signed)
870 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
871 .addImm(0);
872 else // Must be right shift.
873 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
874 .addReg(Op1.getReg(), RS, HiSR)
875 .addImm(31);
876 } else if (S < 64) {
877 S -= 32;
878 if (S == 16 && Left)
879 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR)
880 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
881 else if (S == 16 && Signed)
882 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR)
883 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
884 else
885 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
886 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
887 .addImm(S);
888
889 if (Signed)
890 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
891 .addReg(Op1.getReg(), RS, HiSR)
892 .addImm(31);
893 else
894 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
895 .addImm(0);
896 }
897 }
898
splitAslOr(MachineInstr * MI,const UUPairMap & PairMap)899 void HexagonSplitDoubleRegs::splitAslOr(MachineInstr *MI,
900 const UUPairMap &PairMap) {
901 using namespace Hexagon;
902
903 MachineOperand &Op0 = MI->getOperand(0);
904 MachineOperand &Op1 = MI->getOperand(1);
905 MachineOperand &Op2 = MI->getOperand(2);
906 MachineOperand &Op3 = MI->getOperand(3);
907 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
908 int64_t Sh64 = Op3.getImm();
909 assert(Sh64 >= 0 && Sh64 < 64);
910 unsigned S = Sh64;
911
912 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
913 assert(F != PairMap.end());
914 const UUPair &P = F->second;
915 unsigned LoR = P.first;
916 unsigned HiR = P.second;
917
918 MachineBasicBlock &B = *MI->getParent();
919 DebugLoc DL = MI->getDebugLoc();
920 unsigned RS1 = getRegState(Op1);
921 unsigned RS2 = getRegState(Op2);
922 const TargetRegisterClass *IntRC = &IntRegsRegClass;
923
924 unsigned LoSR = isub_lo;
925 unsigned HiSR = isub_hi;
926
927 // Op0 = S2_asl_i_p_or Op1, Op2, Op3
928 // means: Op0 = or (Op1, asl(Op2, Op3))
929
930 // Expansion of
931 // DR = or (R1, asl(R2, #s))
932 //
933 // LoR = or (R1.lo, asl(R2.lo, #s))
934 // Tmp1 = extractu R2.lo, #s, #32-s
935 // Tmp2 = or R1.hi, Tmp1
936 // HiR = or (Tmp2, asl(R2.hi, #s))
937
938 if (S == 0) {
939 // DR = or (R1, asl(R2, #0))
940 // -> or (R1, R2)
941 // i.e. LoR = or R1.lo, R2.lo
942 // HiR = or R1.hi, R2.hi
943 BuildMI(B, MI, DL, TII->get(A2_or), LoR)
944 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
945 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
946 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
947 .addReg(Op1.getReg(), RS1, HiSR)
948 .addReg(Op2.getReg(), RS2, HiSR);
949 } else if (S < 32) {
950 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), LoR)
951 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
952 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
953 .addImm(S);
954 Register TmpR1 = MRI->createVirtualRegister(IntRC);
955 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
956 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
957 .addImm(S)
958 .addImm(32-S);
959 Register TmpR2 = MRI->createVirtualRegister(IntRC);
960 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
961 .addReg(Op1.getReg(), RS1, HiSR)
962 .addReg(TmpR1);
963 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
964 .addReg(TmpR2)
965 .addReg(Op2.getReg(), RS2, HiSR)
966 .addImm(S);
967 } else if (S == 32) {
968 // DR = or (R1, asl(R2, #32))
969 // -> or R1, R2.lo
970 // LoR = R1.lo
971 // HiR = or R1.hi, R2.lo
972 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
973 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
974 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
975 .addReg(Op1.getReg(), RS1, HiSR)
976 .addReg(Op2.getReg(), RS2, LoSR);
977 } else if (S < 64) {
978 // DR = or (R1, asl(R2, #s))
979 //
980 // LoR = R1:lo
981 // HiR = or (R1:hi, asl(R2:lo, #s-32))
982 S -= 32;
983 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
984 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
985 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
986 .addReg(Op1.getReg(), RS1, HiSR)
987 .addReg(Op2.getReg(), RS2, LoSR)
988 .addImm(S);
989 }
990 }
991
splitInstr(MachineInstr * MI,const UUPairMap & PairMap)992 bool HexagonSplitDoubleRegs::splitInstr(MachineInstr *MI,
993 const UUPairMap &PairMap) {
994 using namespace Hexagon;
995
996 LLVM_DEBUG(dbgs() << "Splitting: " << *MI);
997 bool Split = false;
998 unsigned Opc = MI->getOpcode();
999
1000 switch (Opc) {
1001 case TargetOpcode::PHI:
1002 case TargetOpcode::COPY: {
1003 Register DstR = MI->getOperand(0).getReg();
1004 if (MRI->getRegClass(DstR) == DoubleRC) {
1005 createHalfInstr(Opc, MI, PairMap, isub_lo);
1006 createHalfInstr(Opc, MI, PairMap, isub_hi);
1007 Split = true;
1008 }
1009 break;
1010 }
1011 case A2_andp:
1012 createHalfInstr(A2_and, MI, PairMap, isub_lo);
1013 createHalfInstr(A2_and, MI, PairMap, isub_hi);
1014 Split = true;
1015 break;
1016 case A2_orp:
1017 createHalfInstr(A2_or, MI, PairMap, isub_lo);
1018 createHalfInstr(A2_or, MI, PairMap, isub_hi);
1019 Split = true;
1020 break;
1021 case A2_xorp:
1022 createHalfInstr(A2_xor, MI, PairMap, isub_lo);
1023 createHalfInstr(A2_xor, MI, PairMap, isub_hi);
1024 Split = true;
1025 break;
1026
1027 case L2_loadrd_io:
1028 case L2_loadrd_pi:
1029 case S2_storerd_io:
1030 case S2_storerd_pi:
1031 splitMemRef(MI, PairMap);
1032 Split = true;
1033 break;
1034
1035 case A2_tfrpi:
1036 case CONST64:
1037 splitImmediate(MI, PairMap);
1038 Split = true;
1039 break;
1040
1041 case A2_combineii:
1042 case A4_combineir:
1043 case A4_combineii:
1044 case A4_combineri:
1045 case A2_combinew:
1046 splitCombine(MI, PairMap);
1047 Split = true;
1048 break;
1049
1050 case A2_sxtw:
1051 splitExt(MI, PairMap);
1052 Split = true;
1053 break;
1054
1055 case S2_asl_i_p:
1056 case S2_asr_i_p:
1057 case S2_lsr_i_p:
1058 splitShift(MI, PairMap);
1059 Split = true;
1060 break;
1061
1062 case S2_asl_i_p_or:
1063 splitAslOr(MI, PairMap);
1064 Split = true;
1065 break;
1066
1067 default:
1068 llvm_unreachable("Instruction not splitable");
1069 return false;
1070 }
1071
1072 return Split;
1073 }
1074
replaceSubregUses(MachineInstr * MI,const UUPairMap & PairMap)1075 void HexagonSplitDoubleRegs::replaceSubregUses(MachineInstr *MI,
1076 const UUPairMap &PairMap) {
1077 for (auto &Op : MI->operands()) {
1078 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1079 continue;
1080 Register R = Op.getReg();
1081 UUPairMap::const_iterator F = PairMap.find(R);
1082 if (F == PairMap.end())
1083 continue;
1084 const UUPair &P = F->second;
1085 switch (Op.getSubReg()) {
1086 case Hexagon::isub_lo:
1087 Op.setReg(P.first);
1088 break;
1089 case Hexagon::isub_hi:
1090 Op.setReg(P.second);
1091 break;
1092 }
1093 Op.setSubReg(0);
1094 }
1095 }
1096
collapseRegPairs(MachineInstr * MI,const UUPairMap & PairMap)1097 void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
1098 const UUPairMap &PairMap) {
1099 MachineBasicBlock &B = *MI->getParent();
1100 DebugLoc DL = MI->getDebugLoc();
1101
1102 for (auto &Op : MI->operands()) {
1103 if (!Op.isReg() || !Op.isUse())
1104 continue;
1105 Register R = Op.getReg();
1106 if (!R.isVirtual())
1107 continue;
1108 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
1109 continue;
1110 UUPairMap::const_iterator F = PairMap.find(R);
1111 if (F == PairMap.end())
1112 continue;
1113 const UUPair &Pr = F->second;
1114 Register NewDR = MRI->createVirtualRegister(DoubleRC);
1115 BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
1116 .addReg(Pr.first)
1117 .addImm(Hexagon::isub_lo)
1118 .addReg(Pr.second)
1119 .addImm(Hexagon::isub_hi);
1120 Op.setReg(NewDR);
1121 }
1122 }
1123
splitPartition(const USet & Part)1124 bool HexagonSplitDoubleRegs::splitPartition(const USet &Part) {
1125 using MISet = std::set<MachineInstr *>;
1126
1127 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
1128 bool Changed = false;
1129
1130 LLVM_DEBUG(dbgs() << "Splitting partition: ";
1131 dump_partition(dbgs(), Part, *TRI); dbgs() << '\n');
1132
1133 UUPairMap PairMap;
1134
1135 MISet SplitIns;
1136 for (unsigned DR : Part) {
1137 MachineInstr *DefI = MRI->getVRegDef(DR);
1138 SplitIns.insert(DefI);
1139
1140 // Collect all instructions, including fixed ones. We won't split them,
1141 // but we need to visit them again to insert the REG_SEQUENCE instructions.
1142 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
1143 U != W; ++U)
1144 SplitIns.insert(U->getParent());
1145
1146 Register LoR = MRI->createVirtualRegister(IntRC);
1147 Register HiR = MRI->createVirtualRegister(IntRC);
1148 LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
1149 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
1150 << '\n');
1151 PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
1152 }
1153
1154 MISet Erase;
1155 for (auto MI : SplitIns) {
1156 if (isFixedInstr(MI)) {
1157 collapseRegPairs(MI, PairMap);
1158 } else {
1159 bool Done = splitInstr(MI, PairMap);
1160 if (Done)
1161 Erase.insert(MI);
1162 Changed |= Done;
1163 }
1164 }
1165
1166 for (unsigned DR : Part) {
1167 // Before erasing "double" instructions, revisit all uses of the double
1168 // registers in this partition, and replace all uses of them with subre-
1169 // gisters, with the corresponding single registers.
1170 MISet Uses;
1171 for (auto U = MRI->use_nodbg_begin(DR), W = MRI->use_nodbg_end();
1172 U != W; ++U)
1173 Uses.insert(U->getParent());
1174 for (auto M : Uses)
1175 replaceSubregUses(M, PairMap);
1176 }
1177
1178 for (auto MI : Erase) {
1179 MachineBasicBlock *B = MI->getParent();
1180 B->erase(MI);
1181 }
1182
1183 return Changed;
1184 }
1185
runOnMachineFunction(MachineFunction & MF)1186 bool HexagonSplitDoubleRegs::runOnMachineFunction(MachineFunction &MF) {
1187 if (skipFunction(MF.getFunction()))
1188 return false;
1189
1190 LLVM_DEBUG(dbgs() << "Splitting double registers in function: "
1191 << MF.getName() << '\n');
1192
1193 auto &ST = MF.getSubtarget<HexagonSubtarget>();
1194 TRI = ST.getRegisterInfo();
1195 TII = ST.getInstrInfo();
1196 MRI = &MF.getRegInfo();
1197 MLI = &getAnalysis<MachineLoopInfo>();
1198
1199 UUSetMap P2Rs;
1200 LoopRegMap IRM;
1201
1202 collectIndRegs(IRM);
1203 partitionRegisters(P2Rs);
1204
1205 LLVM_DEBUG({
1206 dbgs() << "Register partitioning: (partition #0 is fixed)\n";
1207 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
1208 dbgs() << '#' << I->first << " -> ";
1209 dump_partition(dbgs(), I->second, *TRI);
1210 dbgs() << '\n';
1211 }
1212 });
1213
1214 bool Changed = false;
1215 int Limit = MaxHSDR;
1216
1217 for (UUSetMap::iterator I = P2Rs.begin(), E = P2Rs.end(); I != E; ++I) {
1218 if (I->first == 0)
1219 continue;
1220 if (Limit >= 0 && Counter >= Limit)
1221 break;
1222 USet &Part = I->second;
1223 LLVM_DEBUG(dbgs() << "Calculating profit for partition #" << I->first
1224 << '\n');
1225 if (!isProfitable(Part, IRM))
1226 continue;
1227 Counter++;
1228 Changed |= splitPartition(Part);
1229 }
1230
1231 return Changed;
1232 }
1233
createHexagonSplitDoubleRegs()1234 FunctionPass *llvm::createHexagonSplitDoubleRegs() {
1235 return new HexagonSplitDoubleRegs();
1236 }
1237