1 //===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass adds the capability to generate pseudo vector/predicate register
10 // printing instructions. These pseudo instructions should be used with the
11 // simulator, NEVER on hardware.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "HexagonInstrInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/TargetOpcodes.h"
25 #include "llvm/IR/DebugLoc.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/Pass.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <string>
33 #include <vector>
34
35 using namespace llvm;
36
37 #define DEBUG_TYPE "hexagon-vector-print"
38
39 static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
40 cl::Hidden, cl::ZeroOrMore, cl::init(false),
41 cl::desc("Enables tracing of vector stores"));
42
43 namespace llvm {
44
45 FunctionPass *createHexagonVectorPrint();
46 void initializeHexagonVectorPrintPass(PassRegistry&);
47
48 } // end namespace llvm
49
50 namespace {
51
52 class HexagonVectorPrint : public MachineFunctionPass {
53 const HexagonSubtarget *QST = nullptr;
54 const HexagonInstrInfo *QII = nullptr;
55 const HexagonRegisterInfo *QRI = nullptr;
56
57 public:
58 static char ID;
59
HexagonVectorPrint()60 HexagonVectorPrint() : MachineFunctionPass(ID) {
61 initializeHexagonVectorPrintPass(*PassRegistry::getPassRegistry());
62 }
63
getPassName() const64 StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
65
66 bool runOnMachineFunction(MachineFunction &Fn) override;
67 };
68
69 } // end anonymous namespace
70
71 char HexagonVectorPrint::ID = 0;
72
isVecReg(unsigned Reg)73 static bool isVecReg(unsigned Reg) {
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) ||
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) ||
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) ||
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
78 }
79
getStringReg(unsigned R)80 static std::string getStringReg(unsigned R) {
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) {
82 static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
83 "28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
84 "30", "31", "32", "33", "34", "35", "36", "37",
85 "38", "39", "3a", "3b", "3c", "3d", "3e", "3f"};
86 return S[R-Hexagon::V0];
87 }
88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) {
89 static const char* S[] = { "00", "01", "02", "03"};
90 return S[R-Hexagon::Q0];
91
92 }
93 llvm_unreachable("valid vreg");
94 }
95
addAsmInstr(MachineBasicBlock * MBB,unsigned Reg,MachineBasicBlock::instr_iterator I,const DebugLoc & DL,const HexagonInstrInfo * QII,MachineFunction & Fn)96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
97 MachineBasicBlock::instr_iterator I,
98 const DebugLoc &DL, const HexagonInstrInfo *QII,
99 MachineFunction &Fn) {
100 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
101 const char *cstr = Fn.createExternalSymbolName(VDescStr);
102 unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
103 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
104 .addExternalSymbol(cstr)
105 .addImm(ExtraInfo);
106 }
107
getInstrVecReg(const MachineInstr & MI,unsigned & Reg)108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
109 if (MI.getNumOperands() < 1) return false;
110 // Vec load or compute.
111 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
112 Reg = MI.getOperand(0).getReg();
113 if (isVecReg(Reg))
114 return !TraceHexVectorStoresOnly;
115 }
116 // Vec store.
117 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
118 Reg = MI.getOperand(2).getReg();
119 if (isVecReg(Reg))
120 return true;
121 }
122 // Vec store post increment.
123 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
124 Reg = MI.getOperand(3).getReg();
125 if (isVecReg(Reg))
126 return true;
127 }
128 return false;
129 }
130
runOnMachineFunction(MachineFunction & Fn)131 bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
132 bool Changed = false;
133 QST = &Fn.getSubtarget<HexagonSubtarget>();
134 QRI = QST->getRegisterInfo();
135 QII = QST->getInstrInfo();
136 std::vector<MachineInstr *> VecPrintList;
137 for (auto &MBB : Fn)
138 for (auto &MI : MBB) {
139 if (MI.isBundle()) {
140 MachineBasicBlock::instr_iterator MII = MI.getIterator();
141 for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
142 if (MII->getNumOperands() < 1)
143 continue;
144 unsigned Reg = 0;
145 if (getInstrVecReg(*MII, Reg)) {
146 VecPrintList.push_back((&*MII));
147 LLVM_DEBUG(dbgs() << "Found vector reg inside bundle \n";
148 MII->dump());
149 }
150 }
151 } else {
152 unsigned Reg = 0;
153 if (getInstrVecReg(MI, Reg)) {
154 VecPrintList.push_back(&MI);
155 LLVM_DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
156 }
157 }
158 }
159
160 Changed = !VecPrintList.empty();
161 if (!Changed)
162 return Changed;
163
164 for (auto *I : VecPrintList) {
165 DebugLoc DL = I->getDebugLoc();
166 MachineBasicBlock *MBB = I->getParent();
167 LLVM_DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
168 unsigned Reg = 0;
169 if (!getInstrVecReg(*I, Reg))
170 llvm_unreachable("Need a vector reg");
171 MachineBasicBlock::instr_iterator MII = I->getIterator();
172 if (I->isInsideBundle()) {
173 LLVM_DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
174 while (MBB->instr_end() != MII && MII->isInsideBundle())
175 MII++;
176 } else {
177 LLVM_DEBUG(dbgs() << "add after instruction\n"; I->dump());
178 MII++;
179 }
180 if (MBB->instr_end() == MII)
181 continue;
182
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');
185 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
186 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
187 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n');
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
189 MII, DL, QII, Fn);
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
191 MII, DL, QII, Fn);
192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
193 LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n');
194 addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
195 } else
196 llvm_unreachable("Bad Vector reg");
197 }
198 return Changed;
199 }
200
201 //===----------------------------------------------------------------------===//
202 // Public Constructor Functions
203 //===----------------------------------------------------------------------===//
204 INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
205 "Hexagon VectorPrint pass", false, false)
206
createHexagonVectorPrint()207 FunctionPass *llvm::createHexagonVectorPrint() {
208 return new HexagonVectorPrint();
209 }
210