1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3
4...
5---
6name:            or_combine_sext
7tracksRegLiveness: true
8body:             |
9  bb.0:
10    liveins: $w0, $w1
11    ; or (sext X), (sext Y) --> sext (or X, Y)
12    ;
13    ; CHECK-LABEL: name: or_combine_sext
14    ; CHECK: liveins: $w0, $w1
15    ; CHECK: %x:_(s32) = COPY $w0
16    ; CHECK: %y:_(s32) = COPY $w1
17    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
18    ; CHECK: %logic_op:_(s64) = G_SEXT [[OR]](s32)
19    ; CHECK: $x0 = COPY %logic_op(s64)
20    ; CHECK: RET_ReallyLR implicit $x0
21    %x:_(s32) = COPY $w0
22    %y:_(s32) = COPY $w1
23    %hand1:_(s64) = G_SEXT %x(s32)
24    %hand2:_(s64) = G_SEXT %y(s32)
25    %logic_op:_(s64) = G_OR %hand1, %hand2
26    $x0 = COPY %logic_op(s64)
27    RET_ReallyLR implicit $x0
28
29...
30---
31name:            or_combine_zext
32tracksRegLiveness: true
33body:             |
34  bb.0:
35    liveins: $w0, $w1
36    ; or (zext X), (zext Y) --> zext (or X, Y)
37    ;
38    ; CHECK-LABEL: name: or_combine_zext
39    ; CHECK: liveins: $w0, $w1
40    ; CHECK: %x:_(s32) = COPY $w0
41    ; CHECK: %y:_(s32) = COPY $w1
42    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
43    ; CHECK: %logic_op:_(s64) = G_ZEXT [[OR]](s32)
44    ; CHECK: $x0 = COPY %logic_op(s64)
45    ; CHECK: RET_ReallyLR implicit $x0
46    %x:_(s32) = COPY $w0
47    %y:_(s32) = COPY $w1
48    %hand1:_(s64) = G_ZEXT %x(s32)
49    %hand2:_(s64) = G_ZEXT %y(s32)
50    %logic_op:_(s64) = G_OR %hand1, %hand2
51    $x0 = COPY %logic_op(s64)
52    RET_ReallyLR implicit $x0
53
54...
55---
56name:            or_combine_anyext
57tracksRegLiveness: true
58body:             |
59  bb.0:
60    liveins: $w0, $w1
61    ; or (anyext X), (anyext Y) --> anyext (or X, Y)
62    ;
63    ; CHECK-LABEL: name: or_combine_anyext
64    ; CHECK: liveins: $w0, $w1
65    ; CHECK: %x:_(s32) = COPY $w0
66    ; CHECK: %y:_(s32) = COPY $w1
67    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR %x, %y
68    ; CHECK: %logic_op:_(s64) = G_ANYEXT [[OR]](s32)
69    ; CHECK: $x0 = COPY %logic_op(s64)
70    ; CHECK: RET_ReallyLR implicit $x0
71    %x:_(s32) = COPY $w0
72    %y:_(s32) = COPY $w1
73    %hand1:_(s64) = G_ANYEXT %x(s32)
74    %hand2:_(s64) = G_ANYEXT %y(s32)
75    %logic_op:_(s64) = G_OR %hand1, %hand2
76    $x0 = COPY %logic_op(s64)
77    RET_ReallyLR implicit $x0
78
79...
80---
81name:            and_combine_sext
82tracksRegLiveness: true
83body:             |
84  bb.0:
85    liveins: $w0, $w1
86    ; and (sext X), (sext Y) --> sext (and X, Y)
87    ;
88    ; CHECK-LABEL: name: and_combine_sext
89    ; CHECK: liveins: $w0, $w1
90    ; CHECK: %x:_(s32) = COPY $w0
91    ; CHECK: %y:_(s32) = COPY $w1
92    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y
93    ; CHECK: %logic_op:_(s64) = G_SEXT [[AND]](s32)
94    ; CHECK: $x0 = COPY %logic_op(s64)
95    ; CHECK: RET_ReallyLR implicit $x0
96    %x:_(s32) = COPY $w0
97    %y:_(s32) = COPY $w1
98    %hand1:_(s64) = G_SEXT %x(s32)
99    %hand2:_(s64) = G_SEXT %y(s32)
100    %logic_op:_(s64) = G_AND %hand1, %hand2
101    $x0 = COPY %logic_op(s64)
102    RET_ReallyLR implicit $x0
103
104...
105---
106name:            and_combine_zext
107tracksRegLiveness: true
108body:             |
109  bb.0:
110    liveins: $w0, $w1
111    ; and (zext X), (zext Y) --> zext (and X, Y)
112    ;
113    ; CHECK-LABEL: name: and_combine_zext
114    ; CHECK: liveins: $w0, $w1
115    ; CHECK: %x:_(s32) = COPY $w0
116    ; CHECK: %y:_(s32) = COPY $w1
117    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y
118    ; CHECK: %logic_op:_(s64) = G_ZEXT [[AND]](s32)
119    ; CHECK: $x0 = COPY %logic_op(s64)
120    ; CHECK: RET_ReallyLR implicit $x0
121    %x:_(s32) = COPY $w0
122    %y:_(s32) = COPY $w1
123    %hand1:_(s64) = G_ZEXT %x(s32)
124    %hand2:_(s64) = G_ZEXT %y(s32)
125    %logic_op:_(s64) = G_AND %hand1, %hand2
126    $x0 = COPY %logic_op(s64)
127    RET_ReallyLR implicit $x0
128
129...
130---
131name:            and_combine_anyext
132tracksRegLiveness: true
133body:             |
134  bb.0:
135    liveins: $w0, $w1
136    ; and (anyext X), (anyext Y) --> anyext (and X, Y)
137    ;
138    ; CHECK-LABEL: name: and_combine_anyext
139    ; CHECK: liveins: $w0, $w1
140    ; CHECK: %x:_(s32) = COPY $w0
141    ; CHECK: %y:_(s32) = COPY $w1
142    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND %x, %y
143    ; CHECK: %logic_op:_(s64) = G_ANYEXT [[AND]](s32)
144    ; CHECK: $x0 = COPY %logic_op(s64)
145    ; CHECK: RET_ReallyLR implicit $x0
146    %x:_(s32) = COPY $w0
147    %y:_(s32) = COPY $w1
148    %hand1:_(s64) = G_ANYEXT %x(s32)
149    %hand2:_(s64) = G_ANYEXT %y(s32)
150    %logic_op:_(s64) = G_AND %hand1, %hand2
151    $x0 = COPY %logic_op(s64)
152    RET_ReallyLR implicit $x0
153
154...
155---
156name:            xor_combine_sext
157tracksRegLiveness: true
158body:             |
159  bb.0:
160    liveins: $w0, $w1
161    ; xor (sext X), (sext Y) --> sext (xor X, Y)
162    ;
163    ; CHECK-LABEL: name: xor_combine_sext
164    ; CHECK: liveins: $w0, $w1
165    ; CHECK: %x:_(s32) = COPY $w0
166    ; CHECK: %y:_(s32) = COPY $w1
167    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y
168    ; CHECK: %logic_op:_(s64) = G_SEXT [[XOR]](s32)
169    ; CHECK: $x0 = COPY %logic_op(s64)
170    ; CHECK: RET_ReallyLR implicit $x0
171    %x:_(s32) = COPY $w0
172    %y:_(s32) = COPY $w1
173    %hand1:_(s64) = G_SEXT %x(s32)
174    %hand2:_(s64) = G_SEXT %y(s32)
175    %logic_op:_(s64) = G_XOR %hand1, %hand2
176    $x0 = COPY %logic_op(s64)
177    RET_ReallyLR implicit $x0
178
179...
180---
181name:            xor_combine_zext
182tracksRegLiveness: true
183body:             |
184  bb.0:
185    liveins: $w0, $w1
186    ; xor (zext X), (zext Y) --> zext (xor X, Y)
187    ;
188    ; CHECK-LABEL: name: xor_combine_zext
189    ; CHECK: liveins: $w0, $w1
190    ; CHECK: %x:_(s32) = COPY $w0
191    ; CHECK: %y:_(s32) = COPY $w1
192    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y
193    ; CHECK: %logic_op:_(s64) = G_ZEXT [[XOR]](s32)
194    ; CHECK: $x0 = COPY %logic_op(s64)
195    ; CHECK: RET_ReallyLR implicit $x0
196    %x:_(s32) = COPY $w0
197    %y:_(s32) = COPY $w1
198    %hand1:_(s64) = G_ZEXT %x(s32)
199    %hand2:_(s64) = G_ZEXT %y(s32)
200    %logic_op:_(s64) = G_XOR %hand1, %hand2
201    $x0 = COPY %logic_op(s64)
202    RET_ReallyLR implicit $x0
203
204...
205---
206name:            xor_combine_anyext
207tracksRegLiveness: true
208body:             |
209  bb.0:
210    liveins: $w0, $w1
211    ; xor (anyext X), (anyext Y) --> anyext (xor X, Y)
212    ;
213    ; CHECK-LABEL: name: xor_combine_anyext
214    ; CHECK: liveins: $w0, $w1
215    ; CHECK: %x:_(s32) = COPY $w0
216    ; CHECK: %y:_(s32) = COPY $w1
217    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR %x, %y
218    ; CHECK: %logic_op:_(s64) = G_ANYEXT [[XOR]](s32)
219    ; CHECK: $x0 = COPY %logic_op(s64)
220    ; CHECK: RET_ReallyLR implicit $x0
221    %x:_(s32) = COPY $w0
222    %y:_(s32) = COPY $w1
223    %hand1:_(s64) = G_ANYEXT %x(s32)
224    %hand2:_(s64) = G_ANYEXT %y(s32)
225    %logic_op:_(s64) = G_XOR %hand1, %hand2
226    $x0 = COPY %logic_op(s64)
227    RET_ReallyLR implicit $x0
228
229...
230---
231name:            dont_combine_different_types
232tracksRegLiveness: true
233body:             |
234  bb.0:
235    liveins: $w0, $w1
236    ; When %x and %y don't have the same type, don't perform the combine.
237    ;
238    ; CHECK-LABEL: name: dont_combine_different_types
239    ; CHECK: liveins: $w0, $w1
240    ; CHECK: %x:_(s32) = COPY $w0
241    ; CHECK: %hand1:_(s32) = COPY $w1
242    ; CHECK: %y:_(s16) = G_TRUNC %hand1(s32)
243    ; CHECK: %hand2:_(s64) = G_SEXT %x(s32)
244    ; CHECK: %logic_op:_(s64) = G_SEXT %y(s16)
245    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR %hand2, %logic_op
246    ; CHECK: $x0 = COPY [[OR]](s64)
247    ; CHECK: RET_ReallyLR implicit $x0
248    %x:_(s32) = COPY $w0
249    %hand1:_(s32) = COPY $w1
250    %y:_(s16) = G_TRUNC %hand1(s32)
251    %hand2:_(s64) = G_SEXT %x(s32)
252    %logic_op:_(s64) = G_SEXT %y(s16)
253    %5:_(s64) = G_OR %hand2, %logic_op
254    $x0 = COPY %5(s64)
255    RET_ReallyLR implicit $x0
256
257...
258---
259name:            illegal_ty
260tracksRegLiveness: true
261legalized: true
262body:             |
263  bb.0:
264    liveins: $w0, $w1
265    ; Pre-legalization, it's okay to produce illegal types.
266    ;
267    ; CHECK-LABEL: name: illegal_ty
268    ; CHECK: liveins: $w0, $w1
269    ; CHECK: %x_wide:_(s32) = COPY $w0
270    ; CHECK: %y_wide:_(s32) = COPY $w1
271    ; CHECK: %x:_(s1) = G_TRUNC %x_wide(s32)
272    ; CHECK: %y:_(s1) = G_TRUNC %y_wide(s32)
273    ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR %x, %y
274    ; CHECK: %logic_op:_(s64) = G_SEXT [[OR]](s1)
275    ; CHECK: $x0 = COPY %logic_op(s64)
276    ; CHECK: RET_ReallyLR implicit $x0
277    %x_wide:_(s32) = COPY $w0
278    %y_wide:_(s32) = COPY $w1
279    %x:_(s1) = G_TRUNC %x_wide
280    %y:_(s1) = G_TRUNC %y_wide
281    %hand1:_(s64) = G_SEXT %x(s1)
282    %hand2:_(s64) = G_SEXT %y(s1)
283    %logic_op:_(s64) = G_OR %hand1, %hand2
284    $x0 = COPY %logic_op(s64)
285    RET_ReallyLR implicit $x0
286
287...
288---
289name:            or_combine_and
290tracksRegLiveness: true
291body:             |
292  bb.0:
293    ; or (and x, z), (and y, z) --> and (or x, y), z
294    ;
295    liveins: $x0, $x1, $x2
296    ; CHECK-LABEL: name: or_combine_and
297    ; CHECK: liveins: $x0, $x1, $x2
298    ; CHECK: %x:_(s64) = COPY $x0
299    ; CHECK: %y:_(s64) = COPY $x1
300    ; CHECK: %z:_(s64) = COPY $x2
301    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y
302    ; CHECK: %logic_op:_(s64) = G_AND [[OR]], %z
303    ; CHECK: $x0 = COPY %logic_op(s64)
304    ; CHECK: RET_ReallyLR implicit $x0
305    %x:_(s64) = COPY $x0
306    %y:_(s64) = COPY $x1
307    %z:_(s64) = COPY $x2
308    %hand1:_(s64) = G_AND %x(s64), %z
309    %hand2:_(s64) = G_AND %y(s64), %z
310    %logic_op:_(s64) = G_OR %hand1, %hand2
311    $x0 = COPY %logic_op(s64)
312    RET_ReallyLR implicit $x0
313
314...
315---
316name:            or_combine_ashr
317tracksRegLiveness: true
318body:             |
319  bb.0:
320    ; or (ashr x, z), (ashr y, z) --> ashr (or x, y), z
321    ;
322    liveins: $x0, $x1, $x2
323    ; CHECK-LABEL: name: or_combine_ashr
324    ; CHECK: liveins: $x0, $x1, $x2
325    ; CHECK: %x:_(s64) = COPY $x0
326    ; CHECK: %y:_(s64) = COPY $x1
327    ; CHECK: %z:_(s64) = COPY $x2
328    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y
329    ; CHECK: %logic_op:_(s64) = G_ASHR [[OR]], %z(s64)
330    ; CHECK: $x0 = COPY %logic_op(s64)
331    ; CHECK: RET_ReallyLR implicit $x0
332    %x:_(s64) = COPY $x0
333    %y:_(s64) = COPY $x1
334    %z:_(s64) = COPY $x2
335    %hand1:_(s64) = G_ASHR %x(s64), %z
336    %hand2:_(s64) = G_ASHR %y(s64), %z
337    %logic_op:_(s64) = G_OR %hand1, %hand2
338    $x0 = COPY %logic_op(s64)
339    RET_ReallyLR implicit $x0
340
341...
342---
343name:            or_combine_lshr
344tracksRegLiveness: true
345body:             |
346  bb.0:
347    ; or (lshr x, z), (lshr y, z) --> lshr (or x, y), z
348    ;
349    liveins: $x0, $x1, $x2
350    ; CHECK-LABEL: name: or_combine_lshr
351    ; CHECK: liveins: $x0, $x1, $x2
352    ; CHECK: %x:_(s64) = COPY $x0
353    ; CHECK: %y:_(s64) = COPY $x1
354    ; CHECK: %z:_(s64) = COPY $x2
355    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y
356    ; CHECK: %logic_op:_(s64) = G_LSHR [[OR]], %z(s64)
357    ; CHECK: $x0 = COPY %logic_op(s64)
358    ; CHECK: RET_ReallyLR implicit $x0
359    %x:_(s64) = COPY $x0
360    %y:_(s64) = COPY $x1
361    %z:_(s64) = COPY $x2
362    %hand1:_(s64) = G_LSHR %x(s64), %z
363    %hand2:_(s64) = G_LSHR %y(s64), %z
364    %logic_op:_(s64) = G_OR %hand1, %hand2
365    $x0 = COPY %logic_op(s64)
366    RET_ReallyLR implicit $x0
367
368...
369---
370name:            or_combine_shl
371tracksRegLiveness: true
372body:             |
373  bb.0:
374    ; or (shl x, z), (shl y, z) --> shl (or x, y), z
375    ;
376    liveins: $x0, $x1, $x2
377    ; CHECK-LABEL: name: or_combine_shl
378    ; CHECK: liveins: $x0, $x1, $x2
379    ; CHECK: %x:_(s64) = COPY $x0
380    ; CHECK: %y:_(s64) = COPY $x1
381    ; CHECK: %z:_(s64) = COPY $x2
382    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR %x, %y
383    ; CHECK: %logic_op:_(s64) = G_SHL [[OR]], %z(s64)
384    ; CHECK: $x0 = COPY %logic_op(s64)
385    ; CHECK: RET_ReallyLR implicit $x0
386    %x:_(s64) = COPY $x0
387    %y:_(s64) = COPY $x1
388    %z:_(s64) = COPY $x2
389    %hand1:_(s64) = G_SHL %x(s64), %z
390    %hand2:_(s64) = G_SHL %y(s64), %z
391    %logic_op:_(s64) = G_OR %hand1, %hand2
392    $x0 = COPY %logic_op(s64)
393    RET_ReallyLR implicit $x0
394
395...
396---
397name:            xor_combine_and
398tracksRegLiveness: true
399body:             |
400  bb.0:
401    ; xor (and x, z), (and y, z) --> and (xor x, y), z
402    ;
403    liveins: $x0, $x1, $x2
404    ; CHECK-LABEL: name: xor_combine_and
405    ; CHECK: liveins: $x0, $x1, $x2
406    ; CHECK: %x:_(s64) = COPY $x0
407    ; CHECK: %y:_(s64) = COPY $x1
408    ; CHECK: %z:_(s64) = COPY $x2
409    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y
410    ; CHECK: %logic_op:_(s64) = G_AND [[XOR]], %z
411    ; CHECK: $x0 = COPY %logic_op(s64)
412    ; CHECK: RET_ReallyLR implicit $x0
413    %x:_(s64) = COPY $x0
414    %y:_(s64) = COPY $x1
415    %z:_(s64) = COPY $x2
416    %hand1:_(s64) = G_AND %x(s64), %z
417    %hand2:_(s64) = G_AND %y(s64), %z
418    %logic_op:_(s64) = G_XOR %hand1, %hand2
419    $x0 = COPY %logic_op(s64)
420    RET_ReallyLR implicit $x0
421
422...
423---
424name:            xor_combine_ashr
425tracksRegLiveness: true
426body:             |
427  bb.0:
428    ; xor (ashr x, z), (ashr y, z) --> ashr (xor x, y), z
429    ;
430    liveins: $x0, $x1, $x2
431    ; CHECK-LABEL: name: xor_combine_ashr
432    ; CHECK: liveins: $x0, $x1, $x2
433    ; CHECK: %x:_(s64) = COPY $x0
434    ; CHECK: %y:_(s64) = COPY $x1
435    ; CHECK: %z:_(s64) = COPY $x2
436    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y
437    ; CHECK: %logic_op:_(s64) = G_ASHR [[XOR]], %z(s64)
438    ; CHECK: $x0 = COPY %logic_op(s64)
439    ; CHECK: RET_ReallyLR implicit $x0
440    %x:_(s64) = COPY $x0
441    %y:_(s64) = COPY $x1
442    %z:_(s64) = COPY $x2
443    %hand1:_(s64) = G_ASHR %x(s64), %z
444    %hand2:_(s64) = G_ASHR %y(s64), %z
445    %logic_op:_(s64) = G_XOR %hand1, %hand2
446    $x0 = COPY %logic_op(s64)
447    RET_ReallyLR implicit $x0
448
449...
450---
451name:            xor_combine_lshr
452tracksRegLiveness: true
453body:             |
454  bb.0:
455    ; xor (lshr x, z), (lshr y, z) --> lshr (xor x, y), z
456    ;
457    liveins: $x0, $x1, $x2
458    ; CHECK-LABEL: name: xor_combine_lshr
459    ; CHECK: liveins: $x0, $x1, $x2
460    ; CHECK: %x:_(s64) = COPY $x0
461    ; CHECK: %y:_(s64) = COPY $x1
462    ; CHECK: %z:_(s64) = COPY $x2
463    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y
464    ; CHECK: %logic_op:_(s64) = G_LSHR [[XOR]], %z(s64)
465    ; CHECK: $x0 = COPY %logic_op(s64)
466    ; CHECK: RET_ReallyLR implicit $x0
467    %x:_(s64) = COPY $x0
468    %y:_(s64) = COPY $x1
469    %z:_(s64) = COPY $x2
470    %hand1:_(s64) = G_LSHR %x(s64), %z
471    %hand2:_(s64) = G_LSHR %y(s64), %z
472    %logic_op:_(s64) = G_XOR %hand1, %hand2
473    $x0 = COPY %logic_op(s64)
474    RET_ReallyLR implicit $x0
475
476...
477---
478name:            xor_combine_shl
479tracksRegLiveness: true
480body:             |
481  bb.0:
482    ; xor (shl x, z), (shl y, z) --> shl (xor x, y), z
483    ;
484    liveins: $x0, $x1, $x2
485    ; CHECK-LABEL: name: xor_combine_shl
486    ; CHECK: liveins: $x0, $x1, $x2
487    ; CHECK: %x:_(s64) = COPY $x0
488    ; CHECK: %y:_(s64) = COPY $x1
489    ; CHECK: %z:_(s64) = COPY $x2
490    ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR %x, %y
491    ; CHECK: %logic_op:_(s64) = G_SHL [[XOR]], %z(s64)
492    ; CHECK: $x0 = COPY %logic_op(s64)
493    ; CHECK: RET_ReallyLR implicit $x0
494    %x:_(s64) = COPY $x0
495    %y:_(s64) = COPY $x1
496    %z:_(s64) = COPY $x2
497    %hand1:_(s64) = G_SHL %x(s64), %z
498    %hand2:_(s64) = G_SHL %y(s64), %z
499    %logic_op:_(s64) = G_XOR %hand1, %hand2
500    $x0 = COPY %logic_op(s64)
501    RET_ReallyLR implicit $x0
502
503...
504---
505name:            and_combine_and
506tracksRegLiveness: true
507body:             |
508  bb.0:
509    ; and (and x, z), (and y, z) --> and (and x, y), z
510    ;
511    liveins: $x0, $x1, $x2
512    ; CHECK-LABEL: name: and_combine_and
513    ; CHECK: liveins: $x0, $x1, $x2
514    ; CHECK: %x:_(s64) = COPY $x0
515    ; CHECK: %y:_(s64) = COPY $x1
516    ; CHECK: %z:_(s64) = COPY $x2
517    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y
518    ; CHECK: %logic_op:_(s64) = G_AND [[AND]], %z
519    ; CHECK: $x0 = COPY %logic_op(s64)
520    ; CHECK: RET_ReallyLR implicit $x0
521    %x:_(s64) = COPY $x0
522    %y:_(s64) = COPY $x1
523    %z:_(s64) = COPY $x2
524    %hand1:_(s64) = G_AND %x(s64), %z
525    %hand2:_(s64) = G_AND %y(s64), %z
526    %logic_op:_(s64) = G_AND %hand1, %hand2
527    $x0 = COPY %logic_op(s64)
528    RET_ReallyLR implicit $x0
529
530...
531---
532name:            and_combine_ashr
533tracksRegLiveness: true
534body:             |
535  bb.0:
536    ; and (ashr x, z), (ashr y, z) --> ashr (and x, y), z
537    ;
538    liveins: $x0, $x1, $x2
539    ; CHECK-LABEL: name: and_combine_ashr
540    ; CHECK: liveins: $x0, $x1, $x2
541    ; CHECK: %x:_(s64) = COPY $x0
542    ; CHECK: %y:_(s64) = COPY $x1
543    ; CHECK: %z:_(s64) = COPY $x2
544    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y
545    ; CHECK: %logic_op:_(s64) = G_ASHR [[AND]], %z(s64)
546    ; CHECK: $x0 = COPY %logic_op(s64)
547    ; CHECK: RET_ReallyLR implicit $x0
548    %x:_(s64) = COPY $x0
549    %y:_(s64) = COPY $x1
550    %z:_(s64) = COPY $x2
551    %hand1:_(s64) = G_ASHR %x(s64), %z
552    %hand2:_(s64) = G_ASHR %y(s64), %z
553    %logic_op:_(s64) = G_AND %hand1, %hand2
554    $x0 = COPY %logic_op(s64)
555    RET_ReallyLR implicit $x0
556
557...
558---
559name:            and_combine_lshr
560tracksRegLiveness: true
561body:             |
562  bb.0:
563    ; and (lshr x, z), (lshr y, z) --> lshr (and x, y), z
564    ;
565    liveins: $x0, $x1, $x2
566    ; CHECK-LABEL: name: and_combine_lshr
567    ; CHECK: liveins: $x0, $x1, $x2
568    ; CHECK: %x:_(s64) = COPY $x0
569    ; CHECK: %y:_(s64) = COPY $x1
570    ; CHECK: %z:_(s64) = COPY $x2
571    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y
572    ; CHECK: %logic_op:_(s64) = G_LSHR [[AND]], %z(s64)
573    ; CHECK: $x0 = COPY %logic_op(s64)
574    ; CHECK: RET_ReallyLR implicit $x0
575    %x:_(s64) = COPY $x0
576    %y:_(s64) = COPY $x1
577    %z:_(s64) = COPY $x2
578    %hand1:_(s64) = G_LSHR %x(s64), %z
579    %hand2:_(s64) = G_LSHR %y(s64), %z
580    %logic_op:_(s64) = G_AND %hand1, %hand2
581    $x0 = COPY %logic_op(s64)
582    RET_ReallyLR implicit $x0
583
584...
585---
586name:            and_combine_shl
587tracksRegLiveness: true
588body:             |
589  bb.0:
590    ; and (shl x, z), (shl y, z) --> shl (and x, y), z
591    ;
592    liveins: $x0, $x1, $x2
593    ; CHECK-LABEL: name: and_combine_shl
594    ; CHECK: liveins: $x0, $x1, $x2
595    ; CHECK: %x:_(s64) = COPY $x0
596    ; CHECK: %y:_(s64) = COPY $x1
597    ; CHECK: %z:_(s64) = COPY $x2
598    ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND %x, %y
599    ; CHECK: %logic_op:_(s64) = G_SHL [[AND]], %z(s64)
600    ; CHECK: $x0 = COPY %logic_op(s64)
601    ; CHECK: RET_ReallyLR implicit $x0
602    %x:_(s64) = COPY $x0
603    %y:_(s64) = COPY $x1
604    %z:_(s64) = COPY $x2
605    %hand1:_(s64) = G_SHL %x(s64), %z
606    %hand2:_(s64) = G_SHL %y(s64), %z
607    %logic_op:_(s64) = G_AND %hand1, %hand2
608    $x0 = COPY %logic_op(s64)
609    RET_ReallyLR implicit $x0
610
611...
612---
613name:            dont_combine_different_defs_on_binop
614tracksRegLiveness: true
615body:             |
616  bb.0:
617    ; z1 != z2, so don't combine.
618    ;
619    liveins: $x0, $x1, $x2, $x3
620    ; CHECK-LABEL: name: dont_combine_different_defs_on_binop
621    ; CHECK: liveins: $x0, $x1, $x2, $x3
622    ; CHECK: %x:_(s64) = COPY $x0
623    ; CHECK: %y:_(s64) = COPY $x1
624    ; CHECK: %z1:_(s64) = COPY $x2
625    ; CHECK: %z2:_(s64) = COPY $x3
626    ; CHECK: %hand1:_(s64) = G_AND %x, %z1
627    ; CHECK: %hand2:_(s64) = G_AND %y, %z2
628    ; CHECK: %logic_op:_(s64) = G_OR %hand1, %hand2
629    ; CHECK: $x0 = COPY %logic_op(s64)
630    ; CHECK: RET_ReallyLR implicit $x0
631    %x:_(s64) = COPY $x0
632    %y:_(s64) = COPY $x1
633    %z1:_(s64) = COPY $x2
634    %z2:_(s64) = COPY $x3
635    %hand1:_(s64) = G_AND %x(s64), %z1
636    %hand2:_(s64) = G_AND %y(s64), %z2
637    %logic_op:_(s64) = G_OR %hand1, %hand2
638    $x0 = COPY %logic_op(s64)
639    RET_ReallyLR implicit $x0
640
641...
642---
643name: dont_combine_more_than_one_use
644tracksRegLiveness: true
645body:             |
646  bb.0:
647    liveins: $w0, $w1
648    ; The LHS register is used more than once. Don't combine.
649    ;
650    ; CHECK-LABEL: name: dont_combine_more_than_one_use
651    ; CHECK: liveins: $w0, $w1
652    ; CHECK: %x:_(s32) = COPY $w0
653    ; CHECK: %y:_(s32) = COPY $w1
654    ; CHECK: %hand1:_(s64) = G_SEXT %x(s32)
655    ; CHECK: %hand2:_(s64) = G_SEXT %y(s32)
656    ; CHECK: %logic_op:_(s64) = G_OR %hand1, %hand2
657    ; CHECK: %other_op:_(s64) = G_ADD %hand1, %logic_op
658    ; CHECK: $x0 = COPY %other_op(s64)
659    ; CHECK: RET_ReallyLR implicit $x0
660    %x:_(s32) = COPY $w0
661    %y:_(s32) = COPY $w1
662    %hand1:_(s64) = G_SEXT %x(s32)
663    %hand2:_(s64) = G_SEXT %y(s32)
664    %logic_op:_(s64) = G_OR %hand1, %hand2
665    %other_op:_(s64) = G_ADD %hand1, %logic_op
666    $x0 = COPY %other_op(s64)
667    RET_ReallyLR implicit $x0
668
669...
670---
671name:           combine_vector
672tracksRegLiveness: true
673body:             |
674  bb.0:
675    liveins: $d0, $d1
676    ; Show that we can combine vector types.
677    ;
678    ; CHECK-LABEL: name: combine_vector
679    ; CHECK: liveins: $d0, $d1
680    ; CHECK: %x:_(<2 x s32>) = COPY $d0
681    ; CHECK: %y:_(<2 x s32>) = COPY $d1
682    ; CHECK: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR %x, %y
683    ; CHECK: %logic_op:_(<2 x s64>) = G_SEXT [[OR]](<2 x s32>)
684    ; CHECK: $q0 = COPY %logic_op(<2 x s64>)
685    ; CHECK: RET_ReallyLR implicit $q0
686    %x:_(<2 x s32>) = COPY $d0
687    %y:_(<2 x s32>) = COPY $d1
688    %hand1:_(<2 x s64>) = G_SEXT %x(<2 x s32>)
689    %hand2:_(<2 x s64>) = G_SEXT %y(<2 x s32>)
690    %logic_op:_(<2 x s64>) = G_OR %hand1, %hand2
691    $q0 = COPY %logic_op(<2 x s64>)
692    RET_ReallyLR implicit $q0
693