1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=machine-scheduler -o - %s | FileCheck %s 3--- 4# Check that machine-scheduler's BotHeightReduce heuristic puts the LD 8 in 5# between the final run of MULLDs and the LDXs that feed them, to try to hide 6# the latency of the LDXs. 7name: test 8tracksRegLiveness: true 9body: | 10 ; CHECK-LABEL: name: test 11 ; CHECK: bb.0: 12 ; CHECK: successors: %bb.1(0x80000000) 13 ; CHECK: liveins: $x3, $x4 14 ; CHECK: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x4 15 ; CHECK: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3 16 ; CHECK: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY1]], 1 17 ; CHECK: [[CMPLDI:%[0-9]+]]:crrc = CMPLDI [[COPY]], 1 18 ; CHECK: [[LI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = LI8 1 19 ; CHECK: [[ISEL8_:%[0-9]+]]:g8rc = ISEL8 [[COPY]], [[LI8_]], [[CMPLDI]].sub_gt 20 ; CHECK: MTCTR8loop [[ISEL8_]], implicit-def dead $ctr8 21 ; CHECK: [[LI8_1:%[0-9]+]]:g8rc = LI8 0 22 ; CHECK: [[LI8_2:%[0-9]+]]:g8rc = LI8 2 23 ; CHECK: [[LI8_3:%[0-9]+]]:g8rc = LI8 3 24 ; CHECK: [[LI8_4:%[0-9]+]]:g8rc = LI8 5 25 ; CHECK: [[LI8_5:%[0-9]+]]:g8rc = LI8 6 26 ; CHECK: [[LI8_6:%[0-9]+]]:g8rc = LI8 7 27 ; CHECK: bb.1: 28 ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) 29 ; CHECK: [[LD:%[0-9]+]]:g8rc = LD 0, [[ADDI8_]] :: (load 8) 30 ; CHECK: [[LDX:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_]] :: (load 8) 31 ; CHECK: [[LDX1:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_3]] :: (load 8) 32 ; CHECK: [[LD1:%[0-9]+]]:g8rc = LD 4, [[ADDI8_]] :: (load 8) 33 ; CHECK: [[LDX2:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_4]] :: (load 8) 34 ; CHECK: [[LDX3:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_5]] :: (load 8) 35 ; CHECK: [[LDX4:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_6]] :: (load 8) 36 ; CHECK: [[LD2:%[0-9]+]]:g8rc = LD 8, [[ADDI8_]] :: (load 8) 37 ; CHECK: [[MULLD:%[0-9]+]]:g8rc = MULLD [[LDX]], [[LD]] 38 ; CHECK: [[LDX5:%[0-9]+]]:g8rc = LDX [[ADDI8_]], [[LI8_2]] :: (load 8) 39 ; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[ADDI8_]], 1 40 ; CHECK: [[MULLD1:%[0-9]+]]:g8rc = MULLD [[MULLD]], [[LDX5]] 41 ; CHECK: [[MULLD2:%[0-9]+]]:g8rc = MULLD [[MULLD1]], [[LDX1]] 42 ; CHECK: [[MULLD3:%[0-9]+]]:g8rc = MULLD [[MULLD2]], [[LD1]] 43 ; CHECK: [[MULLD4:%[0-9]+]]:g8rc = MULLD [[MULLD3]], [[LDX2]] 44 ; CHECK: [[MULLD5:%[0-9]+]]:g8rc = MULLD [[MULLD4]], [[LDX3]] 45 ; CHECK: [[MULLD6:%[0-9]+]]:g8rc = MULLD [[MULLD5]], [[LDX4]] 46 ; CHECK: [[MADDLD8_:%[0-9]+]]:g8rc = MADDLD8 [[MULLD6]], [[LD2]], [[MADDLD8_]] 47 ; CHECK: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_1]] 48 ; CHECK: BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 49 ; CHECK: B %bb.2 50 ; CHECK: bb.2: 51 bb.0: 52 liveins: $x3, $x4 53 54 %0:g8rc_and_g8rc_nox0 = COPY $x4 55 %1:g8rc_and_g8rc_nox0 = COPY $x3 56 %2:g8rc_and_g8rc_nox0 = ADDI8 %1, 1 57 %3:crrc = CMPLDI %0, 1 58 %4:g8rc_and_g8rc_nox0 = LI8 1 59 %5:g8rc = ISEL8 %0, %4, %3.sub_gt 60 MTCTR8loop %5, implicit-def dead $ctr8 61 %6:g8rc = LI8 0 62 %7:g8rc = LI8 2 63 %8:g8rc = LI8 3 64 %9:g8rc = LI8 5 65 %10:g8rc = LI8 6 66 %11:g8rc = LI8 7 67 68 bb.1: 69 %12:g8rc = ADDI8 %2, 1 70 %13:g8rc = LD 0, %2 :: (load 8) 71 %14:g8rc = LDX %2, %4 :: (load 8) 72 %16:g8rc = LDX %2, %8 :: (load 8) 73 %17:g8rc = LD 4, %2 :: (load 8) 74 %18:g8rc = LDX %2, %9 :: (load 8) 75 %19:g8rc = LDX %2, %10 :: (load 8) 76 %20:g8rc = LDX %2, %11 :: (load 8) 77 %21:g8rc = LD 8, %2 :: (load 8) 78 %22:g8rc = MULLD %14, %13 79 %15:g8rc = LDX %2, %7 :: (load 8) 80 %23:g8rc = MULLD %22, %15 81 %24:g8rc = MULLD %23, %16 82 %25:g8rc = MULLD %24, %17 83 %26:g8rc = MULLD %25, %18 84 %27:g8rc = MULLD %26, %19 85 %28:g8rc = MULLD %27, %20 86 %6:g8rc = MADDLD8 %28, %21, %6 87 %2:g8rc_and_g8rc_nox0 = COPY %12 88 BDNZ8 %bb.1, implicit-def dead $ctr8, implicit $ctr8 89 B %bb.2 90 91 bb.2: 92... 93