1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-P8 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s --check-prefix=CHECK-P9 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 9; RUN: -mcpu=pwr8 -mattr=-vsx -ppc-asm-full-reg-names \ 10; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-NOVSX 11; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 12; RUN: -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 13; RUN: FileCheck %s --check-prefix=CHECK-P7 14 15define dso_local <16 x i8> @testmrghb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 16; CHECK-P8-LABEL: testmrghb: 17; CHECK-P8: # %bb.0: # %entry 18; CHECK-P8-NEXT: vmrghb v2, v3, v2 19; CHECK-P8-NEXT: blr 20; 21; CHECK-P9-LABEL: testmrghb: 22; CHECK-P9: # %bb.0: # %entry 23; CHECK-P9-NEXT: vmrghb v2, v3, v2 24; CHECK-P9-NEXT: blr 25; 26; CHECK-NOVSX-LABEL: testmrghb: 27; CHECK-NOVSX: # %bb.0: # %entry 28; CHECK-NOVSX-NEXT: vmrghb v2, v3, v2 29; CHECK-NOVSX-NEXT: blr 30; 31; CHECK-P7-LABEL: testmrghb: 32; CHECK-P7: # %bb.0: # %entry 33; CHECK-P7-NEXT: vmrghb v2, v3, v2 34; CHECK-P7-NEXT: blr 35entry: 36 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> 37 ret <16 x i8> %shuffle 38} 39define dso_local <16 x i8> @testmrghb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 40; CHECK-P8-LABEL: testmrghb2: 41; CHECK-P8: # %bb.0: # %entry 42; CHECK-P8-NEXT: vmrghb v2, v2, v3 43; CHECK-P8-NEXT: blr 44; 45; CHECK-P9-LABEL: testmrghb2: 46; CHECK-P9: # %bb.0: # %entry 47; CHECK-P9-NEXT: vmrghb v2, v2, v3 48; CHECK-P9-NEXT: blr 49; 50; CHECK-NOVSX-LABEL: testmrghb2: 51; CHECK-NOVSX: # %bb.0: # %entry 52; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI1_0@toc@ha 53; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI1_0@toc@l 54; CHECK-NOVSX-NEXT: lvx v4, 0, r3 55; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 56; CHECK-NOVSX-NEXT: blr 57; 58; CHECK-P7-LABEL: testmrghb2: 59; CHECK-P7: # %bb.0: # %entry 60; CHECK-P7-NEXT: vmrghb v2, v2, v3 61; CHECK-P7-NEXT: blr 62entry: 63 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 8, i32 25, i32 9, i32 26, i32 10, i32 27, i32 11, i32 28, i32 12, i32 29, i32 13, i32 30, i32 14, i32 31, i32 15> 64 ret <16 x i8> %shuffle 65} 66define dso_local <16 x i8> @testmrghh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 67; CHECK-P8-LABEL: testmrghh: 68; CHECK-P8: # %bb.0: # %entry 69; CHECK-P8-NEXT: vmrghh v2, v3, v2 70; CHECK-P8-NEXT: blr 71; 72; CHECK-P9-LABEL: testmrghh: 73; CHECK-P9: # %bb.0: # %entry 74; CHECK-P9-NEXT: vmrghh v2, v3, v2 75; CHECK-P9-NEXT: blr 76; 77; CHECK-NOVSX-LABEL: testmrghh: 78; CHECK-NOVSX: # %bb.0: # %entry 79; CHECK-NOVSX-NEXT: vmrghh v2, v3, v2 80; CHECK-NOVSX-NEXT: blr 81; 82; CHECK-P7-LABEL: testmrghh: 83; CHECK-P7: # %bb.0: # %entry 84; CHECK-P7-NEXT: vmrghh v2, v3, v2 85; CHECK-P7-NEXT: blr 86entry: 87 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31> 88 ret <16 x i8> %shuffle 89} 90define dso_local <16 x i8> @testmrghh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 91; CHECK-P8-LABEL: testmrghh2: 92; CHECK-P8: # %bb.0: # %entry 93; CHECK-P8-NEXT: vmrghh v2, v2, v3 94; CHECK-P8-NEXT: blr 95; 96; CHECK-P9-LABEL: testmrghh2: 97; CHECK-P9: # %bb.0: # %entry 98; CHECK-P9-NEXT: vmrghh v2, v2, v3 99; CHECK-P9-NEXT: blr 100; 101; CHECK-NOVSX-LABEL: testmrghh2: 102; CHECK-NOVSX: # %bb.0: # %entry 103; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI3_0@toc@ha 104; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI3_0@toc@l 105; CHECK-NOVSX-NEXT: lvx v4, 0, r3 106; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 107; CHECK-NOVSX-NEXT: blr 108; 109; CHECK-P7-LABEL: testmrghh2: 110; CHECK-P7: # %bb.0: # %entry 111; CHECK-P7-NEXT: vmrghh v2, v2, v3 112; CHECK-P7-NEXT: blr 113entry: 114 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 8, i32 9, i32 26, i32 27, i32 10, i32 11, i32 28, i32 29, i32 12, i32 13, i32 30, i32 31, i32 14, i32 15> 115 ret <16 x i8> %shuffle 116} 117define dso_local <16 x i8> @testmrglb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 118; CHECK-P8-LABEL: testmrglb: 119; CHECK-P8: # %bb.0: # %entry 120; CHECK-P8-NEXT: vmrglb v2, v3, v2 121; CHECK-P8-NEXT: blr 122; 123; CHECK-P9-LABEL: testmrglb: 124; CHECK-P9: # %bb.0: # %entry 125; CHECK-P9-NEXT: vmrglb v2, v3, v2 126; CHECK-P9-NEXT: blr 127; 128; CHECK-NOVSX-LABEL: testmrglb: 129; CHECK-NOVSX: # %bb.0: # %entry 130; CHECK-NOVSX-NEXT: vmrglb v2, v3, v2 131; CHECK-NOVSX-NEXT: blr 132; 133; CHECK-P7-LABEL: testmrglb: 134; CHECK-P7: # %bb.0: # %entry 135; CHECK-P7-NEXT: vmrglb v2, v3, v2 136; CHECK-P7-NEXT: blr 137entry: 138 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> 139 ret <16 x i8> %shuffle 140} 141define dso_local <16 x i8> @testmrglb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 142; CHECK-P8-LABEL: testmrglb2: 143; CHECK-P8: # %bb.0: # %entry 144; CHECK-P8-NEXT: vmrglb v2, v2, v3 145; CHECK-P8-NEXT: blr 146; 147; CHECK-P9-LABEL: testmrglb2: 148; CHECK-P9: # %bb.0: # %entry 149; CHECK-P9-NEXT: vmrglb v2, v2, v3 150; CHECK-P9-NEXT: blr 151; 152; CHECK-NOVSX-LABEL: testmrglb2: 153; CHECK-NOVSX: # %bb.0: # %entry 154; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI5_0@toc@ha 155; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI5_0@toc@l 156; CHECK-NOVSX-NEXT: lvx v4, 0, r3 157; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 158; CHECK-NOVSX-NEXT: blr 159; 160; CHECK-P7-LABEL: testmrglb2: 161; CHECK-P7: # %bb.0: # %entry 162; CHECK-P7-NEXT: vmrglb v2, v2, v3 163; CHECK-P7-NEXT: blr 164entry: 165 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 0, i32 17, i32 1, i32 18, i32 2, i32 19, i32 3, i32 20, i32 4, i32 21, i32 5, i32 22, i32 6, i32 23, i32 7> 166 ret <16 x i8> %shuffle 167} 168define dso_local <16 x i8> @testmrglh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 169; CHECK-P8-LABEL: testmrglh: 170; CHECK-P8: # %bb.0: # %entry 171; CHECK-P8-NEXT: vmrglh v2, v3, v2 172; CHECK-P8-NEXT: blr 173; 174; CHECK-P9-LABEL: testmrglh: 175; CHECK-P9: # %bb.0: # %entry 176; CHECK-P9-NEXT: vmrglh v2, v3, v2 177; CHECK-P9-NEXT: blr 178; 179; CHECK-NOVSX-LABEL: testmrglh: 180; CHECK-NOVSX: # %bb.0: # %entry 181; CHECK-NOVSX-NEXT: vmrglh v2, v3, v2 182; CHECK-NOVSX-NEXT: blr 183; 184; CHECK-P7-LABEL: testmrglh: 185; CHECK-P7: # %bb.0: # %entry 186; CHECK-P7-NEXT: vmrglh v2, v3, v2 187; CHECK-P7-NEXT: blr 188entry: 189 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23> 190 ret <16 x i8> %shuffle 191} 192define dso_local <16 x i8> @testmrglh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 193; CHECK-P8-LABEL: testmrglh2: 194; CHECK-P8: # %bb.0: # %entry 195; CHECK-P8-NEXT: vmrglh v2, v2, v3 196; CHECK-P8-NEXT: blr 197; 198; CHECK-P9-LABEL: testmrglh2: 199; CHECK-P9: # %bb.0: # %entry 200; CHECK-P9-NEXT: vmrglh v2, v2, v3 201; CHECK-P9-NEXT: blr 202; 203; CHECK-NOVSX-LABEL: testmrglh2: 204; CHECK-NOVSX: # %bb.0: # %entry 205; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI7_0@toc@ha 206; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI7_0@toc@l 207; CHECK-NOVSX-NEXT: lvx v4, 0, r3 208; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 209; CHECK-NOVSX-NEXT: blr 210; 211; CHECK-P7-LABEL: testmrglh2: 212; CHECK-P7: # %bb.0: # %entry 213; CHECK-P7-NEXT: vmrglh v2, v2, v3 214; CHECK-P7-NEXT: blr 215entry: 216 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 0, i32 1, i32 18, i32 19, i32 2, i32 3, i32 20, i32 21, i32 4, i32 5, i32 22, i32 23, i32 6, i32 7> 217 ret <16 x i8> %shuffle 218} 219define dso_local <16 x i8> @testmrghw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 220; CHECK-P8-LABEL: testmrghw: 221; CHECK-P8: # %bb.0: # %entry 222; CHECK-P8-NEXT: vmrghw v2, v3, v2 223; CHECK-P8-NEXT: blr 224; 225; CHECK-P9-LABEL: testmrghw: 226; CHECK-P9: # %bb.0: # %entry 227; CHECK-P9-NEXT: vmrghw v2, v3, v2 228; CHECK-P9-NEXT: blr 229; 230; CHECK-NOVSX-LABEL: testmrghw: 231; CHECK-NOVSX: # %bb.0: # %entry 232; CHECK-NOVSX-NEXT: vmrghw v2, v3, v2 233; CHECK-NOVSX-NEXT: blr 234; 235; CHECK-P7-LABEL: testmrghw: 236; CHECK-P7: # %bb.0: # %entry 237; CHECK-P7-NEXT: vmrghw v2, v3, v2 238; CHECK-P7-NEXT: blr 239entry: 240 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31> 241 ret <16 x i8> %shuffle 242} 243define dso_local <16 x i8> @testmrghw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 244; CHECK-P8-LABEL: testmrghw2: 245; CHECK-P8: # %bb.0: # %entry 246; CHECK-P8-NEXT: vmrghw v2, v2, v3 247; CHECK-P8-NEXT: blr 248; 249; CHECK-P9-LABEL: testmrghw2: 250; CHECK-P9: # %bb.0: # %entry 251; CHECK-P9-NEXT: vmrghw v2, v2, v3 252; CHECK-P9-NEXT: blr 253; 254; CHECK-NOVSX-LABEL: testmrghw2: 255; CHECK-NOVSX: # %bb.0: # %entry 256; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI9_0@toc@ha 257; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI9_0@toc@l 258; CHECK-NOVSX-NEXT: lvx v4, 0, r3 259; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 260; CHECK-NOVSX-NEXT: blr 261; 262; CHECK-P7-LABEL: testmrghw2: 263; CHECK-P7: # %bb.0: # %entry 264; CHECK-P7-NEXT: vmrghw v2, v2, v3 265; CHECK-P7-NEXT: blr 266entry: 267 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31, i32 12, i32 13, i32 14, i32 15> 268 ret <16 x i8> %shuffle 269} 270define dso_local <16 x i8> @testmrglw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 271; CHECK-P8-LABEL: testmrglw: 272; CHECK-P8: # %bb.0: # %entry 273; CHECK-P8-NEXT: vmrglw v2, v3, v2 274; CHECK-P8-NEXT: blr 275; 276; CHECK-P9-LABEL: testmrglw: 277; CHECK-P9: # %bb.0: # %entry 278; CHECK-P9-NEXT: vmrglw v2, v3, v2 279; CHECK-P9-NEXT: blr 280; 281; CHECK-NOVSX-LABEL: testmrglw: 282; CHECK-NOVSX: # %bb.0: # %entry 283; CHECK-NOVSX-NEXT: vmrglw v2, v3, v2 284; CHECK-NOVSX-NEXT: blr 285; 286; CHECK-P7-LABEL: testmrglw: 287; CHECK-P7: # %bb.0: # %entry 288; CHECK-P7-NEXT: vmrglw v2, v3, v2 289; CHECK-P7-NEXT: blr 290entry: 291 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23> 292 ret <16 x i8> %shuffle 293} 294define dso_local <16 x i8> @testmrglw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { 295; CHECK-P8-LABEL: testmrglw2: 296; CHECK-P8: # %bb.0: # %entry 297; CHECK-P8-NEXT: vmrglw v2, v2, v3 298; CHECK-P8-NEXT: blr 299; 300; CHECK-P9-LABEL: testmrglw2: 301; CHECK-P9: # %bb.0: # %entry 302; CHECK-P9-NEXT: vmrglw v2, v2, v3 303; CHECK-P9-NEXT: blr 304; 305; CHECK-NOVSX-LABEL: testmrglw2: 306; CHECK-NOVSX: # %bb.0: # %entry 307; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI11_0@toc@ha 308; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI11_0@toc@l 309; CHECK-NOVSX-NEXT: lvx v4, 0, r3 310; CHECK-NOVSX-NEXT: vperm v2, v3, v2, v4 311; CHECK-NOVSX-NEXT: blr 312; 313; CHECK-P7-LABEL: testmrglw2: 314; CHECK-P7: # %bb.0: # %entry 315; CHECK-P7-NEXT: vmrglw v2, v2, v3 316; CHECK-P7-NEXT: blr 317entry: 318 %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 4, i32 5, i32 6, i32 7> 319 ret <16 x i8> %shuffle 320} 321 322define dso_local <8 x i16> @testmrglb3(<8 x i8>* nocapture readonly %a) local_unnamed_addr #0 { 323; CHECK-P8-LABEL: testmrglb3: 324; CHECK-P8: # %bb.0: # %entry 325; CHECK-P8-NEXT: lxsdx v2, 0, r3 326; CHECK-P8-NEXT: xxlxor v3, v3, v3 327; CHECK-P8-NEXT: vmrghb v2, v3, v2 328; CHECK-P8-NEXT: blr 329; 330; CHECK-P9-LABEL: testmrglb3: 331; CHECK-P9: # %bb.0: # %entry 332; CHECK-P9-NEXT: lxsd v2, 0(r3) 333; CHECK-P9-NEXT: xxlxor v3, v3, v3 334; CHECK-P9-NEXT: vmrghb v2, v3, v2 335; CHECK-P9-NEXT: blr 336; 337; CHECK-NOVSX-LABEL: testmrglb3: 338; CHECK-NOVSX: # %bb.0: # %entry 339; CHECK-NOVSX-NEXT: vxor v2, v2, v2 340; CHECK-NOVSX-NEXT: ld r3, 0(r3) 341; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI12_0@toc@ha 342; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI12_0@toc@l 343; CHECK-NOVSX-NEXT: lvx v3, 0, r4 344; CHECK-NOVSX-NEXT: std r3, -16(r1) 345; CHECK-NOVSX-NEXT: addi r3, r1, -16 346; CHECK-NOVSX-NEXT: lvx v4, 0, r3 347; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3 348; CHECK-NOVSX-NEXT: blr 349; 350; CHECK-P7-LABEL: testmrglb3: 351; CHECK-P7: # %bb.0: # %entry 352; CHECK-P7-NEXT: lxsdx v2, 0, r3 353; CHECK-P7-NEXT: xxlxor v3, v3, v3 354; CHECK-P7-NEXT: vmrghb v2, v3, v2 355; CHECK-P7-NEXT: blr 356entry: 357 %0 = load <8 x i8>, <8 x i8>* %a, align 8 358 %1 = zext <8 x i8> %0 to <8 x i16> 359 ret <8 x i16> %1 360} 361 362define dso_local void @no_crash_elt0_from_RHS(<2 x double>* noalias nocapture dereferenceable(16) %.vtx6) #0 { 363; CHECK-P8-LABEL: no_crash_elt0_from_RHS: 364; CHECK-P8: # %bb.0: # %test_entry 365; CHECK-P8-NEXT: mflr r0 366; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill 367; CHECK-P8-NEXT: std r0, 16(r1) 368; CHECK-P8-NEXT: stdu r1, -48(r1) 369; CHECK-P8-NEXT: mr r30, r3 370; CHECK-P8-NEXT: bl dummy 371; CHECK-P8-NEXT: nop 372; CHECK-P8-NEXT: xxlxor f0, f0, f0 373; CHECK-P8-NEXT: # kill: def $f1 killed $f1 def $vsl1 374; CHECK-P8-NEXT: xxmrghd vs0, vs1, vs0 375; CHECK-P8-NEXT: xxswapd vs0, vs0 376; CHECK-P8-NEXT: stxvd2x vs0, 0, r30 377; 378; CHECK-P9-LABEL: no_crash_elt0_from_RHS: 379; CHECK-P9: # %bb.0: # %test_entry 380; CHECK-P9-NEXT: mflr r0 381; CHECK-P9-NEXT: std r30, -16(r1) # 8-byte Folded Spill 382; CHECK-P9-NEXT: std r0, 16(r1) 383; CHECK-P9-NEXT: stdu r1, -48(r1) 384; CHECK-P9-NEXT: mr r30, r3 385; CHECK-P9-NEXT: bl dummy 386; CHECK-P9-NEXT: nop 387; CHECK-P9-NEXT: xxlxor f0, f0, f0 388; CHECK-P9-NEXT: # kill: def $f1 killed $f1 def $vsl1 389; CHECK-P9-NEXT: xxmrghd vs0, vs1, vs0 390; CHECK-P9-NEXT: stxv vs0, 0(r30) 391; 392; CHECK-NOVSX-LABEL: no_crash_elt0_from_RHS: 393; CHECK-NOVSX: # %bb.0: # %test_entry 394; CHECK-NOVSX-NEXT: mflr r0 395; CHECK-NOVSX-NEXT: std r30, -16(r1) # 8-byte Folded Spill 396; CHECK-NOVSX-NEXT: std r0, 16(r1) 397; CHECK-NOVSX-NEXT: stdu r1, -48(r1) 398; CHECK-NOVSX-NEXT: mr r30, r3 399; CHECK-NOVSX-NEXT: bl dummy 400; CHECK-NOVSX-NEXT: nop 401; CHECK-NOVSX-NEXT: li r3, 0 402; CHECK-NOVSX-NEXT: stfd f1, 8(r30) 403; CHECK-NOVSX-NEXT: std r3, 0(r30) 404; 405; CHECK-P7-LABEL: no_crash_elt0_from_RHS: 406; CHECK-P7: # %bb.0: # %test_entry 407; CHECK-P7-NEXT: mflr r0 408; CHECK-P7-NEXT: std r30, -16(r1) # 8-byte Folded Spill 409; CHECK-P7-NEXT: std r0, 16(r1) 410; CHECK-P7-NEXT: stdu r1, -48(r1) 411; CHECK-P7-NEXT: mr r30, r3 412; CHECK-P7-NEXT: bl dummy 413; CHECK-P7-NEXT: nop 414; CHECK-P7-NEXT: xxlxor f0, f0, f0 415; CHECK-P7-NEXT: # kill: def $f1 killed $f1 def $vsl1 416; CHECK-P7-NEXT: xxmrghd vs0, vs1, vs0 417; CHECK-P7-NEXT: xxswapd vs0, vs0 418; CHECK-P7-NEXT: stxvd2x vs0, 0, r30 419test_entry: 420 %_div_result = tail call double @dummy() 421 %oldret = insertvalue { double, double } undef, double %_div_result, 0 422 %0 = extractvalue { double, double } %oldret, 0 423 %.splatinsert = insertelement <2 x double> undef, double %0, i32 0 424 %.splat = shufflevector <2 x double> %.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer 425 %1 = shufflevector <2 x double> zeroinitializer, <2 x double> %.splat, <2 x i32> <i32 0, i32 3> 426 store <2 x double> %1, <2 x double>* %.vtx6, align 16 427 unreachable 428} 429 430define dso_local <16 x i8> @no_crash_bitcast(i32 %a) { 431; CHECK-P8-LABEL: no_crash_bitcast: 432; CHECK-P8: # %bb.0: # %entry 433; CHECK-P8-NEXT: mtvsrwz v2, r3 434; CHECK-P8-NEXT: blr 435; 436; CHECK-P9-LABEL: no_crash_bitcast: 437; CHECK-P9: # %bb.0: # %entry 438; CHECK-P9-NEXT: mtvsrws v2, r3 439; CHECK-P9-NEXT: blr 440; 441; CHECK-NOVSX-LABEL: no_crash_bitcast: 442; CHECK-NOVSX: # %bb.0: # %entry 443; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI14_0@toc@ha 444; CHECK-NOVSX-NEXT: stw r3, -16(r1) 445; CHECK-NOVSX-NEXT: addi r3, r1, -16 446; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI14_0@toc@l 447; CHECK-NOVSX-NEXT: lvx v3, 0, r3 448; CHECK-NOVSX-NEXT: lvx v2, 0, r4 449; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2 450; CHECK-NOVSX-NEXT: blr 451; 452; CHECK-P7-LABEL: no_crash_bitcast: 453; CHECK-P7: # %bb.0: # %entry 454; CHECK-P7-NEXT: addis r4, r2, .LCPI14_0@toc@ha 455; CHECK-P7-NEXT: stw r3, -16(r1) 456; CHECK-P7-NEXT: addi r3, r1, -16 457; CHECK-P7-NEXT: addi r4, r4, .LCPI14_0@toc@l 458; CHECK-P7-NEXT: lvx v3, 0, r3 459; CHECK-P7-NEXT: lvx v2, 0, r4 460; CHECK-P7-NEXT: vperm v2, v3, v3, v2 461; CHECK-P7-NEXT: blr 462entry: 463 %cast = bitcast i32 %a to <4 x i8> 464 %ret = shufflevector <4 x i8> %cast, <4 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> 465 ret <16 x i8> %ret 466} 467 468define dso_local <4 x i32> @replace_undefs_in_splat(<4 x i32> %a) local_unnamed_addr #0 { 469; CHECK-P8-LABEL: replace_undefs_in_splat: 470; CHECK-P8: # %bb.0: # %entry 471; CHECK-P8-NEXT: addis r3, r2, .LCPI15_0@toc@ha 472; CHECK-P8-NEXT: addi r3, r3, .LCPI15_0@toc@l 473; CHECK-P8-NEXT: lvx v3, 0, r3 474; CHECK-P8-NEXT: vmrgow v2, v3, v2 475; CHECK-P8-NEXT: blr 476; 477; CHECK-P9-LABEL: replace_undefs_in_splat: 478; CHECK-P9: # %bb.0: # %entry 479; CHECK-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha 480; CHECK-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l 481; CHECK-P9-NEXT: lxvx v3, 0, r3 482; CHECK-P9-NEXT: vmrgow v2, v3, v2 483; CHECK-P9-NEXT: blr 484; 485; CHECK-NOVSX-LABEL: replace_undefs_in_splat: 486; CHECK-NOVSX: # %bb.0: # %entry 487; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI15_0@toc@ha 488; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI15_1@toc@ha 489; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI15_0@toc@l 490; CHECK-NOVSX-NEXT: lvx v3, 0, r3 491; CHECK-NOVSX-NEXT: addi r3, r4, .LCPI15_1@toc@l 492; CHECK-NOVSX-NEXT: lvx v4, 0, r3 493; CHECK-NOVSX-NEXT: vperm v2, v4, v2, v3 494; CHECK-NOVSX-NEXT: blr 495; 496; CHECK-P7-LABEL: replace_undefs_in_splat: 497; CHECK-P7: # %bb.0: # %entry 498; CHECK-P7-NEXT: addis r3, r2, .LCPI15_0@toc@ha 499; CHECK-P7-NEXT: addis r4, r2, .LCPI15_1@toc@ha 500; CHECK-P7-NEXT: addi r3, r3, .LCPI15_0@toc@l 501; CHECK-P7-NEXT: lvx v3, 0, r3 502; CHECK-P7-NEXT: addi r3, r4, .LCPI15_1@toc@l 503; CHECK-P7-NEXT: lvx v4, 0, r3 504; CHECK-P7-NEXT: vperm v2, v4, v2, v3 505; CHECK-P7-NEXT: blr 506entry: 507 %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7> 508 ret <4 x i32> %vecins1 509} 510 511define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 { 512; CHECK-P8-LABEL: no_RAUW_in_combine_during_legalize: 513; CHECK-P8: # %bb.0: # %entry 514; CHECK-P8-NEXT: addis r5, r2, .LCPI16_0@toc@ha 515; CHECK-P8-NEXT: sldi r4, r4, 2 516; CHECK-P8-NEXT: xxlxor v4, v4, v4 517; CHECK-P8-NEXT: addi r5, r5, .LCPI16_0@toc@l 518; CHECK-P8-NEXT: lxsiwzx v2, r3, r4 519; CHECK-P8-NEXT: lvx v3, 0, r5 520; CHECK-P8-NEXT: vperm v2, v4, v2, v3 521; CHECK-P8-NEXT: blr 522; 523; CHECK-P9-LABEL: no_RAUW_in_combine_during_legalize: 524; CHECK-P9: # %bb.0: # %entry 525; CHECK-P9-NEXT: sldi r4, r4, 2 526; CHECK-P9-NEXT: xxlxor v4, v4, v4 527; CHECK-P9-NEXT: lxsiwzx v2, r3, r4 528; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha 529; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l 530; CHECK-P9-NEXT: lxvx v3, 0, r3 531; CHECK-P9-NEXT: vperm v2, v4, v2, v3 532; CHECK-P9-NEXT: blr 533; 534; CHECK-NOVSX-LABEL: no_RAUW_in_combine_during_legalize: 535; CHECK-NOVSX: # %bb.0: # %entry 536; CHECK-NOVSX-NEXT: sldi r4, r4, 2 537; CHECK-NOVSX-NEXT: vxor v2, v2, v2 538; CHECK-NOVSX-NEXT: lwzx r3, r3, r4 539; CHECK-NOVSX-NEXT: std r3, -16(r1) 540; CHECK-NOVSX-NEXT: addi r3, r1, -16 541; CHECK-NOVSX-NEXT: lvx v3, 0, r3 542; CHECK-NOVSX-NEXT: vmrglb v2, v2, v3 543; CHECK-NOVSX-NEXT: blr 544; 545; CHECK-P7-LABEL: no_RAUW_in_combine_during_legalize: 546; CHECK-P7: # %bb.0: # %entry 547; CHECK-P7-NEXT: sldi r4, r4, 2 548; CHECK-P7-NEXT: addi r5, r1, -16 549; CHECK-P7-NEXT: xxlxor v3, v3, v3 550; CHECK-P7-NEXT: lwzx r3, r3, r4 551; CHECK-P7-NEXT: std r3, -16(r1) 552; CHECK-P7-NEXT: lxvd2x vs0, 0, r5 553; CHECK-P7-NEXT: xxswapd v2, vs0 554; CHECK-P7-NEXT: vmrglb v2, v3, v2 555; CHECK-P7-NEXT: blr 556entry: 557 %idx.ext = sext i32 %offset to i64 558 %add.ptr = getelementptr inbounds i32, i32* %ptr, i64 %idx.ext 559 %0 = load i32, i32* %add.ptr, align 4 560 %conv = zext i32 %0 to i64 561 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 562 %1 = bitcast <2 x i64> %splat.splatinsert to <16 x i8> 563 %shuffle = shufflevector <16 x i8> %1, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> 564 ret <16 x i8> %shuffle 565} 566 567define dso_local <4 x i32> @testSplat4Low(<8 x i8>* nocapture readonly %ptr) local_unnamed_addr #0 { 568; CHECK-P8-LABEL: testSplat4Low: 569; CHECK-P8: # %bb.0: # %entry 570; CHECK-P8-NEXT: lfdx f0, 0, r3 571; CHECK-P8-NEXT: xxspltw v2, vs0, 0 572; CHECK-P8-NEXT: blr 573; 574; CHECK-P9-LABEL: testSplat4Low: 575; CHECK-P9: # %bb.0: # %entry 576; CHECK-P9-NEXT: addi r3, r3, 4 577; CHECK-P9-NEXT: lxvwsx v2, 0, r3 578; CHECK-P9-NEXT: blr 579; 580; CHECK-NOVSX-LABEL: testSplat4Low: 581; CHECK-NOVSX: # %bb.0: # %entry 582; CHECK-NOVSX-NEXT: ld r3, 0(r3) 583; CHECK-NOVSX-NEXT: addi r4, r1, -16 584; CHECK-NOVSX-NEXT: std r3, -16(r1) 585; CHECK-NOVSX-NEXT: lvx v2, 0, r4 586; CHECK-NOVSX-NEXT: vspltw v2, v2, 2 587; CHECK-NOVSX-NEXT: blr 588; 589; CHECK-P7-LABEL: testSplat4Low: 590; CHECK-P7: # %bb.0: # %entry 591; CHECK-P7-NEXT: lfdx f0, 0, r3 592; CHECK-P7-NEXT: xxspltw v2, vs0, 0 593; CHECK-P7-NEXT: blr 594entry: 595 %0 = load <8 x i8>, <8 x i8>* %ptr, align 8 596 %vecinit18 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 597 %1 = bitcast <16 x i8> %vecinit18 to <4 x i32> 598 ret <4 x i32> %1 599} 600 601; Function Attrs: norecurse nounwind readonly 602define dso_local <4 x i32> @testSplat4hi(<8 x i8>* nocapture readonly %ptr) local_unnamed_addr #0 { 603; CHECK-P8-LABEL: testSplat4hi: 604; CHECK-P8: # %bb.0: # %entry 605; CHECK-P8-NEXT: lfdx f0, 0, r3 606; CHECK-P8-NEXT: xxspltw v2, vs0, 1 607; CHECK-P8-NEXT: blr 608; 609; CHECK-P9-LABEL: testSplat4hi: 610; CHECK-P9: # %bb.0: # %entry 611; CHECK-P9-NEXT: lxvwsx v2, 0, r3 612; CHECK-P9-NEXT: blr 613; 614; CHECK-NOVSX-LABEL: testSplat4hi: 615; CHECK-NOVSX: # %bb.0: # %entry 616; CHECK-NOVSX-NEXT: ld r3, 0(r3) 617; CHECK-NOVSX-NEXT: addi r4, r1, -16 618; CHECK-NOVSX-NEXT: std r3, -16(r1) 619; CHECK-NOVSX-NEXT: lvx v2, 0, r4 620; CHECK-NOVSX-NEXT: vspltw v2, v2, 3 621; CHECK-NOVSX-NEXT: blr 622; 623; CHECK-P7-LABEL: testSplat4hi: 624; CHECK-P7: # %bb.0: # %entry 625; CHECK-P7-NEXT: lfdx f0, 0, r3 626; CHECK-P7-NEXT: xxspltw v2, vs0, 1 627; CHECK-P7-NEXT: blr 628entry: 629 %0 = load <8 x i8>, <8 x i8>* %ptr, align 8 630 %vecinit22 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 631 %1 = bitcast <16 x i8> %vecinit22 to <4 x i32> 632 ret <4 x i32> %1 633} 634 635; Function Attrs: norecurse nounwind readonly 636define dso_local <2 x i64> @testSplat8(<8 x i8>* nocapture readonly %ptr) local_unnamed_addr #0 { 637; CHECK-P8-LABEL: testSplat8: 638; CHECK-P8: # %bb.0: # %entry 639; CHECK-P8-NEXT: lxvdsx v2, 0, r3 640; CHECK-P8-NEXT: blr 641; 642; CHECK-P9-LABEL: testSplat8: 643; CHECK-P9: # %bb.0: # %entry 644; CHECK-P9-NEXT: lxvdsx v2, 0, r3 645; CHECK-P9-NEXT: blr 646; 647; CHECK-NOVSX-LABEL: testSplat8: 648; CHECK-NOVSX: # %bb.0: # %entry 649; CHECK-NOVSX-NEXT: ld r3, 0(r3) 650; CHECK-NOVSX-NEXT: addis r4, r2, .LCPI19_0@toc@ha 651; CHECK-NOVSX-NEXT: addi r4, r4, .LCPI19_0@toc@l 652; CHECK-NOVSX-NEXT: lvx v2, 0, r4 653; CHECK-NOVSX-NEXT: std r3, -16(r1) 654; CHECK-NOVSX-NEXT: addi r3, r1, -16 655; CHECK-NOVSX-NEXT: lvx v3, 0, r3 656; CHECK-NOVSX-NEXT: vperm v2, v3, v3, v2 657; CHECK-NOVSX-NEXT: blr 658; 659; CHECK-P7-LABEL: testSplat8: 660; CHECK-P7: # %bb.0: # %entry 661; CHECK-P7-NEXT: lxvdsx v2, 0, r3 662; CHECK-P7-NEXT: blr 663entry: 664 %0 = load <8 x i8>, <8 x i8>* %ptr, align 8 665 %vecinit30 = shufflevector <8 x i8> %0, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 666 %1 = bitcast <16 x i8> %vecinit30 to <2 x i64> 667 ret <2 x i64> %1 668} 669 670declare double @dummy() local_unnamed_addr 671attributes #0 = { nounwind } 672