1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
3; RUN:  -ppc-asm-full-reg-names < %s  | FileCheck %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
5; RUN:  -ppc-asm-full-reg-names < %s  | FileCheck %s
6
7define zeroext i1 @eq1(i1 zeroext %x, i1 zeroext %y) {
8; CHECK-LABEL: eq1:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    add r3, r4, r3
11; CHECK-NEXT:    cntlzw r3, r3
12; CHECK-NEXT:    srwi r3, r3, 5
13; CHECK-NEXT:    blr
14  %sub = sext i1 %x to i32
15  %conv3 = zext i1 %y to i32
16  %cmp = icmp eq i32 %sub, %conv3
17  ret i1 %cmp
18}
19
20define zeroext i8 @eq2(i8 zeroext %x, i8 zeroext %y) {
21; CHECK-LABEL: eq2:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    add r3, r4, r3
24; CHECK-NEXT:    cntlzw r3, r3
25; CHECK-NEXT:    srwi r3, r3, 5
26; CHECK-NEXT:    blr
27  %conv = zext i8 %x to i32
28  %sub = sub nsw i32 0, %conv
29  %conv1 = zext i8 %y to i32
30  %cmp = icmp eq i32 %sub, %conv1
31  %conv3 = zext i1 %cmp to i8
32  ret i8 %conv3
33}
34
35define signext i16 @eq3(i16 signext %x, i16 signext %y) {
36; CHECK-LABEL: eq3:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    add r3, r4, r3
39; CHECK-NEXT:    cntlzw r3, r3
40; CHECK-NEXT:    srwi r3, r3, 5
41; CHECK-NEXT:    blr
42  %conv = sext i16 %x to i32
43  %sub = sub nsw i32 0, %conv
44  %conv1 = sext i16 %y to i32
45  %cmp = icmp eq i32 %sub, %conv1
46  %conv3 = zext i1 %cmp to i16
47  ret i16 %conv3
48}
49
50define zeroext i16 @eq4(i16 zeroext %x, i16 zeroext %y) {
51; CHECK-LABEL: eq4:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    add r3, r4, r3
54; CHECK-NEXT:    cntlzw r3, r3
55; CHECK-NEXT:    srwi r3, r3, 5
56; CHECK-NEXT:    blr
57  %conv = zext i16 %x to i32
58  %sub = sub nsw i32 0, %conv
59  %conv1 = zext i16 %y to i32
60  %cmp = icmp eq i32 %sub, %conv1
61  %conv3 = zext i1 %cmp to i16
62  ret i16 %conv3
63}
64
65define signext i32 @eq5(i32 signext %x, i32 signext %y) {
66; CHECK-LABEL: eq5:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    add r3, r4, r3
69; CHECK-NEXT:    cntlzw r3, r3
70; CHECK-NEXT:    srwi r3, r3, 5
71; CHECK-NEXT:    blr
72  %sub = sub nsw i32 0, %x
73  %cmp = icmp eq i32 %sub, %y
74  %conv = zext i1 %cmp to i32
75  ret i32 %conv
76}
77
78define zeroext i32 @eq6(i32 zeroext %x, i32 zeroext %y) {
79; CHECK-LABEL: eq6:
80; CHECK:       # %bb.0:
81; CHECK-NEXT:    add r3, r4, r3
82; CHECK-NEXT:    cntlzw r3, r3
83; CHECK-NEXT:    srwi r3, r3, 5
84; CHECK-NEXT:    blr
85  %sub = sub i32 0, %x
86  %cmp = icmp eq i32 %sub, %y
87  %conv = zext i1 %cmp to i32
88  ret i32 %conv
89}
90
91define i64 @eq7(i64 %x, i64 %y) {
92; CHECK-LABEL: eq7:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    add r3, r4, r3
95; CHECK-NEXT:    cntlzd r3, r3
96; CHECK-NEXT:    rldicl r3, r3, 58, 63
97; CHECK-NEXT:    blr
98  %sub = sub nsw i64 0, %x
99  %cmp = icmp eq i64 %sub, %y
100  %zext = zext i1 %cmp to i64
101  ret i64 %zext
102}
103
104define zeroext i1 @eq8(i1 zeroext %x, i1 zeroext %y) {
105; CHECK-LABEL: eq8:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    add r3, r4, r3
108; CHECK-NEXT:    cntlzw r3, r3
109; CHECK-NEXT:    srwi r3, r3, 5
110; CHECK-NEXT:    blr
111  %conv = zext i1 %y to i32
112  %sub = sext i1 %x to i32
113  %cmp = icmp eq i32 %conv, %sub
114  ret i1 %cmp
115}
116
117define zeroext i8 @eq9(i8 zeroext %x, i8 zeroext %y) {
118; CHECK-LABEL: eq9:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    add r3, r3, r4
121; CHECK-NEXT:    cntlzw r3, r3
122; CHECK-NEXT:    srwi r3, r3, 5
123; CHECK-NEXT:    blr
124  %conv = zext i8 %x to i32
125  %conv1 = zext i8 %y to i32
126  %sub = sub nsw i32 0, %conv1
127  %cmp = icmp eq i32 %conv, %sub
128  %conv3 = zext i1 %cmp to i8
129  ret i8 %conv3
130}
131
132define signext i16 @eq10(i16 signext %x, i16 signext %y) {
133; CHECK-LABEL: eq10:
134; CHECK:       # %bb.0:
135; CHECK-NEXT:    add r3, r3, r4
136; CHECK-NEXT:    cntlzw r3, r3
137; CHECK-NEXT:    srwi r3, r3, 5
138; CHECK-NEXT:    blr
139  %conv = sext i16 %x to i32
140  %conv1 = sext i16 %y to i32
141  %sub = sub nsw i32 0, %conv1
142  %cmp = icmp eq i32 %conv, %sub
143  %conv3 = zext i1 %cmp to i16
144  ret i16 %conv3
145}
146
147define zeroext i16 @eq11(i16 zeroext %x, i16 zeroext %y) {
148; CHECK-LABEL: eq11:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    add r3, r3, r4
151; CHECK-NEXT:    cntlzw r3, r3
152; CHECK-NEXT:    srwi r3, r3, 5
153; CHECK-NEXT:    blr
154  %conv = zext i16 %x to i32
155  %conv1 = zext i16 %y to i32
156  %sub = sub nsw i32 0, %conv1
157  %cmp = icmp eq i32 %conv, %sub
158  %conv3 = zext i1 %cmp to i16
159  ret i16 %conv3
160}
161
162define signext i32 @eq12(i32 signext %x, i32 signext %y) {
163; CHECK-LABEL: eq12:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    add r3, r3, r4
166; CHECK-NEXT:    cntlzw r3, r3
167; CHECK-NEXT:    srwi r3, r3, 5
168; CHECK-NEXT:    blr
169  %sub = sub nsw i32 0, %y
170  %cmp = icmp eq i32 %sub, %x
171  %conv = zext i1 %cmp to i32
172  ret i32 %conv
173}
174
175define zeroext i32 @eq13(i32 zeroext %x, i32 zeroext %y) {
176; CHECK-LABEL: eq13:
177; CHECK:       # %bb.0:
178; CHECK-NEXT:    add r3, r3, r4
179; CHECK-NEXT:    cntlzw r3, r3
180; CHECK-NEXT:    srwi r3, r3, 5
181; CHECK-NEXT:    blr
182  %sub = sub i32 0, %y
183  %cmp = icmp eq i32 %sub, %x
184  %conv = zext i1 %cmp to i32
185  ret i32 %conv
186}
187
188define i64 @eq14(i64 %x, i64 %y) {
189; CHECK-LABEL: eq14:
190; CHECK:       # %bb.0:
191; CHECK-NEXT:    add r3, r3, r4
192; CHECK-NEXT:    cntlzd r3, r3
193; CHECK-NEXT:    rldicl r3, r3, 58, 63
194; CHECK-NEXT:    blr
195  %sub = sub nsw i64 0, %y
196  %cmp = icmp eq i64 %sub, %x
197  %conv1 = zext i1 %cmp to i64
198  ret i64 %conv1
199}
200
201define zeroext i1 @neq1(i1 zeroext %x, i1 zeroext %y) {
202; CHECK-LABEL: neq1:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    add r3, r4, r3
205; CHECK-NEXT:    cntlzw r3, r3
206; CHECK-NEXT:    srwi r3, r3, 5
207; CHECK-NEXT:    xori r3, r3, 1
208; CHECK-NEXT:    blr
209  %sub = sext i1 %x to i32
210  %conv3 = zext i1 %y to i32
211  %cmp = icmp ne i32 %sub, %conv3
212  ret i1 %cmp
213}
214
215define zeroext i8 @neq2(i8 zeroext %x, i8 zeroext %y) {
216; CHECK-LABEL: neq2:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    add r3, r4, r3
219; CHECK-NEXT:    cntlzw r3, r3
220; CHECK-NEXT:    srwi r3, r3, 5
221; CHECK-NEXT:    xori r3, r3, 1
222; CHECK-NEXT:    blr
223  %conv = zext i8 %x to i32
224  %sub = sub nsw i32 0, %conv
225  %conv1 = zext i8 %y to i32
226  %cmp = icmp ne i32 %sub, %conv1
227  %conv3 = zext i1 %cmp to i8
228  ret i8 %conv3
229}
230
231define signext i16 @neq3(i16 signext %x, i16 signext %y) {
232; CHECK-LABEL: neq3:
233; CHECK:       # %bb.0:
234; CHECK-NEXT:    add r3, r4, r3
235; CHECK-NEXT:    cntlzw r3, r3
236; CHECK-NEXT:    srwi r3, r3, 5
237; CHECK-NEXT:    xori r3, r3, 1
238; CHECK-NEXT:    blr
239  %conv = sext i16 %x to i32
240  %sub = sub nsw i32 0, %conv
241  %conv1 = sext i16 %y to i32
242  %cmp = icmp ne i32 %sub, %conv1
243  %conv3 = zext i1 %cmp to i16
244  ret i16 %conv3
245}
246
247define zeroext i16 @neq4(i16 zeroext %x, i16 zeroext %y) {
248; CHECK-LABEL: neq4:
249; CHECK:       # %bb.0:
250; CHECK-NEXT:    add r3, r4, r3
251; CHECK-NEXT:    cntlzw r3, r3
252; CHECK-NEXT:    srwi r3, r3, 5
253; CHECK-NEXT:    xori r3, r3, 1
254; CHECK-NEXT:    blr
255  %conv = zext i16 %x to i32
256  %sub = sub nsw i32 0, %conv
257  %conv1 = zext i16 %y to i32
258  %cmp = icmp ne i32 %sub, %conv1
259  %conv3 = zext i1 %cmp to i16
260  ret i16 %conv3
261}
262
263define signext i32 @neq5(i32 signext %x, i32 signext %y) {
264; CHECK-LABEL: neq5:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    add r3, r4, r3
267; CHECK-NEXT:    cntlzw r3, r3
268; CHECK-NEXT:    srwi r3, r3, 5
269; CHECK-NEXT:    xori r3, r3, 1
270; CHECK-NEXT:    blr
271  %sub = sub nsw i32 0, %x
272  %cmp = icmp ne i32 %sub, %y
273  %conv = zext i1 %cmp to i32
274  ret i32 %conv
275}
276
277define zeroext i32 @neq6(i32 zeroext %x, i32 zeroext %y) {
278; CHECK-LABEL: neq6:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    add r3, r4, r3
281; CHECK-NEXT:    cntlzw r3, r3
282; CHECK-NEXT:    srwi r3, r3, 5
283; CHECK-NEXT:    xori r3, r3, 1
284; CHECK-NEXT:    blr
285  %sub = sub i32 0, %x
286  %cmp = icmp ne i32 %sub, %y
287  %conv = zext i1 %cmp to i32
288  ret i32 %conv
289}
290
291define i64 @neq7(i64 %x, i64 %y) {
292; CHECK-LABEL: neq7:
293; CHECK:       # %bb.0:
294; CHECK-NEXT:    add r3, r4, r3
295; CHECK-NEXT:    addic r4, r3, -1
296; CHECK-NEXT:    subfe r3, r4, r3
297; CHECK-NEXT:    blr
298  %sub = sub nsw i64 0, %x
299  %cmp = icmp ne i64 %sub, %y
300  %zext = zext i1 %cmp to i64
301  ret i64 %zext
302}
303
304define zeroext i1 @neq8(i1 zeroext %x, i1 zeroext %y) {
305; CHECK-LABEL: neq8:
306; CHECK:       # %bb.0:
307; CHECK-NEXT:    add r3, r4, r3
308; CHECK-NEXT:    cntlzw r3, r3
309; CHECK-NEXT:    srwi r3, r3, 5
310; CHECK-NEXT:    xori r3, r3, 1
311; CHECK-NEXT:    blr
312  %conv = zext i1 %y to i32
313  %sub = sext i1 %x to i32
314  %cmp = icmp ne i32 %conv, %sub
315  ret i1 %cmp
316}
317
318define zeroext i8 @neq9(i8 zeroext %x, i8 zeroext %y) {
319; CHECK-LABEL: neq9:
320; CHECK:       # %bb.0:
321; CHECK-NEXT:    add r3, r4, r3
322; CHECK-NEXT:    cntlzw r3, r3
323; CHECK-NEXT:    srwi r3, r3, 5
324; CHECK-NEXT:    xori r3, r3, 1
325; CHECK-NEXT:    blr
326  %conv = zext i8 %y to i32
327  %conv1 = zext i8 %x to i32
328  %sub = sub nsw i32 0, %conv1
329  %cmp = icmp ne i32 %conv, %sub
330  %conv3 = zext i1 %cmp to i8
331  ret i8 %conv3
332}
333
334define signext i16 @neq10(i16 signext %x, i16 signext %y) {
335; CHECK-LABEL: neq10:
336; CHECK:       # %bb.0:
337; CHECK-NEXT:    add r3, r4, r3
338; CHECK-NEXT:    cntlzw r3, r3
339; CHECK-NEXT:    srwi r3, r3, 5
340; CHECK-NEXT:    xori r3, r3, 1
341; CHECK-NEXT:    blr
342  %conv = sext i16 %y to i32
343  %conv1 = sext i16 %x to i32
344  %sub = sub nsw i32 0, %conv1
345  %cmp = icmp ne i32 %conv, %sub
346  %conv3 = zext i1 %cmp to i16
347  ret i16 %conv3
348}
349
350define zeroext i16 @neq11(i16 zeroext %x, i16 zeroext %y) {
351; CHECK-LABEL: neq11:
352; CHECK:       # %bb.0: # %entry
353; CHECK-NEXT:    add r3, r4, r3
354; CHECK-NEXT:    cntlzw r3, r3
355; CHECK-NEXT:    srwi r3, r3, 5
356; CHECK-NEXT:    xori r3, r3, 1
357; CHECK-NEXT:    blr
358entry:
359  %conv = zext i16 %y to i32
360  %conv1 = zext i16 %x to i32
361  %sub = sub nsw i32 0, %conv1
362  %cmp = icmp ne i32 %conv, %sub
363  %conv3 = zext i1 %cmp to i16
364  ret i16 %conv3
365}
366
367define signext i32 @neq12(i32 signext %x, i32 signext %y) {
368; CHECK-LABEL: neq12:
369; CHECK:       # %bb.0: # %entry
370; CHECK-NEXT:    add r3, r4, r3
371; CHECK-NEXT:    cntlzw r3, r3
372; CHECK-NEXT:    srwi r3, r3, 5
373; CHECK-NEXT:    xori r3, r3, 1
374; CHECK-NEXT:    blr
375entry:
376  %sub = sub nsw i32 0, %x
377  %cmp = icmp ne i32 %sub, %y
378  %conv = zext i1 %cmp to i32
379  ret i32 %conv
380}
381
382define zeroext i32 @neq13(i32 zeroext %x, i32 zeroext %y) {
383; CHECK-LABEL: neq13:
384; CHECK:       # %bb.0: # %entry
385; CHECK-NEXT:    add r3, r4, r3
386; CHECK-NEXT:    cntlzw r3, r3
387; CHECK-NEXT:    srwi r3, r3, 5
388; CHECK-NEXT:    xori r3, r3, 1
389; CHECK-NEXT:    blr
390entry:
391  %sub = sub i32 0, %x
392  %cmp = icmp ne i32 %sub, %y
393  %conv = zext i1 %cmp to i32
394  ret i32 %conv
395}
396
397define i64 @neq14(i64 %x, i64 %y) {
398; CHECK-LABEL: neq14:
399; CHECK:       # %bb.0:
400; CHECK-NEXT:    add r3, r4, r3
401; CHECK-NEXT:    addic r4, r3, -1
402; CHECK-NEXT:    subfe r3, r4, r3
403; CHECK-NEXT:    blr
404  %sub = sub nsw i64 0, %x
405  %cmp = icmp ne i64 %y, %sub
406  %zext = zext i1 %cmp to i64
407  ret i64 %zext
408}
409