1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN:   FileCheck %s
5
6; This test case aims to test vector sign extend builtins.
7
8declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>) nounwind readnone
9declare <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8>) nounwind readnone
10declare <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16>) nounwind readnone
11declare <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16>) nounwind readnone
12declare <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32>) nounwind readnone
13
14define <4 x i32> @test_vextsb2w(<16 x i8> %x) nounwind readnone {
15; CHECK-LABEL: test_vextsb2w:
16; CHECK:       # %bb.0:
17; CHECK-NEXT:    vextsb2w v2, v2
18; CHECK-NEXT:    blr
19  %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> %x)
20  ret <4 x i32> %tmp
21}
22
23define <2 x i64> @test_vextsb2d(<16 x i8> %x) nounwind readnone {
24; CHECK-LABEL: test_vextsb2d:
25; CHECK:       # %bb.0:
26; CHECK-NEXT:    vextsb2d v2, v2
27; CHECK-NEXT:    blr
28  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8> %x)
29  ret <2 x i64> %tmp
30}
31
32define <4 x i32> @test_vextsh2w(<8 x i16> %x) nounwind readnone {
33; CHECK-LABEL: test_vextsh2w:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    vextsh2w v2, v2
36; CHECK-NEXT:    blr
37  %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16> %x)
38  ret <4 x i32> %tmp
39}
40
41define <2 x i64> @test_vextsh2d(<8 x i16> %x) nounwind readnone {
42; CHECK-LABEL: test_vextsh2d:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vextsh2d v2, v2
45; CHECK-NEXT:    blr
46  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16> %x)
47  ret <2 x i64> %tmp
48}
49
50define <2 x i64> @test_vextsw2d(<4 x i32> %x) nounwind readnone {
51; CHECK-LABEL: test_vextsw2d:
52; CHECK:       # %bb.0:
53; CHECK-NEXT:    vextsw2d v2, v2
54; CHECK-NEXT:    blr
55  %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32> %x)
56  ret <2 x i64> %tmp
57}
58