1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: split-file %s %t
3; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
4; RUN:          -mattr=+spe |  FileCheck %t/single.ll
5; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
6; RUN:          -mattr=+spe |  FileCheck %t/double.ll -check-prefix=SPE
7; RUN: llc -verify-machineinstrs < %t/hwdouble.ll -mtriple=powerpc-unknown-linux-gnu \
8; RUN:          -mattr=+spe |  FileCheck %t/hwdouble.ll -check-prefix=SPE
9; RUN: llc -verify-machineinstrs < %t/single.ll -mtriple=powerpc-unknown-linux-gnu \
10; RUN:          -mattr=+efpu2 |  FileCheck %t/single.ll
11; RUN: llc -verify-machineinstrs < %t/double.ll -mtriple=powerpc-unknown-linux-gnu \
12; RUN:          -mattr=+efpu2 |  FileCheck %t/double.ll -check-prefix=EFPU2
13
14;--- single.ll
15; single tests (identical for -mattr=+spe and -mattr=+efpu2)
16
17declare float @llvm.fabs.float(float)
18define float @test_float_abs(float %a) #0 {
19; CHECK-LABEL: test_float_abs:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    efsabs 3, 3
22; CHECK-NEXT:    blr
23  entry:
24    %0 = tail call float @llvm.fabs.float(float %a)
25    ret float %0
26}
27
28define float @test_fnabs(float %a) #0 {
29; CHECK-LABEL: test_fnabs:
30; CHECK:       # %bb.0: # %entry
31; CHECK-NEXT:    efsnabs 3, 3
32; CHECK-NEXT:    blr
33  entry:
34    %0 = tail call float @llvm.fabs.float(float %a)
35    %sub = fsub float -0.000000e+00, %0
36    ret float %sub
37}
38
39define float @test_fdiv(float %a, float %b) #0 {
40; CHECK-LABEL: test_fdiv:
41; CHECK:       # %bb.0: # %entry
42; CHECK-NEXT:    efsdiv 3, 3, 4
43; CHECK-NEXT:    blr
44entry:
45  %v = fdiv float %a, %b
46  ret float %v
47
48}
49
50define float @test_fmul(float %a, float %b) #0 {
51; CHECK-LABEL: test_fmul:
52; CHECK:       # %bb.0: # %entry
53; CHECK-NEXT:    efsmul 3, 3, 4
54; CHECK-NEXT:    blr
55  entry:
56  %v = fmul float %a, %b
57  ret float %v
58}
59
60define float @test_fadd(float %a, float %b) #0 {
61; CHECK-LABEL: test_fadd:
62; CHECK:       # %bb.0: # %entry
63; CHECK-NEXT:    efsadd 3, 3, 4
64; CHECK-NEXT:    blr
65  entry:
66  %v = fadd float %a, %b
67  ret float %v
68}
69
70define float @test_fsub(float %a, float %b) #0 {
71; CHECK-LABEL: test_fsub:
72; CHECK:       # %bb.0: # %entry
73; CHECK-NEXT:    efssub 3, 3, 4
74; CHECK-NEXT:    blr
75  entry:
76  %v = fsub float %a, %b
77  ret float %v
78}
79
80define float @test_fneg(float %a) #0 {
81; CHECK-LABEL: test_fneg:
82; CHECK:       # %bb.0: # %entry
83; CHECK-NEXT:    efsneg 3, 3
84; CHECK-NEXT:    blr
85  entry:
86  %v = fsub float -0.0, %a
87  ret float %v
88}
89
90define i32 @test_fcmpgt(float %a, float %b) #0 {
91; CHECK-LABEL: test_fcmpgt:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    stwu 1, -16(1)
94; CHECK-NEXT:    efscmpgt 0, 3, 4
95; CHECK-NEXT:    ble 0, .LBB7_2
96; CHECK-NEXT:  # %bb.1: # %tr
97; CHECK-NEXT:    li 3, 1
98; CHECK-NEXT:    b .LBB7_3
99; CHECK-NEXT:  .LBB7_2: # %fa
100; CHECK-NEXT:    li 3, 0
101; CHECK-NEXT:  .LBB7_3: # %ret
102; CHECK-NEXT:    stw 3, 12(1)
103; CHECK-NEXT:    lwz 3, 12(1)
104; CHECK-NEXT:    addi 1, 1, 16
105; CHECK-NEXT:    blr
106  entry:
107  %r = alloca i32, align 4
108  %c = fcmp ogt float %a, %b
109  br i1 %c, label %tr, label %fa
110tr:
111  store i32 1, i32* %r, align 4
112  br label %ret
113fa:
114  store i32 0, i32* %r, align 4
115  br label %ret
116ret:
117  %0 = load i32, i32* %r, align 4
118  ret i32 %0
119}
120
121define i32 @test_fcmpugt(float %a, float %b) #0 {
122; CHECK-LABEL: test_fcmpugt:
123; CHECK:       # %bb.0: # %entry
124; CHECK-NEXT:    stwu 1, -16(1)
125; CHECK-NEXT:    efscmpeq 0, 4, 4
126; CHECK-NEXT:    bc 4, 1, .LBB8_4
127; CHECK-NEXT:  # %bb.1: # %entry
128; CHECK-NEXT:    efscmpeq 0, 3, 3
129; CHECK-NEXT:    bc 4, 1, .LBB8_4
130; CHECK-NEXT:  # %bb.2: # %entry
131; CHECK-NEXT:    efscmpgt 0, 3, 4
132; CHECK-NEXT:    bc 12, 1, .LBB8_4
133; CHECK-NEXT:  # %bb.3: # %fa
134; CHECK-NEXT:    li 3, 0
135; CHECK-NEXT:    b .LBB8_5
136; CHECK-NEXT:  .LBB8_4: # %tr
137; CHECK-NEXT:    li 3, 1
138; CHECK-NEXT:  .LBB8_5: # %ret
139; CHECK-NEXT:    stw 3, 12(1)
140; CHECK-NEXT:    lwz 3, 12(1)
141; CHECK-NEXT:    addi 1, 1, 16
142; CHECK-NEXT:    blr
143  entry:
144  %r = alloca i32, align 4
145  %c = fcmp ugt float %a, %b
146  br i1 %c, label %tr, label %fa
147tr:
148  store i32 1, i32* %r, align 4
149  br label %ret
150fa:
151  store i32 0, i32* %r, align 4
152  br label %ret
153ret:
154  %0 = load i32, i32* %r, align 4
155  ret i32 %0
156}
157
158define i32 @test_fcmple(float %a, float %b) #0 {
159; CHECK-LABEL: test_fcmple:
160; CHECK:       # %bb.0: # %entry
161; CHECK-NEXT:    stwu 1, -16(1)
162; CHECK-NEXT:    efscmpeq 0, 3, 3
163; CHECK-NEXT:    bc 4, 1, .LBB9_4
164; CHECK-NEXT:  # %bb.1: # %entry
165; CHECK-NEXT:    efscmpeq 0, 4, 4
166; CHECK-NEXT:    bc 4, 1, .LBB9_4
167; CHECK-NEXT:  # %bb.2: # %entry
168; CHECK-NEXT:    efscmpgt 0, 3, 4
169; CHECK-NEXT:    bc 12, 1, .LBB9_4
170; CHECK-NEXT:  # %bb.3: # %tr
171; CHECK-NEXT:    li 3, 1
172; CHECK-NEXT:    b .LBB9_5
173; CHECK-NEXT:  .LBB9_4: # %fa
174; CHECK-NEXT:    li 3, 0
175; CHECK-NEXT:  .LBB9_5: # %ret
176; CHECK-NEXT:    stw 3, 12(1)
177; CHECK-NEXT:    lwz 3, 12(1)
178; CHECK-NEXT:    addi 1, 1, 16
179; CHECK-NEXT:    blr
180  entry:
181  %r = alloca i32, align 4
182  %c = fcmp ole float %a, %b
183  br i1 %c, label %tr, label %fa
184tr:
185  store i32 1, i32* %r, align 4
186  br label %ret
187fa:
188  store i32 0, i32* %r, align 4
189  br label %ret
190ret:
191  %0 = load i32, i32* %r, align 4
192  ret i32 %0
193}
194
195define i32 @test_fcmpule(float %a, float %b) #0 {
196; CHECK-LABEL: test_fcmpule:
197; CHECK:       # %bb.0: # %entry
198; CHECK-NEXT:    stwu 1, -16(1)
199; CHECK-NEXT:    efscmpgt 0, 3, 4
200; CHECK-NEXT:    bgt 0, .LBB10_2
201; CHECK-NEXT:  # %bb.1: # %tr
202; CHECK-NEXT:    li 3, 1
203; CHECK-NEXT:    b .LBB10_3
204; CHECK-NEXT:  .LBB10_2: # %fa
205; CHECK-NEXT:    li 3, 0
206; CHECK-NEXT:  .LBB10_3: # %ret
207; CHECK-NEXT:    stw 3, 12(1)
208; CHECK-NEXT:    lwz 3, 12(1)
209; CHECK-NEXT:    addi 1, 1, 16
210; CHECK-NEXT:    blr
211  entry:
212  %r = alloca i32, align 4
213  %c = fcmp ule float %a, %b
214  br i1 %c, label %tr, label %fa
215tr:
216  store i32 1, i32* %r, align 4
217  br label %ret
218fa:
219  store i32 0, i32* %r, align 4
220  br label %ret
221ret:
222  %0 = load i32, i32* %r, align 4
223  ret i32 %0
224}
225
226; The type of comparison found in C's if (x == y)
227define i32 @test_fcmpeq(float %a, float %b) #0 {
228; CHECK-LABEL: test_fcmpeq:
229; CHECK:       # %bb.0: # %entry
230; CHECK-NEXT:    stwu 1, -16(1)
231; CHECK-NEXT:    efscmpeq 0, 3, 4
232; CHECK-NEXT:    ble 0, .LBB11_2
233; CHECK-NEXT:  # %bb.1: # %tr
234; CHECK-NEXT:    li 3, 1
235; CHECK-NEXT:    b .LBB11_3
236; CHECK-NEXT:  .LBB11_2: # %fa
237; CHECK-NEXT:    li 3, 0
238; CHECK-NEXT:  .LBB11_3: # %ret
239; CHECK-NEXT:    stw 3, 12(1)
240; CHECK-NEXT:    lwz 3, 12(1)
241; CHECK-NEXT:    addi 1, 1, 16
242; CHECK-NEXT:    blr
243  entry:
244  %r = alloca i32, align 4
245  %c = fcmp oeq float %a, %b
246  br i1 %c, label %tr, label %fa
247tr:
248  store i32 1, i32* %r, align 4
249  br label %ret
250fa:
251  store i32 0, i32* %r, align 4
252  br label %ret
253ret:
254  %0 = load i32, i32* %r, align 4
255  ret i32 %0
256}
257
258; (un)ordered tests are expanded to une and oeq so verify
259define i1 @test_fcmpuno(float %a, float %b) #0 {
260; CHECK-LABEL: test_fcmpuno:
261; CHECK:       # %bb.0: # %entry
262; CHECK-NEXT:    efscmpeq 0, 3, 3
263; CHECK-NEXT:    efscmpeq 1, 4, 4
264; CHECK-NEXT:    li 5, 1
265; CHECK-NEXT:    crand 20, 5, 1
266; CHECK-NEXT:    bc 12, 20, .LBB12_2
267; CHECK-NEXT:  # %bb.1: # %entry
268; CHECK-NEXT:    ori 3, 5, 0
269; CHECK-NEXT:    blr
270; CHECK-NEXT:  .LBB12_2: # %entry
271; CHECK-NEXT:    li 3, 0
272; CHECK-NEXT:    blr
273  entry:
274  %r = fcmp uno float %a, %b
275  ret i1 %r
276}
277
278define i1 @test_fcmpord(float %a, float %b) #0 {
279; CHECK-LABEL: test_fcmpord:
280; CHECK:       # %bb.0: # %entry
281; CHECK-NEXT:    efscmpeq 0, 4, 4
282; CHECK-NEXT:    efscmpeq 1, 3, 3
283; CHECK-NEXT:    li 5, 1
284; CHECK-NEXT:    crnand 20, 5, 1
285; CHECK-NEXT:    bc 12, 20, .LBB13_2
286; CHECK-NEXT:  # %bb.1: # %entry
287; CHECK-NEXT:    ori 3, 5, 0
288; CHECK-NEXT:    blr
289; CHECK-NEXT:  .LBB13_2: # %entry
290; CHECK-NEXT:    li 3, 0
291; CHECK-NEXT:    blr
292  entry:
293  %r = fcmp ord float %a, %b
294  ret i1 %r
295}
296
297define i1 @test_fcmpueq(float %a, float %b) #0 {
298; CHECK-LABEL: test_fcmpueq:
299; CHECK:       # %bb.0: # %entry
300; CHECK-NEXT:    efscmpgt 0, 3, 4
301; CHECK-NEXT:    efscmplt 1, 3, 4
302; CHECK-NEXT:    li 5, 1
303; CHECK-NEXT:    cror 20, 5, 1
304; CHECK-NEXT:    bc 12, 20, .LBB14_2
305; CHECK-NEXT:  # %bb.1: # %entry
306; CHECK-NEXT:    ori 3, 5, 0
307; CHECK-NEXT:    blr
308; CHECK-NEXT:  .LBB14_2: # %entry
309; CHECK-NEXT:    li 3, 0
310; CHECK-NEXT:    blr
311  entry:
312  %r = fcmp ueq float %a, %b
313  ret i1 %r
314}
315
316define i1 @test_fcmpne(float %a, float %b) #0 {
317; CHECK-LABEL: test_fcmpne:
318; CHECK:       # %bb.0: # %entry
319; CHECK-NEXT:    efscmplt 0, 3, 4
320; CHECK-NEXT:    efscmpgt 1, 3, 4
321; CHECK-NEXT:    li 5, 1
322; CHECK-NEXT:    crnor 20, 5, 1
323; CHECK-NEXT:    bc 12, 20, .LBB15_2
324; CHECK-NEXT:  # %bb.1: # %entry
325; CHECK-NEXT:    ori 3, 5, 0
326; CHECK-NEXT:    blr
327; CHECK-NEXT:  .LBB15_2: # %entry
328; CHECK-NEXT:    li 3, 0
329; CHECK-NEXT:    blr
330  entry:
331  %r = fcmp one float %a, %b
332  ret i1 %r
333}
334
335define i32 @test_fcmpune(float %a, float %b) #0 {
336; CHECK-LABEL: test_fcmpune:
337; CHECK:       # %bb.0: # %entry
338; CHECK-NEXT:    stwu 1, -16(1)
339; CHECK-NEXT:    efscmpeq 0, 3, 4
340; CHECK-NEXT:    bgt 0, .LBB16_2
341; CHECK-NEXT:  # %bb.1: # %tr
342; CHECK-NEXT:    li 3, 1
343; CHECK-NEXT:    b .LBB16_3
344; CHECK-NEXT:  .LBB16_2: # %fa
345; CHECK-NEXT:    li 3, 0
346; CHECK-NEXT:  .LBB16_3: # %ret
347; CHECK-NEXT:    stw 3, 12(1)
348; CHECK-NEXT:    lwz 3, 12(1)
349; CHECK-NEXT:    addi 1, 1, 16
350; CHECK-NEXT:    blr
351  entry:
352  %r = alloca i32, align 4
353  %c = fcmp une float %a, %b
354  br i1 %c, label %tr, label %fa
355tr:
356  store i32 1, i32* %r, align 4
357  br label %ret
358fa:
359  store i32 0, i32* %r, align 4
360  br label %ret
361ret:
362  %0 = load i32, i32* %r, align 4
363  ret i32 %0
364}
365
366define i32 @test_fcmplt(float %a, float %b) #0 {
367; CHECK-LABEL: test_fcmplt:
368; CHECK:       # %bb.0: # %entry
369; CHECK-NEXT:    stwu 1, -16(1)
370; CHECK-NEXT:    efscmplt 0, 3, 4
371; CHECK-NEXT:    ble 0, .LBB17_2
372; CHECK-NEXT:  # %bb.1: # %tr
373; CHECK-NEXT:    li 3, 1
374; CHECK-NEXT:    b .LBB17_3
375; CHECK-NEXT:  .LBB17_2: # %fa
376; CHECK-NEXT:    li 3, 0
377; CHECK-NEXT:  .LBB17_3: # %ret
378; CHECK-NEXT:    stw 3, 12(1)
379; CHECK-NEXT:    lwz 3, 12(1)
380; CHECK-NEXT:    addi 1, 1, 16
381; CHECK-NEXT:    blr
382  entry:
383  %r = alloca i32, align 4
384  %c = fcmp olt float %a, %b
385  br i1 %c, label %tr, label %fa
386tr:
387  store i32 1, i32* %r, align 4
388  br label %ret
389fa:
390  store i32 0, i32* %r, align 4
391  br label %ret
392ret:
393  %0 = load i32, i32* %r, align 4
394  ret i32 %0
395}
396
397define i1 @test_fcmpult(float %a, float %b) #0 {
398; CHECK-LABEL: test_fcmpult:
399; CHECK:       # %bb.0: # %entry
400; CHECK-NEXT:    efscmpeq 0, 3, 3
401; CHECK-NEXT:    efscmpeq 1, 4, 4
402; CHECK-NEXT:    crnand 20, 5, 1
403; CHECK-NEXT:    efscmplt 0, 3, 4
404; CHECK-NEXT:    li 5, 1
405; CHECK-NEXT:    crnor 20, 1, 20
406; CHECK-NEXT:    bc 12, 20, .LBB18_2
407; CHECK-NEXT:  # %bb.1: # %entry
408; CHECK-NEXT:    ori 3, 5, 0
409; CHECK-NEXT:    blr
410; CHECK-NEXT:  .LBB18_2: # %entry
411; CHECK-NEXT:    li 3, 0
412; CHECK-NEXT:    blr
413  entry:
414  %r = fcmp ult float %a, %b
415  ret i1 %r
416}
417
418define i32 @test_fcmpge(float %a, float %b) #0 {
419; CHECK-LABEL: test_fcmpge:
420; CHECK:       # %bb.0: # %entry
421; CHECK-NEXT:    stwu 1, -16(1)
422; CHECK-NEXT:    efscmpeq 0, 3, 3
423; CHECK-NEXT:    bc 4, 1, .LBB19_4
424; CHECK-NEXT:  # %bb.1: # %entry
425; CHECK-NEXT:    efscmpeq 0, 4, 4
426; CHECK-NEXT:    bc 4, 1, .LBB19_4
427; CHECK-NEXT:  # %bb.2: # %entry
428; CHECK-NEXT:    efscmplt 0, 3, 4
429; CHECK-NEXT:    bc 12, 1, .LBB19_4
430; CHECK-NEXT:  # %bb.3: # %tr
431; CHECK-NEXT:    li 3, 1
432; CHECK-NEXT:    b .LBB19_5
433; CHECK-NEXT:  .LBB19_4: # %fa
434; CHECK-NEXT:    li 3, 0
435; CHECK-NEXT:  .LBB19_5: # %ret
436; CHECK-NEXT:    stw 3, 12(1)
437; CHECK-NEXT:    lwz 3, 12(1)
438; CHECK-NEXT:    addi 1, 1, 16
439; CHECK-NEXT:    blr
440  entry:
441  %r = alloca i32, align 4
442  %c = fcmp oge float %a, %b
443  br i1 %c, label %tr, label %fa
444tr:
445  store i32 1, i32* %r, align 4
446  br label %ret
447fa:
448  store i32 0, i32* %r, align 4
449  br label %ret
450ret:
451  %0 = load i32, i32* %r, align 4
452  ret i32 %0
453}
454
455define i32 @test_fcmpuge(float %a, float %b) #0 {
456; CHECK-LABEL: test_fcmpuge:
457; CHECK:       # %bb.0: # %entry
458; CHECK-NEXT:    stwu 1, -16(1)
459; CHECK-NEXT:    efscmplt 0, 3, 4
460; CHECK-NEXT:    bgt 0, .LBB20_2
461; CHECK-NEXT:  # %bb.1: # %tr
462; CHECK-NEXT:    li 3, 1
463; CHECK-NEXT:    b .LBB20_3
464; CHECK-NEXT:  .LBB20_2: # %fa
465; CHECK-NEXT:    li 3, 0
466; CHECK-NEXT:  .LBB20_3: # %ret
467; CHECK-NEXT:    stw 3, 12(1)
468; CHECK-NEXT:    lwz 3, 12(1)
469; CHECK-NEXT:    addi 1, 1, 16
470; CHECK-NEXT:    blr
471  entry:
472  %r = alloca i32, align 4
473  %c = fcmp uge float %a, %b
474  br i1 %c, label %tr, label %fa
475tr:
476  store i32 1, i32* %r, align 4
477  br label %ret
478fa:
479  store i32 0, i32* %r, align 4
480  br label %ret
481ret:
482  %0 = load i32, i32* %r, align 4
483  ret i32 %0
484}
485
486
487define i32 @test_ftoui(float %a) #0 {
488; CHECK-LABEL: test_ftoui:
489; CHECK:       # %bb.0:
490; CHECK-NEXT:    efsctuiz 3, 3
491; CHECK-NEXT:    blr
492  %v = fptoui float %a to i32
493  ret i32 %v
494}
495
496define i32 @test_ftosi(float %a) #0 {
497; CHECK-LABEL: test_ftosi:
498; CHECK:       # %bb.0:
499; CHECK-NEXT:    efsctsiz 3, 3
500; CHECK-NEXT:    blr
501  %v = fptosi float %a to i32
502  ret i32 %v
503}
504
505define float @test_ffromui(i32 %a) #0 {
506; CHECK-LABEL: test_ffromui:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    efscfui 3, 3
509; CHECK-NEXT:    blr
510  %v = uitofp i32 %a to float
511  ret float %v
512}
513
514define float @test_ffromsi(i32 %a) #0 {
515; CHECK-LABEL: test_ffromsi:
516; CHECK:       # %bb.0:
517; CHECK-NEXT:    efscfsi 3, 3
518; CHECK-NEXT:    blr
519  %v = sitofp i32 %a to float
520  ret float %v
521}
522
523define i32 @test_fasmconst(float %x) #0 {
524; CHECK-LABEL: test_fasmconst:
525; CHECK:       # %bb.0: # %entry
526; CHECK-NEXT:    stwu 1, -32(1)
527; CHECK-NEXT:    stw 3, 20(1)
528; CHECK-NEXT:    stw 3, 24(1)
529; CHECK-NEXT:    lwz 3, 20(1)
530; CHECK-NEXT:    #APP
531; CHECK-NEXT:    efsctsi 3, 3
532; CHECK-NEXT:    #NO_APP
533; CHECK-NEXT:    addi 1, 1, 32
534; CHECK-NEXT:    blr
535entry:
536  %x.addr = alloca float, align 8
537  store float %x, float* %x.addr, align 8
538  %0 = load float, float* %x.addr, align 8
539  %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
540  ret i32 %1
541; Check that it's not loading a double
542}
543attributes #0 = { nounwind }
544
545;--- double.ll
546; Double tests
547; results depend on -mattr=+spe or -mattr=+efpu2
548
549define float @test_dtos(double %a) #0 {
550; SPE-LABEL: test_dtos:
551; SPE:       # %bb.0: # %entry
552; SPE-NEXT:    evmergelo 3, 3, 4
553; SPE-NEXT:    efscfd 3, 3
554; SPE-NEXT:    blr
555;
556; EFPU2-LABEL: test_dtos:
557; EFPU2:       # %bb.0: # %entry
558; EFPU2-NEXT:    mflr 0
559; EFPU2-NEXT:    stw 0, 4(1)
560; EFPU2-NEXT:    stwu 1, -16(1)
561; EFPU2-NEXT:    bl __truncdfsf2
562; EFPU2-NEXT:    lwz 0, 20(1)
563; EFPU2-NEXT:    addi 1, 1, 16
564; EFPU2-NEXT:    mtlr 0
565; EFPU2-NEXT:    blr
566  entry:
567  %v = fptrunc double %a to float
568  ret float %v
569}
570
571define void @test_double_abs(double * %aa) #0 {
572; SPE-LABEL: test_double_abs:
573; SPE:       # %bb.0: # %entry
574; SPE-NEXT:    evldd 4, 0(3)
575; SPE-NEXT:    efdabs 4, 4
576; SPE-NEXT:    evstdd 4, 0(3)
577; SPE-NEXT:    blr
578;
579; EFPU2-LABEL: test_double_abs:
580; EFPU2:       # %bb.0: # %entry
581; EFPU2-NEXT:    lwz 4, 0(3)
582; EFPU2-NEXT:    clrlwi 4, 4, 1
583; EFPU2-NEXT:    stw 4, 0(3)
584; EFPU2-NEXT:    blr
585  entry:
586    %0 = load double, double * %aa
587    %1 = tail call double @llvm.fabs.f64(double %0) #2
588    store double %1, double * %aa
589    ret void
590}
591
592; Function Attrs: nounwind readnone
593declare double @llvm.fabs.f64(double) #1
594
595define void @test_dnabs(double * %aa) #0 {
596; SPE-LABEL: test_dnabs:
597; SPE:       # %bb.0: # %entry
598; SPE-NEXT:    evldd 4, 0(3)
599; SPE-NEXT:    efdnabs 4, 4
600; SPE-NEXT:    evstdd 4, 0(3)
601; SPE-NEXT:    blr
602;
603; EFPU2-LABEL: test_dnabs:
604; EFPU2:       # %bb.0: # %entry
605; EFPU2-NEXT:    lwz 4, 0(3)
606; EFPU2-NEXT:    oris 4, 4, 32768
607; EFPU2-NEXT:    stw 4, 0(3)
608; EFPU2-NEXT:    blr
609  entry:
610    %0 = load double, double * %aa
611    %1 = tail call double @llvm.fabs.f64(double %0) #2
612    %sub = fsub double -0.000000e+00, %1
613    store double %sub, double * %aa
614    ret void
615}
616
617define double @test_ddiv(double %a, double %b) #0 {
618; SPE-LABEL: test_ddiv:
619; SPE:       # %bb.0: # %entry
620; SPE-NEXT:    evmergelo 5, 5, 6
621; SPE-NEXT:    evmergelo 3, 3, 4
622; SPE-NEXT:    efddiv 4, 3, 5
623; SPE-NEXT:    evmergehi 3, 4, 4
624; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
625; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
626; SPE-NEXT:    blr
627;
628; EFPU2-LABEL: test_ddiv:
629; EFPU2:       # %bb.0: # %entry
630; EFPU2-NEXT:    mflr 0
631; EFPU2-NEXT:    stw 0, 4(1)
632; EFPU2-NEXT:    stwu 1, -16(1)
633; EFPU2-NEXT:    bl __divdf3
634; EFPU2-NEXT:    lwz 0, 20(1)
635; EFPU2-NEXT:    addi 1, 1, 16
636; EFPU2-NEXT:    mtlr 0
637; EFPU2-NEXT:    blr
638entry:
639  %v = fdiv double %a, %b
640  ret double %v
641
642}
643
644define double @test_dmul(double %a, double %b) #0 {
645; SPE-LABEL: test_dmul:
646; SPE:       # %bb.0: # %entry
647; SPE-NEXT:    evmergelo 5, 5, 6
648; SPE-NEXT:    evmergelo 3, 3, 4
649; SPE-NEXT:    efdmul 4, 3, 5
650; SPE-NEXT:    evmergehi 3, 4, 4
651; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
652; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
653; SPE-NEXT:    blr
654;
655; EFPU2-LABEL: test_dmul:
656; EFPU2:       # %bb.0: # %entry
657; EFPU2-NEXT:    mflr 0
658; EFPU2-NEXT:    stw 0, 4(1)
659; EFPU2-NEXT:    stwu 1, -16(1)
660; EFPU2-NEXT:    bl __muldf3
661; EFPU2-NEXT:    lwz 0, 20(1)
662; EFPU2-NEXT:    addi 1, 1, 16
663; EFPU2-NEXT:    mtlr 0
664; EFPU2-NEXT:    blr
665  entry:
666  %v = fmul double %a, %b
667  ret double %v
668}
669
670define double @test_dadd(double %a, double %b) #0 {
671; SPE-LABEL: test_dadd:
672; SPE:       # %bb.0: # %entry
673; SPE-NEXT:    evmergelo 5, 5, 6
674; SPE-NEXT:    evmergelo 3, 3, 4
675; SPE-NEXT:    efdadd 4, 3, 5
676; SPE-NEXT:    evmergehi 3, 4, 4
677; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
678; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
679; SPE-NEXT:    blr
680;
681; EFPU2-LABEL: test_dadd:
682; EFPU2:       # %bb.0: # %entry
683; EFPU2-NEXT:    mflr 0
684; EFPU2-NEXT:    stw 0, 4(1)
685; EFPU2-NEXT:    stwu 1, -16(1)
686; EFPU2-NEXT:    bl __adddf3
687; EFPU2-NEXT:    lwz 0, 20(1)
688; EFPU2-NEXT:    addi 1, 1, 16
689; EFPU2-NEXT:    mtlr 0
690; EFPU2-NEXT:    blr
691  entry:
692  %v = fadd double %a, %b
693  ret double %v
694}
695
696define double @test_dsub(double %a, double %b) #0 {
697; SPE-LABEL: test_dsub:
698; SPE:       # %bb.0: # %entry
699; SPE-NEXT:    evmergelo 5, 5, 6
700; SPE-NEXT:    evmergelo 3, 3, 4
701; SPE-NEXT:    efdsub 4, 3, 5
702; SPE-NEXT:    evmergehi 3, 4, 4
703; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
704; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
705; SPE-NEXT:    blr
706;
707; EFPU2-LABEL: test_dsub:
708; EFPU2:       # %bb.0: # %entry
709; EFPU2-NEXT:    mflr 0
710; EFPU2-NEXT:    stw 0, 4(1)
711; EFPU2-NEXT:    stwu 1, -16(1)
712; EFPU2-NEXT:    bl __subdf3
713; EFPU2-NEXT:    lwz 0, 20(1)
714; EFPU2-NEXT:    addi 1, 1, 16
715; EFPU2-NEXT:    mtlr 0
716; EFPU2-NEXT:    blr
717  entry:
718  %v = fsub double %a, %b
719  ret double %v
720}
721
722define double @test_dneg(double %a) #0 {
723; SPE-LABEL: test_dneg:
724; SPE:       # %bb.0: # %entry
725; SPE-NEXT:    evmergelo 3, 3, 4
726; SPE-NEXT:    efdneg 4, 3
727; SPE-NEXT:    evmergehi 3, 4, 4
728; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
729; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
730; SPE-NEXT:    blr
731;
732; EFPU2-LABEL: test_dneg:
733; EFPU2:       # %bb.0: # %entry
734; EFPU2-NEXT:    xoris 3, 3, 32768
735; EFPU2-NEXT:    blr
736  entry:
737  %v = fsub double -0.0, %a
738  ret double %v
739}
740
741define double @test_stod(float %a) #0 {
742; SPE-LABEL: test_stod:
743; SPE:       # %bb.0: # %entry
744; SPE-NEXT:    efdcfs 4, 3
745; SPE-NEXT:    evmergehi 3, 4, 4
746; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
747; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
748; SPE-NEXT:    blr
749;
750; EFPU2-LABEL: test_stod:
751; EFPU2:       # %bb.0: # %entry
752; EFPU2-NEXT:    mflr 0
753; EFPU2-NEXT:    stw 0, 4(1)
754; EFPU2-NEXT:    stwu 1, -16(1)
755; EFPU2-NEXT:    bl __extendsfdf2
756; EFPU2-NEXT:    lwz 0, 20(1)
757; EFPU2-NEXT:    addi 1, 1, 16
758; EFPU2-NEXT:    mtlr 0
759; EFPU2-NEXT:    blr
760  entry:
761  %v = fpext float %a to double
762  ret double %v
763}
764
765; (un)ordered tests are expanded to une and oeq so verify
766define i1 @test_dcmpuno(double %a, double %b) #0 {
767; SPE-LABEL: test_dcmpuno:
768; SPE:       # %bb.0: # %entry
769; SPE-NEXT:    evmergelo 5, 5, 6
770; SPE-NEXT:    evmergelo 3, 3, 4
771; SPE-NEXT:    li 7, 1
772; SPE-NEXT:    efdcmpeq 0, 3, 3
773; SPE-NEXT:    efdcmpeq 1, 5, 5
774; SPE-NEXT:    crand 20, 5, 1
775; SPE-NEXT:    bc 12, 20, .LBB9_2
776; SPE-NEXT:  # %bb.1: # %entry
777; SPE-NEXT:    ori 3, 7, 0
778; SPE-NEXT:    blr
779; SPE-NEXT:  .LBB9_2: # %entry
780; SPE-NEXT:    li 3, 0
781; SPE-NEXT:    blr
782;
783; EFPU2-LABEL: test_dcmpuno:
784; EFPU2:       # %bb.0: # %entry
785; EFPU2-NEXT:    mflr 0
786; EFPU2-NEXT:    stw 0, 4(1)
787; EFPU2-NEXT:    stwu 1, -16(1)
788; EFPU2-NEXT:    bl __unorddf2
789; EFPU2-NEXT:    cntlzw 3, 3
790; EFPU2-NEXT:    not 3, 3
791; EFPU2-NEXT:    rlwinm 3, 3, 27, 31, 31
792; EFPU2-NEXT:    lwz 0, 20(1)
793; EFPU2-NEXT:    addi 1, 1, 16
794; EFPU2-NEXT:    mtlr 0
795; EFPU2-NEXT:    blr
796  entry:
797  %r = fcmp uno double %a, %b
798  ret i1 %r
799}
800
801define i1 @test_dcmpord(double %a, double %b) #0 {
802; SPE-LABEL: test_dcmpord:
803; SPE:       # %bb.0: # %entry
804; SPE-NEXT:    evmergelo 3, 3, 4
805; SPE-NEXT:    evmergelo 4, 5, 6
806; SPE-NEXT:    li 7, 1
807; SPE-NEXT:    efdcmpeq 0, 4, 4
808; SPE-NEXT:    efdcmpeq 1, 3, 3
809; SPE-NEXT:    crnand 20, 5, 1
810; SPE-NEXT:    bc 12, 20, .LBB10_2
811; SPE-NEXT:  # %bb.1: # %entry
812; SPE-NEXT:    ori 3, 7, 0
813; SPE-NEXT:    blr
814; SPE-NEXT:  .LBB10_2: # %entry
815; SPE-NEXT:    li 3, 0
816; SPE-NEXT:    blr
817;
818; EFPU2-LABEL: test_dcmpord:
819; EFPU2:       # %bb.0: # %entry
820; EFPU2-NEXT:    mflr 0
821; EFPU2-NEXT:    stw 0, 4(1)
822; EFPU2-NEXT:    stwu 1, -16(1)
823; EFPU2-NEXT:    bl __unorddf2
824; EFPU2-NEXT:    cntlzw 3, 3
825; EFPU2-NEXT:    rlwinm 3, 3, 27, 31, 31
826; EFPU2-NEXT:    lwz 0, 20(1)
827; EFPU2-NEXT:    addi 1, 1, 16
828; EFPU2-NEXT:    mtlr 0
829; EFPU2-NEXT:    blr
830  entry:
831  %r = fcmp ord double %a, %b
832  ret i1 %r
833}
834
835define i32 @test_dcmpgt(double %a, double %b) #0 {
836; SPE-LABEL: test_dcmpgt:
837; SPE:       # %bb.0: # %entry
838; SPE-NEXT:    stwu 1, -16(1)
839; SPE-NEXT:    evmergelo 5, 5, 6
840; SPE-NEXT:    evmergelo 3, 3, 4
841; SPE-NEXT:    efdcmpgt 0, 3, 5
842; SPE-NEXT:    ble 0, .LBB11_2
843; SPE-NEXT:  # %bb.1: # %tr
844; SPE-NEXT:    li 3, 1
845; SPE-NEXT:    b .LBB11_3
846; SPE-NEXT:  .LBB11_2: # %fa
847; SPE-NEXT:    li 3, 0
848; SPE-NEXT:  .LBB11_3: # %ret
849; SPE-NEXT:    stw 3, 12(1)
850; SPE-NEXT:    lwz 3, 12(1)
851; SPE-NEXT:    addi 1, 1, 16
852; SPE-NEXT:    blr
853;
854; EFPU2-LABEL: test_dcmpgt:
855; EFPU2:       # %bb.0: # %entry
856; EFPU2-NEXT:    mflr 0
857; EFPU2-NEXT:    stw 0, 4(1)
858; EFPU2-NEXT:    stwu 1, -16(1)
859; EFPU2-NEXT:    bl __gtdf2
860; EFPU2-NEXT:    cmpwi 3, 1
861; EFPU2-NEXT:    blt 0, .LBB11_2
862; EFPU2-NEXT:  # %bb.1: # %tr
863; EFPU2-NEXT:    li 3, 1
864; EFPU2-NEXT:    b .LBB11_3
865; EFPU2-NEXT:  .LBB11_2: # %fa
866; EFPU2-NEXT:    li 3, 0
867; EFPU2-NEXT:  .LBB11_3: # %ret
868; EFPU2-NEXT:    stw 3, 12(1)
869; EFPU2-NEXT:    lwz 3, 12(1)
870; EFPU2-NEXT:    lwz 0, 20(1)
871; EFPU2-NEXT:    addi 1, 1, 16
872; EFPU2-NEXT:    mtlr 0
873; EFPU2-NEXT:    blr
874  entry:
875  %r = alloca i32, align 4
876  %c = fcmp ogt double %a, %b
877  br i1 %c, label %tr, label %fa
878tr:
879  store i32 1, i32* %r, align 4
880  br label %ret
881fa:
882  store i32 0, i32* %r, align 4
883  br label %ret
884ret:
885  %0 = load i32, i32* %r, align 4
886  ret i32 %0
887}
888
889define i32 @test_dcmpugt(double %a, double %b) #0 {
890; SPE-LABEL: test_dcmpugt:
891; SPE:       # %bb.0: # %entry
892; SPE-NEXT:    stwu 1, -16(1)
893; SPE-NEXT:    evmergelo 3, 3, 4
894; SPE-NEXT:    evmergelo 4, 5, 6
895; SPE-NEXT:    efdcmpeq 0, 4, 4
896; SPE-NEXT:    bc 4, 1, .LBB12_4
897; SPE-NEXT:  # %bb.1: # %entry
898; SPE-NEXT:    efdcmpeq 0, 3, 3
899; SPE-NEXT:    bc 4, 1, .LBB12_4
900; SPE-NEXT:  # %bb.2: # %entry
901; SPE-NEXT:    efdcmpgt 0, 3, 4
902; SPE-NEXT:    bc 12, 1, .LBB12_4
903; SPE-NEXT:  # %bb.3: # %fa
904; SPE-NEXT:    li 3, 0
905; SPE-NEXT:    b .LBB12_5
906; SPE-NEXT:  .LBB12_4: # %tr
907; SPE-NEXT:    li 3, 1
908; SPE-NEXT:  .LBB12_5: # %ret
909; SPE-NEXT:    stw 3, 12(1)
910; SPE-NEXT:    lwz 3, 12(1)
911; SPE-NEXT:    addi 1, 1, 16
912; SPE-NEXT:    blr
913;
914; EFPU2-LABEL: test_dcmpugt:
915; EFPU2:       # %bb.0: # %entry
916; EFPU2-NEXT:    mflr 0
917; EFPU2-NEXT:    stw 0, 4(1)
918; EFPU2-NEXT:    stwu 1, -16(1)
919; EFPU2-NEXT:    bl __ledf2
920; EFPU2-NEXT:    cmpwi 3, 1
921; EFPU2-NEXT:    blt 0, .LBB12_2
922; EFPU2-NEXT:  # %bb.1: # %tr
923; EFPU2-NEXT:    li 3, 1
924; EFPU2-NEXT:    b .LBB12_3
925; EFPU2-NEXT:  .LBB12_2: # %fa
926; EFPU2-NEXT:    li 3, 0
927; EFPU2-NEXT:  .LBB12_3: # %ret
928; EFPU2-NEXT:    stw 3, 12(1)
929; EFPU2-NEXT:    lwz 3, 12(1)
930; EFPU2-NEXT:    lwz 0, 20(1)
931; EFPU2-NEXT:    addi 1, 1, 16
932; EFPU2-NEXT:    mtlr 0
933; EFPU2-NEXT:    blr
934  entry:
935  %r = alloca i32, align 4
936  %c = fcmp ugt double %a, %b
937  br i1 %c, label %tr, label %fa
938tr:
939  store i32 1, i32* %r, align 4
940  br label %ret
941fa:
942  store i32 0, i32* %r, align 4
943  br label %ret
944ret:
945  %0 = load i32, i32* %r, align 4
946  ret i32 %0
947}
948
949define i32 @test_dcmple(double %a, double %b) #0 {
950; SPE-LABEL: test_dcmple:
951; SPE:       # %bb.0: # %entry
952; SPE-NEXT:    stwu 1, -16(1)
953; SPE-NEXT:    evmergelo 5, 5, 6
954; SPE-NEXT:    evmergelo 3, 3, 4
955; SPE-NEXT:    efdcmpgt 0, 3, 5
956; SPE-NEXT:    bgt 0, .LBB13_2
957; SPE-NEXT:  # %bb.1: # %tr
958; SPE-NEXT:    li 3, 1
959; SPE-NEXT:    b .LBB13_3
960; SPE-NEXT:  .LBB13_2: # %fa
961; SPE-NEXT:    li 3, 0
962; SPE-NEXT:  .LBB13_3: # %ret
963; SPE-NEXT:    stw 3, 12(1)
964; SPE-NEXT:    lwz 3, 12(1)
965; SPE-NEXT:    addi 1, 1, 16
966; SPE-NEXT:    blr
967;
968; EFPU2-LABEL: test_dcmple:
969; EFPU2:       # %bb.0: # %entry
970; EFPU2-NEXT:    mflr 0
971; EFPU2-NEXT:    stw 0, 4(1)
972; EFPU2-NEXT:    stwu 1, -16(1)
973; EFPU2-NEXT:    bl __gtdf2
974; EFPU2-NEXT:    cmpwi 3, 0
975; EFPU2-NEXT:    bgt 0, .LBB13_2
976; EFPU2-NEXT:  # %bb.1: # %tr
977; EFPU2-NEXT:    li 3, 1
978; EFPU2-NEXT:    b .LBB13_3
979; EFPU2-NEXT:  .LBB13_2: # %fa
980; EFPU2-NEXT:    li 3, 0
981; EFPU2-NEXT:  .LBB13_3: # %ret
982; EFPU2-NEXT:    stw 3, 12(1)
983; EFPU2-NEXT:    lwz 3, 12(1)
984; EFPU2-NEXT:    lwz 0, 20(1)
985; EFPU2-NEXT:    addi 1, 1, 16
986; EFPU2-NEXT:    mtlr 0
987; EFPU2-NEXT:    blr
988  entry:
989  %r = alloca i32, align 4
990  %c = fcmp ule double %a, %b
991  br i1 %c, label %tr, label %fa
992tr:
993  store i32 1, i32* %r, align 4
994  br label %ret
995fa:
996  store i32 0, i32* %r, align 4
997  br label %ret
998ret:
999  %0 = load i32, i32* %r, align 4
1000  ret i32 %0
1001}
1002
1003define i32 @test_dcmpule(double %a, double %b) #0 {
1004; SPE-LABEL: test_dcmpule:
1005; SPE:       # %bb.0: # %entry
1006; SPE-NEXT:    stwu 1, -16(1)
1007; SPE-NEXT:    evmergelo 5, 5, 6
1008; SPE-NEXT:    evmergelo 3, 3, 4
1009; SPE-NEXT:    efdcmpgt 0, 3, 5
1010; SPE-NEXT:    bgt 0, .LBB14_2
1011; SPE-NEXT:  # %bb.1: # %tr
1012; SPE-NEXT:    li 3, 1
1013; SPE-NEXT:    b .LBB14_3
1014; SPE-NEXT:  .LBB14_2: # %fa
1015; SPE-NEXT:    li 3, 0
1016; SPE-NEXT:  .LBB14_3: # %ret
1017; SPE-NEXT:    stw 3, 12(1)
1018; SPE-NEXT:    lwz 3, 12(1)
1019; SPE-NEXT:    addi 1, 1, 16
1020; SPE-NEXT:    blr
1021;
1022; EFPU2-LABEL: test_dcmpule:
1023; EFPU2:       # %bb.0: # %entry
1024; EFPU2-NEXT:    mflr 0
1025; EFPU2-NEXT:    stw 0, 4(1)
1026; EFPU2-NEXT:    stwu 1, -16(1)
1027; EFPU2-NEXT:    bl __gtdf2
1028; EFPU2-NEXT:    cmpwi 3, 0
1029; EFPU2-NEXT:    bgt 0, .LBB14_2
1030; EFPU2-NEXT:  # %bb.1: # %tr
1031; EFPU2-NEXT:    li 3, 1
1032; EFPU2-NEXT:    b .LBB14_3
1033; EFPU2-NEXT:  .LBB14_2: # %fa
1034; EFPU2-NEXT:    li 3, 0
1035; EFPU2-NEXT:  .LBB14_3: # %ret
1036; EFPU2-NEXT:    stw 3, 12(1)
1037; EFPU2-NEXT:    lwz 3, 12(1)
1038; EFPU2-NEXT:    lwz 0, 20(1)
1039; EFPU2-NEXT:    addi 1, 1, 16
1040; EFPU2-NEXT:    mtlr 0
1041; EFPU2-NEXT:    blr
1042  entry:
1043  %r = alloca i32, align 4
1044  %c = fcmp ule double %a, %b
1045  br i1 %c, label %tr, label %fa
1046tr:
1047  store i32 1, i32* %r, align 4
1048  br label %ret
1049fa:
1050  store i32 0, i32* %r, align 4
1051  br label %ret
1052ret:
1053  %0 = load i32, i32* %r, align 4
1054  ret i32 %0
1055}
1056
1057; The type of comparison found in C's if (x == y)
1058define i32 @test_dcmpeq(double %a, double %b) #0 {
1059; SPE-LABEL: test_dcmpeq:
1060; SPE:       # %bb.0: # %entry
1061; SPE-NEXT:    stwu 1, -16(1)
1062; SPE-NEXT:    evmergelo 5, 5, 6
1063; SPE-NEXT:    evmergelo 3, 3, 4
1064; SPE-NEXT:    efdcmpeq 0, 3, 5
1065; SPE-NEXT:    ble 0, .LBB15_2
1066; SPE-NEXT:  # %bb.1: # %tr
1067; SPE-NEXT:    li 3, 1
1068; SPE-NEXT:    b .LBB15_3
1069; SPE-NEXT:  .LBB15_2: # %fa
1070; SPE-NEXT:    li 3, 0
1071; SPE-NEXT:  .LBB15_3: # %ret
1072; SPE-NEXT:    stw 3, 12(1)
1073; SPE-NEXT:    lwz 3, 12(1)
1074; SPE-NEXT:    addi 1, 1, 16
1075; SPE-NEXT:    blr
1076;
1077; EFPU2-LABEL: test_dcmpeq:
1078; EFPU2:       # %bb.0: # %entry
1079; EFPU2-NEXT:    mflr 0
1080; EFPU2-NEXT:    stw 0, 4(1)
1081; EFPU2-NEXT:    stwu 1, -16(1)
1082; EFPU2-NEXT:    bl __nedf2
1083; EFPU2-NEXT:    cmplwi 3, 0
1084; EFPU2-NEXT:    bne 0, .LBB15_2
1085; EFPU2-NEXT:  # %bb.1: # %tr
1086; EFPU2-NEXT:    li 3, 1
1087; EFPU2-NEXT:    b .LBB15_3
1088; EFPU2-NEXT:  .LBB15_2: # %fa
1089; EFPU2-NEXT:    li 3, 0
1090; EFPU2-NEXT:  .LBB15_3: # %ret
1091; EFPU2-NEXT:    stw 3, 12(1)
1092; EFPU2-NEXT:    lwz 3, 12(1)
1093; EFPU2-NEXT:    lwz 0, 20(1)
1094; EFPU2-NEXT:    addi 1, 1, 16
1095; EFPU2-NEXT:    mtlr 0
1096; EFPU2-NEXT:    blr
1097  entry:
1098  %r = alloca i32, align 4
1099  %c = fcmp oeq double %a, %b
1100  br i1 %c, label %tr, label %fa
1101tr:
1102  store i32 1, i32* %r, align 4
1103  br label %ret
1104fa:
1105  store i32 0, i32* %r, align 4
1106  br label %ret
1107ret:
1108  %0 = load i32, i32* %r, align 4
1109  ret i32 %0
1110}
1111
1112define i32 @test_dcmpueq(double %a, double %b) #0 {
1113; SPE-LABEL: test_dcmpueq:
1114; SPE:       # %bb.0: # %entry
1115; SPE-NEXT:    stwu 1, -16(1)
1116; SPE-NEXT:    evmergelo 5, 5, 6
1117; SPE-NEXT:    evmergelo 3, 3, 4
1118; SPE-NEXT:    efdcmplt 0, 3, 5
1119; SPE-NEXT:    bc 12, 1, .LBB16_3
1120; SPE-NEXT:  # %bb.1: # %entry
1121; SPE-NEXT:    efdcmpgt 0, 3, 5
1122; SPE-NEXT:    bc 12, 1, .LBB16_3
1123; SPE-NEXT:  # %bb.2: # %tr
1124; SPE-NEXT:    li 3, 1
1125; SPE-NEXT:    b .LBB16_4
1126; SPE-NEXT:  .LBB16_3: # %fa
1127; SPE-NEXT:    li 3, 0
1128; SPE-NEXT:  .LBB16_4: # %ret
1129; SPE-NEXT:    stw 3, 12(1)
1130; SPE-NEXT:    lwz 3, 12(1)
1131; SPE-NEXT:    addi 1, 1, 16
1132; SPE-NEXT:    blr
1133;
1134; EFPU2-LABEL: test_dcmpueq:
1135; EFPU2:       # %bb.0: # %entry
1136; EFPU2-NEXT:    mflr 0
1137; EFPU2-NEXT:    stw 0, 4(1)
1138; EFPU2-NEXT:    stwu 1, -96(1)
1139; EFPU2-NEXT:    mfcr 12
1140; EFPU2-NEXT:    stw 27, 76(1) # 4-byte Folded Spill
1141; EFPU2-NEXT:    stw 28, 80(1) # 4-byte Folded Spill
1142; EFPU2-NEXT:    stw 29, 84(1) # 4-byte Folded Spill
1143; EFPU2-NEXT:    stw 30, 88(1) # 4-byte Folded Spill
1144; EFPU2-NEXT:    stw 12, 72(1)
1145; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
1146; EFPU2-NEXT:    mr 27, 3
1147; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
1148; EFPU2-NEXT:    mr 28, 4
1149; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
1150; EFPU2-NEXT:    mr 29, 5
1151; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
1152; EFPU2-NEXT:    mr 30, 6
1153; EFPU2-NEXT:    bl __eqdf2
1154; EFPU2-NEXT:    cmpwi 2, 3, 0
1155; EFPU2-NEXT:    mr 3, 27
1156; EFPU2-NEXT:    mr 4, 28
1157; EFPU2-NEXT:    mr 5, 29
1158; EFPU2-NEXT:    mr 6, 30
1159; EFPU2-NEXT:    bl __unorddf2
1160; EFPU2-NEXT:    bc 12, 10, .LBB16_3
1161; EFPU2-NEXT:  # %bb.1: # %entry
1162; EFPU2-NEXT:    cmpwi 3, 0
1163; EFPU2-NEXT:    bc 4, 2, .LBB16_3
1164; EFPU2-NEXT:  # %bb.2: # %fa
1165; EFPU2-NEXT:    li 3, 0
1166; EFPU2-NEXT:    b .LBB16_4
1167; EFPU2-NEXT:  .LBB16_3: # %tr
1168; EFPU2-NEXT:    li 3, 1
1169; EFPU2-NEXT:  .LBB16_4: # %ret
1170; EFPU2-NEXT:    stw 3, 20(1)
1171; EFPU2-NEXT:    lwz 3, 20(1)
1172; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
1173; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
1174; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
1175; EFPU2-NEXT:    lwz 12, 72(1)
1176; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
1177; EFPU2-NEXT:    mtcrf 32, 12 # cr2
1178; EFPU2-NEXT:    lwz 30, 88(1) # 4-byte Folded Reload
1179; EFPU2-NEXT:    lwz 29, 84(1) # 4-byte Folded Reload
1180; EFPU2-NEXT:    lwz 28, 80(1) # 4-byte Folded Reload
1181; EFPU2-NEXT:    lwz 27, 76(1) # 4-byte Folded Reload
1182; EFPU2-NEXT:    lwz 0, 100(1)
1183; EFPU2-NEXT:    addi 1, 1, 96
1184; EFPU2-NEXT:    mtlr 0
1185; EFPU2-NEXT:    blr
1186  entry:
1187  %r = alloca i32, align 4
1188  %c = fcmp ueq double %a, %b
1189  br i1 %c, label %tr, label %fa
1190tr:
1191  store i32 1, i32* %r, align 4
1192  br label %ret
1193fa:
1194  store i32 0, i32* %r, align 4
1195  br label %ret
1196ret:
1197  %0 = load i32, i32* %r, align 4
1198  ret i32 %0
1199}
1200
1201define i1 @test_dcmpne(double %a, double %b) #0 {
1202; SPE-LABEL: test_dcmpne:
1203; SPE:       # %bb.0: # %entry
1204; SPE-NEXT:    evmergelo 5, 5, 6
1205; SPE-NEXT:    evmergelo 3, 3, 4
1206; SPE-NEXT:    li 7, 1
1207; SPE-NEXT:    efdcmplt 0, 3, 5
1208; SPE-NEXT:    efdcmpgt 1, 3, 5
1209; SPE-NEXT:    crnor 20, 5, 1
1210; SPE-NEXT:    bc 12, 20, .LBB17_2
1211; SPE-NEXT:  # %bb.1: # %entry
1212; SPE-NEXT:    ori 3, 7, 0
1213; SPE-NEXT:    blr
1214; SPE-NEXT:  .LBB17_2: # %entry
1215; SPE-NEXT:    li 3, 0
1216; SPE-NEXT:    blr
1217;
1218; EFPU2-LABEL: test_dcmpne:
1219; EFPU2:       # %bb.0: # %entry
1220; EFPU2-NEXT:    mflr 0
1221; EFPU2-NEXT:    stw 0, 4(1)
1222; EFPU2-NEXT:    stwu 1, -96(1)
1223; EFPU2-NEXT:    mfcr 12
1224; EFPU2-NEXT:    stw 27, 76(1) # 4-byte Folded Spill
1225; EFPU2-NEXT:    stw 28, 80(1) # 4-byte Folded Spill
1226; EFPU2-NEXT:    stw 29, 84(1) # 4-byte Folded Spill
1227; EFPU2-NEXT:    stw 30, 88(1) # 4-byte Folded Spill
1228; EFPU2-NEXT:    stw 12, 72(1)
1229; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
1230; EFPU2-NEXT:    mr 27, 3
1231; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
1232; EFPU2-NEXT:    mr 28, 4
1233; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
1234; EFPU2-NEXT:    mr 29, 5
1235; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
1236; EFPU2-NEXT:    mr 30, 6
1237; EFPU2-NEXT:    bl __unorddf2
1238; EFPU2-NEXT:    cmpwi 2, 3, 0
1239; EFPU2-NEXT:    mr 3, 27
1240; EFPU2-NEXT:    mr 4, 28
1241; EFPU2-NEXT:    mr 5, 29
1242; EFPU2-NEXT:    mr 6, 30
1243; EFPU2-NEXT:    bl __eqdf2
1244; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
1245; EFPU2-NEXT:    cmpwi 3, 0
1246; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
1247; EFPU2-NEXT:    li 4, 1
1248; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
1249; EFPU2-NEXT:    crorc 20, 2, 10
1250; EFPU2-NEXT:    lwz 12, 72(1)
1251; EFPU2-NEXT:    bc 12, 20, .LBB17_2
1252; EFPU2-NEXT:  # %bb.1: # %entry
1253; EFPU2-NEXT:    ori 3, 4, 0
1254; EFPU2-NEXT:    b .LBB17_3
1255; EFPU2-NEXT:  .LBB17_2: # %entry
1256; EFPU2-NEXT:    li 3, 0
1257; EFPU2-NEXT:  .LBB17_3: # %entry
1258; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
1259; EFPU2-NEXT:    mtcrf 32, 12 # cr2
1260; EFPU2-NEXT:    lwz 30, 88(1) # 4-byte Folded Reload
1261; EFPU2-NEXT:    lwz 29, 84(1) # 4-byte Folded Reload
1262; EFPU2-NEXT:    lwz 28, 80(1) # 4-byte Folded Reload
1263; EFPU2-NEXT:    lwz 27, 76(1) # 4-byte Folded Reload
1264; EFPU2-NEXT:    lwz 0, 100(1)
1265; EFPU2-NEXT:    addi 1, 1, 96
1266; EFPU2-NEXT:    mtlr 0
1267; EFPU2-NEXT:    blr
1268  entry:
1269  %r = fcmp one double %a, %b
1270  ret i1 %r
1271}
1272
1273define i32 @test_dcmpune(double %a, double %b) #0 {
1274; SPE-LABEL: test_dcmpune:
1275; SPE:       # %bb.0: # %entry
1276; SPE-NEXT:    stwu 1, -16(1)
1277; SPE-NEXT:    evmergelo 5, 5, 6
1278; SPE-NEXT:    evmergelo 3, 3, 4
1279; SPE-NEXT:    efdcmpeq 0, 3, 5
1280; SPE-NEXT:    bgt 0, .LBB18_2
1281; SPE-NEXT:  # %bb.1: # %tr
1282; SPE-NEXT:    li 3, 1
1283; SPE-NEXT:    b .LBB18_3
1284; SPE-NEXT:  .LBB18_2: # %fa
1285; SPE-NEXT:    li 3, 0
1286; SPE-NEXT:  .LBB18_3: # %ret
1287; SPE-NEXT:    stw 3, 12(1)
1288; SPE-NEXT:    lwz 3, 12(1)
1289; SPE-NEXT:    addi 1, 1, 16
1290; SPE-NEXT:    blr
1291;
1292; EFPU2-LABEL: test_dcmpune:
1293; EFPU2:       # %bb.0: # %entry
1294; EFPU2-NEXT:    mflr 0
1295; EFPU2-NEXT:    stw 0, 4(1)
1296; EFPU2-NEXT:    stwu 1, -16(1)
1297; EFPU2-NEXT:    bl __eqdf2
1298; EFPU2-NEXT:    cmplwi 3, 0
1299; EFPU2-NEXT:    beq 0, .LBB18_2
1300; EFPU2-NEXT:  # %bb.1: # %tr
1301; EFPU2-NEXT:    li 3, 1
1302; EFPU2-NEXT:    b .LBB18_3
1303; EFPU2-NEXT:  .LBB18_2: # %fa
1304; EFPU2-NEXT:    li 3, 0
1305; EFPU2-NEXT:  .LBB18_3: # %ret
1306; EFPU2-NEXT:    stw 3, 12(1)
1307; EFPU2-NEXT:    lwz 3, 12(1)
1308; EFPU2-NEXT:    lwz 0, 20(1)
1309; EFPU2-NEXT:    addi 1, 1, 16
1310; EFPU2-NEXT:    mtlr 0
1311; EFPU2-NEXT:    blr
1312  entry:
1313  %r = alloca i32, align 4
1314  %c = fcmp une double %a, %b
1315  br i1 %c, label %tr, label %fa
1316tr:
1317  store i32 1, i32* %r, align 4
1318  br label %ret
1319fa:
1320  store i32 0, i32* %r, align 4
1321  br label %ret
1322ret:
1323  %0 = load i32, i32* %r, align 4
1324  ret i32 %0
1325}
1326
1327define i32 @test_dcmplt(double %a, double %b) #0 {
1328; SPE-LABEL: test_dcmplt:
1329; SPE:       # %bb.0: # %entry
1330; SPE-NEXT:    stwu 1, -16(1)
1331; SPE-NEXT:    evmergelo 5, 5, 6
1332; SPE-NEXT:    evmergelo 3, 3, 4
1333; SPE-NEXT:    efdcmplt 0, 3, 5
1334; SPE-NEXT:    ble 0, .LBB19_2
1335; SPE-NEXT:  # %bb.1: # %tr
1336; SPE-NEXT:    li 3, 1
1337; SPE-NEXT:    b .LBB19_3
1338; SPE-NEXT:  .LBB19_2: # %fa
1339; SPE-NEXT:    li 3, 0
1340; SPE-NEXT:  .LBB19_3: # %ret
1341; SPE-NEXT:    stw 3, 12(1)
1342; SPE-NEXT:    lwz 3, 12(1)
1343; SPE-NEXT:    addi 1, 1, 16
1344; SPE-NEXT:    blr
1345;
1346; EFPU2-LABEL: test_dcmplt:
1347; EFPU2:       # %bb.0: # %entry
1348; EFPU2-NEXT:    mflr 0
1349; EFPU2-NEXT:    stw 0, 4(1)
1350; EFPU2-NEXT:    stwu 1, -16(1)
1351; EFPU2-NEXT:    bl __ltdf2
1352; EFPU2-NEXT:    cmpwi 3, -1
1353; EFPU2-NEXT:    bgt 0, .LBB19_2
1354; EFPU2-NEXT:  # %bb.1: # %tr
1355; EFPU2-NEXT:    li 3, 1
1356; EFPU2-NEXT:    b .LBB19_3
1357; EFPU2-NEXT:  .LBB19_2: # %fa
1358; EFPU2-NEXT:    li 3, 0
1359; EFPU2-NEXT:  .LBB19_3: # %ret
1360; EFPU2-NEXT:    stw 3, 12(1)
1361; EFPU2-NEXT:    lwz 3, 12(1)
1362; EFPU2-NEXT:    lwz 0, 20(1)
1363; EFPU2-NEXT:    addi 1, 1, 16
1364; EFPU2-NEXT:    mtlr 0
1365; EFPU2-NEXT:    blr
1366  entry:
1367  %r = alloca i32, align 4
1368  %c = fcmp olt double %a, %b
1369  br i1 %c, label %tr, label %fa
1370tr:
1371  store i32 1, i32* %r, align 4
1372  br label %ret
1373fa:
1374  store i32 0, i32* %r, align 4
1375  br label %ret
1376ret:
1377  %0 = load i32, i32* %r, align 4
1378  ret i32 %0
1379}
1380
1381define i32 @test_dcmpult(double %a, double %b) #0 {
1382; SPE-LABEL: test_dcmpult:
1383; SPE:       # %bb.0: # %entry
1384; SPE-NEXT:    stwu 1, -16(1)
1385; SPE-NEXT:    evmergelo 3, 3, 4
1386; SPE-NEXT:    evmergelo 4, 5, 6
1387; SPE-NEXT:    efdcmpeq 0, 4, 4
1388; SPE-NEXT:    bc 4, 1, .LBB20_4
1389; SPE-NEXT:  # %bb.1: # %entry
1390; SPE-NEXT:    efdcmpeq 0, 3, 3
1391; SPE-NEXT:    bc 4, 1, .LBB20_4
1392; SPE-NEXT:  # %bb.2: # %entry
1393; SPE-NEXT:    efdcmplt 0, 3, 4
1394; SPE-NEXT:    bc 12, 1, .LBB20_4
1395; SPE-NEXT:  # %bb.3: # %fa
1396; SPE-NEXT:    li 3, 0
1397; SPE-NEXT:    b .LBB20_5
1398; SPE-NEXT:  .LBB20_4: # %tr
1399; SPE-NEXT:    li 3, 1
1400; SPE-NEXT:  .LBB20_5: # %ret
1401; SPE-NEXT:    stw 3, 12(1)
1402; SPE-NEXT:    lwz 3, 12(1)
1403; SPE-NEXT:    addi 1, 1, 16
1404; SPE-NEXT:    blr
1405;
1406; EFPU2-LABEL: test_dcmpult:
1407; EFPU2:       # %bb.0: # %entry
1408; EFPU2-NEXT:    mflr 0
1409; EFPU2-NEXT:    stw 0, 4(1)
1410; EFPU2-NEXT:    stwu 1, -16(1)
1411; EFPU2-NEXT:    bl __gedf2
1412; EFPU2-NEXT:    cmpwi 3, -1
1413; EFPU2-NEXT:    bgt 0, .LBB20_2
1414; EFPU2-NEXT:  # %bb.1: # %tr
1415; EFPU2-NEXT:    li 3, 1
1416; EFPU2-NEXT:    b .LBB20_3
1417; EFPU2-NEXT:  .LBB20_2: # %fa
1418; EFPU2-NEXT:    li 3, 0
1419; EFPU2-NEXT:  .LBB20_3: # %ret
1420; EFPU2-NEXT:    stw 3, 12(1)
1421; EFPU2-NEXT:    lwz 3, 12(1)
1422; EFPU2-NEXT:    lwz 0, 20(1)
1423; EFPU2-NEXT:    addi 1, 1, 16
1424; EFPU2-NEXT:    mtlr 0
1425; EFPU2-NEXT:    blr
1426  entry:
1427  %r = alloca i32, align 4
1428  %c = fcmp ult double %a, %b
1429  br i1 %c, label %tr, label %fa
1430tr:
1431  store i32 1, i32* %r, align 4
1432  br label %ret
1433fa:
1434  store i32 0, i32* %r, align 4
1435  br label %ret
1436ret:
1437  %0 = load i32, i32* %r, align 4
1438  ret i32 %0
1439}
1440
1441define i1 @test_dcmpge(double %a, double %b) #0 {
1442; SPE-LABEL: test_dcmpge:
1443; SPE:       # %bb.0: # %entry
1444; SPE-NEXT:    evmergelo 3, 3, 4
1445; SPE-NEXT:    evmergelo 4, 5, 6
1446; SPE-NEXT:    li 7, 1
1447; SPE-NEXT:    efdcmpeq 0, 4, 4
1448; SPE-NEXT:    efdcmpeq 1, 3, 3
1449; SPE-NEXT:    efdcmplt 5, 3, 4
1450; SPE-NEXT:    crand 24, 5, 1
1451; SPE-NEXT:    crorc 20, 21, 24
1452; SPE-NEXT:    bc 12, 20, .LBB21_2
1453; SPE-NEXT:  # %bb.1: # %entry
1454; SPE-NEXT:    ori 3, 7, 0
1455; SPE-NEXT:    blr
1456; SPE-NEXT:  .LBB21_2: # %entry
1457; SPE-NEXT:    li 3, 0
1458; SPE-NEXT:    blr
1459;
1460; EFPU2-LABEL: test_dcmpge:
1461; EFPU2:       # %bb.0: # %entry
1462; EFPU2-NEXT:    mflr 0
1463; EFPU2-NEXT:    stw 0, 4(1)
1464; EFPU2-NEXT:    stwu 1, -16(1)
1465; EFPU2-NEXT:    bl __gedf2
1466; EFPU2-NEXT:    not 3, 3
1467; EFPU2-NEXT:    srwi 3, 3, 31
1468; EFPU2-NEXT:    lwz 0, 20(1)
1469; EFPU2-NEXT:    addi 1, 1, 16
1470; EFPU2-NEXT:    mtlr 0
1471; EFPU2-NEXT:    blr
1472  entry:
1473  %r = fcmp oge double %a, %b
1474  ret i1 %r
1475}
1476
1477define i32 @test_dcmpuge(double %a, double %b) #0 {
1478; SPE-LABEL: test_dcmpuge:
1479; SPE:       # %bb.0: # %entry
1480; SPE-NEXT:    stwu 1, -16(1)
1481; SPE-NEXT:    evmergelo 5, 5, 6
1482; SPE-NEXT:    evmergelo 3, 3, 4
1483; SPE-NEXT:    efdcmplt 0, 3, 5
1484; SPE-NEXT:    bgt 0, .LBB22_2
1485; SPE-NEXT:  # %bb.1: # %tr
1486; SPE-NEXT:    li 3, 1
1487; SPE-NEXT:    b .LBB22_3
1488; SPE-NEXT:  .LBB22_2: # %fa
1489; SPE-NEXT:    li 3, 0
1490; SPE-NEXT:  .LBB22_3: # %ret
1491; SPE-NEXT:    stw 3, 12(1)
1492; SPE-NEXT:    lwz 3, 12(1)
1493; SPE-NEXT:    addi 1, 1, 16
1494; SPE-NEXT:    blr
1495;
1496; EFPU2-LABEL: test_dcmpuge:
1497; EFPU2:       # %bb.0: # %entry
1498; EFPU2-NEXT:    mflr 0
1499; EFPU2-NEXT:    stw 0, 4(1)
1500; EFPU2-NEXT:    stwu 1, -16(1)
1501; EFPU2-NEXT:    bl __ltdf2
1502; EFPU2-NEXT:    cmpwi 3, 0
1503; EFPU2-NEXT:    blt 0, .LBB22_2
1504; EFPU2-NEXT:  # %bb.1: # %tr
1505; EFPU2-NEXT:    li 3, 1
1506; EFPU2-NEXT:    b .LBB22_3
1507; EFPU2-NEXT:  .LBB22_2: # %fa
1508; EFPU2-NEXT:    li 3, 0
1509; EFPU2-NEXT:  .LBB22_3: # %ret
1510; EFPU2-NEXT:    stw 3, 12(1)
1511; EFPU2-NEXT:    lwz 3, 12(1)
1512; EFPU2-NEXT:    lwz 0, 20(1)
1513; EFPU2-NEXT:    addi 1, 1, 16
1514; EFPU2-NEXT:    mtlr 0
1515; EFPU2-NEXT:    blr
1516  entry:
1517  %r = alloca i32, align 4
1518  %c = fcmp uge double %a, %b
1519  br i1 %c, label %tr, label %fa
1520tr:
1521  store i32 1, i32* %r, align 4
1522  br label %ret
1523fa:
1524  store i32 0, i32* %r, align 4
1525  br label %ret
1526ret:
1527  %0 = load i32, i32* %r, align 4
1528  ret i32 %0
1529}
1530
1531define double @test_dselect(double %a, double %b, i1 %c) #0 {
1532; SPE-LABEL: test_dselect:
1533; SPE:       # %bb.0: # %entry
1534; SPE-NEXT:    andi. 7, 7, 1
1535; SPE-NEXT:    evmergelo 5, 5, 6
1536; SPE-NEXT:    evmergelo 4, 3, 4
1537; SPE-NEXT:    bc 12, 1, .LBB23_2
1538; SPE-NEXT:  # %bb.1: # %entry
1539; SPE-NEXT:    evor 4, 5, 5
1540; SPE-NEXT:  .LBB23_2: # %entry
1541; SPE-NEXT:    evmergehi 3, 4, 4
1542; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
1543; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1544; SPE-NEXT:    blr
1545;
1546; EFPU2-LABEL: test_dselect:
1547; EFPU2:       # %bb.0: # %entry
1548; EFPU2-NEXT:    andi. 7, 7, 1
1549; EFPU2-NEXT:    bclr 12, 1, 0
1550; EFPU2-NEXT:  # %bb.1: # %entry
1551; EFPU2-NEXT:    ori 3, 5, 0
1552; EFPU2-NEXT:    ori 4, 6, 0
1553; EFPU2-NEXT:    blr
1554entry:
1555  %r = select i1 %c, double %a, double %b
1556  ret double %r
1557}
1558
1559define i32 @test_dtoui(double %a) #0 {
1560; SPE-LABEL: test_dtoui:
1561; SPE:       # %bb.0: # %entry
1562; SPE-NEXT:    evmergelo 3, 3, 4
1563; SPE-NEXT:    efdctuiz 3, 3
1564; SPE-NEXT:    blr
1565;
1566; EFPU2-LABEL: test_dtoui:
1567; EFPU2:       # %bb.0: # %entry
1568; EFPU2-NEXT:    mflr 0
1569; EFPU2-NEXT:    stw 0, 4(1)
1570; EFPU2-NEXT:    stwu 1, -16(1)
1571; EFPU2-NEXT:    bl __fixunsdfsi
1572; EFPU2-NEXT:    lwz 0, 20(1)
1573; EFPU2-NEXT:    addi 1, 1, 16
1574; EFPU2-NEXT:    mtlr 0
1575; EFPU2-NEXT:    blr
1576entry:
1577  %v = fptoui double %a to i32
1578  ret i32 %v
1579}
1580
1581define i32 @test_dtosi(double %a) #0 {
1582; SPE-LABEL: test_dtosi:
1583; SPE:       # %bb.0: # %entry
1584; SPE-NEXT:    evmergelo 3, 3, 4
1585; SPE-NEXT:    efdctsiz 3, 3
1586; SPE-NEXT:    blr
1587;
1588; EFPU2-LABEL: test_dtosi:
1589; EFPU2:       # %bb.0: # %entry
1590; EFPU2-NEXT:    mflr 0
1591; EFPU2-NEXT:    stw 0, 4(1)
1592; EFPU2-NEXT:    stwu 1, -16(1)
1593; EFPU2-NEXT:    bl __fixdfsi
1594; EFPU2-NEXT:    lwz 0, 20(1)
1595; EFPU2-NEXT:    addi 1, 1, 16
1596; EFPU2-NEXT:    mtlr 0
1597; EFPU2-NEXT:    blr
1598entry:
1599  %v = fptosi double %a to i32
1600  ret i32 %v
1601}
1602
1603define double @test_dfromui(i32 %a) #0 {
1604; SPE-LABEL: test_dfromui:
1605; SPE:       # %bb.0: # %entry
1606; SPE-NEXT:    efdcfui 4, 3
1607; SPE-NEXT:    evmergehi 3, 4, 4
1608; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
1609; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1610; SPE-NEXT:    blr
1611;
1612; EFPU2-LABEL: test_dfromui:
1613; EFPU2:       # %bb.0: # %entry
1614; EFPU2-NEXT:    mflr 0
1615; EFPU2-NEXT:    stw 0, 4(1)
1616; EFPU2-NEXT:    stwu 1, -16(1)
1617; EFPU2-NEXT:    bl __floatunsidf
1618; EFPU2-NEXT:    lwz 0, 20(1)
1619; EFPU2-NEXT:    addi 1, 1, 16
1620; EFPU2-NEXT:    mtlr 0
1621; EFPU2-NEXT:    blr
1622entry:
1623  %v = uitofp i32 %a to double
1624  ret double %v
1625}
1626
1627define double @test_dfromsi(i32 %a) #0 {
1628; SPE-LABEL: test_dfromsi:
1629; SPE:       # %bb.0: # %entry
1630; SPE-NEXT:    efdcfsi 4, 3
1631; SPE-NEXT:    evmergehi 3, 4, 4
1632; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
1633; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1634; SPE-NEXT:    blr
1635;
1636; EFPU2-LABEL: test_dfromsi:
1637; EFPU2:       # %bb.0: # %entry
1638; EFPU2-NEXT:    mflr 0
1639; EFPU2-NEXT:    stw 0, 4(1)
1640; EFPU2-NEXT:    stwu 1, -16(1)
1641; EFPU2-NEXT:    bl __floatsidf
1642; EFPU2-NEXT:    lwz 0, 20(1)
1643; EFPU2-NEXT:    addi 1, 1, 16
1644; EFPU2-NEXT:    mtlr 0
1645; EFPU2-NEXT:    blr
1646entry:
1647  %v = sitofp i32 %a to double
1648  ret double %v
1649}
1650
1651declare double @test_spill_spe_regs(double, double);
1652define dso_local void @test_func2() #0 {
1653; SPE-LABEL: test_func2:
1654; SPE:       # %bb.0: # %entry
1655; SPE-NEXT:    blr
1656;
1657; EFPU2-LABEL: test_func2:
1658; EFPU2:       # %bb.0: # %entry
1659; EFPU2-NEXT:    blr
1660entry:
1661  ret void
1662}
1663
1664declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
1665@global_var1 = global i32 0, align 4
1666define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) #0 {
1667; SPE-LABEL: test_spill:
1668; SPE:       # %bb.0: # %entry
1669; SPE-NEXT:    mflr 0
1670; SPE-NEXT:    stw 0, 4(1)
1671; SPE-NEXT:    stwu 1, -352(1)
1672; SPE-NEXT:    li 5, 256
1673; SPE-NEXT:    evstddx 30, 1, 5 # 8-byte Folded Spill
1674; SPE-NEXT:    li 5, 264
1675; SPE-NEXT:    evstddx 31, 1, 5 # 8-byte Folded Spill
1676; SPE-NEXT:    li 5, .LCPI29_0@l
1677; SPE-NEXT:    lis 6, .LCPI29_0@ha
1678; SPE-NEXT:    evlddx 5, 6, 5
1679; SPE-NEXT:    stw 14, 280(1) # 4-byte Folded Spill
1680; SPE-NEXT:    stw 15, 284(1) # 4-byte Folded Spill
1681; SPE-NEXT:    stw 16, 288(1) # 4-byte Folded Spill
1682; SPE-NEXT:    stw 17, 292(1) # 4-byte Folded Spill
1683; SPE-NEXT:    stw 18, 296(1) # 4-byte Folded Spill
1684; SPE-NEXT:    stw 19, 300(1) # 4-byte Folded Spill
1685; SPE-NEXT:    stw 20, 304(1) # 4-byte Folded Spill
1686; SPE-NEXT:    stw 21, 308(1) # 4-byte Folded Spill
1687; SPE-NEXT:    stw 22, 312(1) # 4-byte Folded Spill
1688; SPE-NEXT:    stw 23, 316(1) # 4-byte Folded Spill
1689; SPE-NEXT:    stw 24, 320(1) # 4-byte Folded Spill
1690; SPE-NEXT:    stw 25, 324(1) # 4-byte Folded Spill
1691; SPE-NEXT:    stw 26, 328(1) # 4-byte Folded Spill
1692; SPE-NEXT:    stw 27, 332(1) # 4-byte Folded Spill
1693; SPE-NEXT:    stw 28, 336(1) # 4-byte Folded Spill
1694; SPE-NEXT:    stw 29, 340(1) # 4-byte Folded Spill
1695; SPE-NEXT:    stw 30, 344(1) # 4-byte Folded Spill
1696; SPE-NEXT:    stw 31, 348(1) # 4-byte Folded Spill
1697; SPE-NEXT:    evstdd 14, 128(1) # 8-byte Folded Spill
1698; SPE-NEXT:    evstdd 15, 136(1) # 8-byte Folded Spill
1699; SPE-NEXT:    evstdd 16, 144(1) # 8-byte Folded Spill
1700; SPE-NEXT:    evstdd 17, 152(1) # 8-byte Folded Spill
1701; SPE-NEXT:    evstdd 18, 160(1) # 8-byte Folded Spill
1702; SPE-NEXT:    evstdd 19, 168(1) # 8-byte Folded Spill
1703; SPE-NEXT:    evstdd 20, 176(1) # 8-byte Folded Spill
1704; SPE-NEXT:    evstdd 21, 184(1) # 8-byte Folded Spill
1705; SPE-NEXT:    evstdd 22, 192(1) # 8-byte Folded Spill
1706; SPE-NEXT:    evstdd 23, 200(1) # 8-byte Folded Spill
1707; SPE-NEXT:    evstdd 24, 208(1) # 8-byte Folded Spill
1708; SPE-NEXT:    evstdd 25, 216(1) # 8-byte Folded Spill
1709; SPE-NEXT:    evstdd 26, 224(1) # 8-byte Folded Spill
1710; SPE-NEXT:    evstdd 27, 232(1) # 8-byte Folded Spill
1711; SPE-NEXT:    evstdd 28, 240(1) # 8-byte Folded Spill
1712; SPE-NEXT:    evstdd 29, 248(1) # 8-byte Folded Spill
1713; SPE-NEXT:    evmergelo 3, 3, 4
1714; SPE-NEXT:    lwz 4, 360(1)
1715; SPE-NEXT:    efdadd 3, 3, 3
1716; SPE-NEXT:    efdadd 3, 3, 5
1717; SPE-NEXT:    evstdd 3, 24(1) # 8-byte Folded Spill
1718; SPE-NEXT:    stw 4, 20(1) # 4-byte Folded Spill
1719; SPE-NEXT:    #APP
1720; SPE-NEXT:    #NO_APP
1721; SPE-NEXT:    addi 3, 1, 76
1722; SPE-NEXT:    li 4, 0
1723; SPE-NEXT:    li 5, 24
1724; SPE-NEXT:    li 6, 1
1725; SPE-NEXT:    li 30, 0
1726; SPE-NEXT:    bl test_memset
1727; SPE-NEXT:    lwz 3, 20(1) # 4-byte Folded Reload
1728; SPE-NEXT:    stw 30, 0(3)
1729; SPE-NEXT:    bl test_func2
1730; SPE-NEXT:    addi 3, 1, 32
1731; SPE-NEXT:    li 4, 0
1732; SPE-NEXT:    li 5, 20
1733; SPE-NEXT:    li 6, 1
1734; SPE-NEXT:    bl test_memset
1735; SPE-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
1736; SPE-NEXT:    li 5, 264
1737; SPE-NEXT:    evmergehi 3, 4, 4
1738; SPE-NEXT:    evlddx 31, 1, 5 # 8-byte Folded Reload
1739; SPE-NEXT:    li 5, 256
1740; SPE-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
1741; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1742; SPE-NEXT:    # kill: def $r4 killed $r4 killed $s4
1743; SPE-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
1744; SPE-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
1745; SPE-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
1746; SPE-NEXT:    evldd 26, 224(1) # 8-byte Folded Reload
1747; SPE-NEXT:    evldd 25, 216(1) # 8-byte Folded Reload
1748; SPE-NEXT:    evldd 24, 208(1) # 8-byte Folded Reload
1749; SPE-NEXT:    evldd 23, 200(1) # 8-byte Folded Reload
1750; SPE-NEXT:    evldd 22, 192(1) # 8-byte Folded Reload
1751; SPE-NEXT:    evldd 21, 184(1) # 8-byte Folded Reload
1752; SPE-NEXT:    evldd 20, 176(1) # 8-byte Folded Reload
1753; SPE-NEXT:    evldd 19, 168(1) # 8-byte Folded Reload
1754; SPE-NEXT:    evldd 18, 160(1) # 8-byte Folded Reload
1755; SPE-NEXT:    evldd 17, 152(1) # 8-byte Folded Reload
1756; SPE-NEXT:    evldd 16, 144(1) # 8-byte Folded Reload
1757; SPE-NEXT:    evldd 15, 136(1) # 8-byte Folded Reload
1758; SPE-NEXT:    evldd 14, 128(1) # 8-byte Folded Reload
1759; SPE-NEXT:    lwz 31, 348(1) # 4-byte Folded Reload
1760; SPE-NEXT:    lwz 30, 344(1) # 4-byte Folded Reload
1761; SPE-NEXT:    lwz 29, 340(1) # 4-byte Folded Reload
1762; SPE-NEXT:    lwz 28, 336(1) # 4-byte Folded Reload
1763; SPE-NEXT:    lwz 27, 332(1) # 4-byte Folded Reload
1764; SPE-NEXT:    lwz 26, 328(1) # 4-byte Folded Reload
1765; SPE-NEXT:    lwz 25, 324(1) # 4-byte Folded Reload
1766; SPE-NEXT:    lwz 24, 320(1) # 4-byte Folded Reload
1767; SPE-NEXT:    lwz 23, 316(1) # 4-byte Folded Reload
1768; SPE-NEXT:    lwz 22, 312(1) # 4-byte Folded Reload
1769; SPE-NEXT:    lwz 21, 308(1) # 4-byte Folded Reload
1770; SPE-NEXT:    lwz 20, 304(1) # 4-byte Folded Reload
1771; SPE-NEXT:    lwz 19, 300(1) # 4-byte Folded Reload
1772; SPE-NEXT:    lwz 18, 296(1) # 4-byte Folded Reload
1773; SPE-NEXT:    lwz 17, 292(1) # 4-byte Folded Reload
1774; SPE-NEXT:    lwz 16, 288(1) # 4-byte Folded Reload
1775; SPE-NEXT:    lwz 15, 284(1) # 4-byte Folded Reload
1776; SPE-NEXT:    lwz 14, 280(1) # 4-byte Folded Reload
1777; SPE-NEXT:    lwz 0, 356(1)
1778; SPE-NEXT:    addi 1, 1, 352
1779; SPE-NEXT:    mtlr 0
1780; SPE-NEXT:    blr
1781;
1782; EFPU2-LABEL: test_spill:
1783; EFPU2:       # %bb.0: # %entry
1784; EFPU2-NEXT:    mflr 0
1785; EFPU2-NEXT:    stw 0, 4(1)
1786; EFPU2-NEXT:    stwu 1, -176(1)
1787; EFPU2-NEXT:    mr 5, 3
1788; EFPU2-NEXT:    mr 6, 4
1789; EFPU2-NEXT:    stw 27, 156(1) # 4-byte Folded Spill
1790; EFPU2-NEXT:    stw 28, 160(1) # 4-byte Folded Spill
1791; EFPU2-NEXT:    stw 29, 164(1) # 4-byte Folded Spill
1792; EFPU2-NEXT:    stw 30, 168(1) # 4-byte Folded Spill
1793; EFPU2-NEXT:    evstdd 27, 104(1) # 8-byte Folded Spill
1794; EFPU2-NEXT:    evstdd 28, 112(1) # 8-byte Folded Spill
1795; EFPU2-NEXT:    evstdd 29, 120(1) # 8-byte Folded Spill
1796; EFPU2-NEXT:    evstdd 30, 128(1) # 8-byte Folded Spill
1797; EFPU2-NEXT:    lwz 28, 184(1)
1798; EFPU2-NEXT:    bl __adddf3
1799; EFPU2-NEXT:    lis 5, 16393
1800; EFPU2-NEXT:    lis 6, -4069
1801; EFPU2-NEXT:    ori 5, 5, 8697
1802; EFPU2-NEXT:    ori 6, 6, 34414
1803; EFPU2-NEXT:    #APP
1804; EFPU2-NEXT:    #NO_APP
1805; EFPU2-NEXT:    bl __adddf3
1806; EFPU2-NEXT:    mr 30, 3
1807; EFPU2-NEXT:    mr 29, 4
1808; EFPU2-NEXT:    addi 3, 1, 52
1809; EFPU2-NEXT:    li 4, 0
1810; EFPU2-NEXT:    li 5, 24
1811; EFPU2-NEXT:    li 6, 1
1812; EFPU2-NEXT:    li 27, 0
1813; EFPU2-NEXT:    bl test_memset
1814; EFPU2-NEXT:    stw 27, 0(28)
1815; EFPU2-NEXT:    bl test_func2
1816; EFPU2-NEXT:    addi 3, 1, 8
1817; EFPU2-NEXT:    li 4, 0
1818; EFPU2-NEXT:    li 5, 20
1819; EFPU2-NEXT:    li 6, 1
1820; EFPU2-NEXT:    bl test_memset
1821; EFPU2-NEXT:    mr 3, 30
1822; EFPU2-NEXT:    mr 4, 29
1823; EFPU2-NEXT:    evldd 30, 128(1) # 8-byte Folded Reload
1824; EFPU2-NEXT:    evldd 29, 120(1) # 8-byte Folded Reload
1825; EFPU2-NEXT:    evldd 28, 112(1) # 8-byte Folded Reload
1826; EFPU2-NEXT:    evldd 27, 104(1) # 8-byte Folded Reload
1827; EFPU2-NEXT:    lwz 30, 168(1) # 4-byte Folded Reload
1828; EFPU2-NEXT:    lwz 29, 164(1) # 4-byte Folded Reload
1829; EFPU2-NEXT:    lwz 28, 160(1) # 4-byte Folded Reload
1830; EFPU2-NEXT:    lwz 27, 156(1) # 4-byte Folded Reload
1831; EFPU2-NEXT:    lwz 0, 180(1)
1832; EFPU2-NEXT:    addi 1, 1, 176
1833; EFPU2-NEXT:    mtlr 0
1834; EFPU2-NEXT:    blr
1835entry:
1836  %v1 = alloca [13 x i32], align 4
1837  %v2 = alloca [11 x i32], align 4
1838  %0 = fadd double %a, %a
1839  call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
1840  %1 = fadd double %0, 3.14159
1841  %2 = bitcast [13 x i32]* %v1 to i8*
1842  call void @test_memset(i8* align 4 %2, i8 0, i32 24, i1 true)
1843  store i32 0, i32* %a5, align 4
1844  call void @test_func2()
1845  %3 = bitcast [11 x i32]* %v2 to i8*
1846  call void @test_memset(i8* align 4 %3, i8 0, i32 20, i1 true)
1847  br label %return
1848
1849return:
1850  ret double %1
1851
1852}
1853
1854define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
1855; SPE-LABEL: test_fma:
1856; SPE:       # %bb.0: # %entry
1857; SPE-NEXT:    mflr 0
1858; SPE-NEXT:    stw 0, 4(1)
1859; SPE-NEXT:    stwu 1, -48(1)
1860; SPE-NEXT:    cmpwi 3, 1
1861; SPE-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
1862; SPE-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
1863; SPE-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
1864; SPE-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
1865; SPE-NEXT:    blt 0, .LBB30_3
1866; SPE-NEXT:  # %bb.1: # %for.body.preheader
1867; SPE-NEXT:    mr 30, 3
1868; SPE-NEXT:    li 29, 0
1869; SPE-NEXT:    # implicit-def: $r5
1870; SPE-NEXT:  .LBB30_2: # %for.body
1871; SPE-NEXT:    #
1872; SPE-NEXT:    efscfsi 3, 29
1873; SPE-NEXT:    mr 4, 3
1874; SPE-NEXT:    bl fmaf
1875; SPE-NEXT:    addi 29, 29, 1
1876; SPE-NEXT:    cmplw 30, 29
1877; SPE-NEXT:    mr 5, 3
1878; SPE-NEXT:    bne 0, .LBB30_2
1879; SPE-NEXT:    b .LBB30_4
1880; SPE-NEXT:  .LBB30_3:
1881; SPE-NEXT:    # implicit-def: $r5
1882; SPE-NEXT:  .LBB30_4: # %for.cond.cleanup
1883; SPE-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
1884; SPE-NEXT:    mr 3, 5
1885; SPE-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
1886; SPE-NEXT:    lwz 30, 40(1) # 4-byte Folded Reload
1887; SPE-NEXT:    lwz 29, 36(1) # 4-byte Folded Reload
1888; SPE-NEXT:    lwz 0, 52(1)
1889; SPE-NEXT:    addi 1, 1, 48
1890; SPE-NEXT:    mtlr 0
1891; SPE-NEXT:    blr
1892;
1893; EFPU2-LABEL: test_fma:
1894; EFPU2:       # %bb.0: # %entry
1895; EFPU2-NEXT:    mflr 0
1896; EFPU2-NEXT:    stw 0, 4(1)
1897; EFPU2-NEXT:    stwu 1, -48(1)
1898; EFPU2-NEXT:    cmpwi 3, 1
1899; EFPU2-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
1900; EFPU2-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
1901; EFPU2-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
1902; EFPU2-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
1903; EFPU2-NEXT:    blt 0, .LBB30_3
1904; EFPU2-NEXT:  # %bb.1: # %for.body.preheader
1905; EFPU2-NEXT:    mr 30, 3
1906; EFPU2-NEXT:    li 29, 0
1907; EFPU2-NEXT:    # implicit-def: $r5
1908; EFPU2-NEXT:  .LBB30_2: # %for.body
1909; EFPU2-NEXT:    #
1910; EFPU2-NEXT:    efscfsi 3, 29
1911; EFPU2-NEXT:    mr 4, 3
1912; EFPU2-NEXT:    bl fmaf
1913; EFPU2-NEXT:    addi 29, 29, 1
1914; EFPU2-NEXT:    cmplw 30, 29
1915; EFPU2-NEXT:    mr 5, 3
1916; EFPU2-NEXT:    bne 0, .LBB30_2
1917; EFPU2-NEXT:    b .LBB30_4
1918; EFPU2-NEXT:  .LBB30_3:
1919; EFPU2-NEXT:    # implicit-def: $r5
1920; EFPU2-NEXT:  .LBB30_4: # %for.cond.cleanup
1921; EFPU2-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
1922; EFPU2-NEXT:    mr 3, 5
1923; EFPU2-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
1924; EFPU2-NEXT:    lwz 30, 40(1) # 4-byte Folded Reload
1925; EFPU2-NEXT:    lwz 29, 36(1) # 4-byte Folded Reload
1926; EFPU2-NEXT:    lwz 0, 52(1)
1927; EFPU2-NEXT:    addi 1, 1, 48
1928; EFPU2-NEXT:    mtlr 0
1929; EFPU2-NEXT:    blr
1930entry:
1931  %cmp8 = icmp sgt i32 %d, 0
1932  br i1 %cmp8, label %for.body, label %for.cond.cleanup
1933
1934for.cond.cleanup:                                 ; preds = %for.body, %entry
1935  %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]
1936  ret float %e.0.lcssa
1937
1938for.body:                                         ; preds = %for.body, %entry
1939  %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
1940  %e.09 = phi float [ %0, %for.body ], [ undef, %entry ]
1941  %conv = sitofp i32 %f.010 to float
1942  %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09)
1943  %inc = add nuw nsw i32 %f.010, 1
1944  %exitcond = icmp eq i32 %inc, %d
1945  br i1 %exitcond, label %for.cond.cleanup, label %for.body
1946}
1947
1948; Function Attrs: nounwind readnone speculatable willreturn
1949declare float @llvm.fma.f32(float, float, float) #1
1950
1951attributes #1 = { nounwind readnone speculatable willreturn }
1952
1953%struct.a = type { float, float }
1954
1955declare i32 @foo(double)
1956
1957define void @d(%struct.a* %e, %struct.a* %f) #0 {
1958; SPE-LABEL: d:
1959; SPE:       # %bb.0: # %entry
1960; SPE-NEXT:    mflr 0
1961; SPE-NEXT:    stw 0, 4(1)
1962; SPE-NEXT:    stwu 1, -64(1)
1963; SPE-NEXT:    lwz 4, 0(4)
1964; SPE-NEXT:    lwz 3, 0(3)
1965; SPE-NEXT:    stw 29, 52(1) # 4-byte Folded Spill
1966; SPE-NEXT:    evstdd 29, 24(1) # 8-byte Folded Spill
1967; SPE-NEXT:    efdcfs 29, 4
1968; SPE-NEXT:    stw 28, 48(1) # 4-byte Folded Spill
1969; SPE-NEXT:    mr 4, 29
1970; SPE-NEXT:    stw 30, 56(1) # 4-byte Folded Spill
1971; SPE-NEXT:    evstdd 28, 16(1) # 8-byte Folded Spill
1972; SPE-NEXT:    evstdd 30, 32(1) # 8-byte Folded Spill
1973; SPE-NEXT:    efdcfs 30, 3
1974; SPE-NEXT:    evmergehi 3, 29, 29
1975; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1976; SPE-NEXT:    bl foo
1977; SPE-NEXT:    mr 28, 3
1978; SPE-NEXT:    evmergehi 3, 30, 30
1979; SPE-NEXT:    mr 4, 30
1980; SPE-NEXT:    # kill: def $r3 killed $r3 killed $s3
1981; SPE-NEXT:    bl foo
1982; SPE-NEXT:    efdcfsi 3, 28
1983; SPE-NEXT:    evldd 30, 32(1) # 8-byte Folded Reload
1984; SPE-NEXT:    efdmul 3, 29, 3
1985; SPE-NEXT:    efscfd 3, 3
1986; SPE-NEXT:    evldd 29, 24(1) # 8-byte Folded Reload
1987; SPE-NEXT:    stw 3, 0(3)
1988; SPE-NEXT:    evldd 28, 16(1) # 8-byte Folded Reload
1989; SPE-NEXT:    lwz 30, 56(1) # 4-byte Folded Reload
1990; SPE-NEXT:    lwz 29, 52(1) # 4-byte Folded Reload
1991; SPE-NEXT:    lwz 28, 48(1) # 4-byte Folded Reload
1992; SPE-NEXT:    lwz 0, 68(1)
1993; SPE-NEXT:    addi 1, 1, 64
1994; SPE-NEXT:    mtlr 0
1995; SPE-NEXT:    blr
1996;
1997; EFPU2-LABEL: d:
1998; EFPU2:       # %bb.0: # %entry
1999; EFPU2-NEXT:    mflr 0
2000; EFPU2-NEXT:    stw 0, 4(1)
2001; EFPU2-NEXT:    stwu 1, -96(1)
2002; EFPU2-NEXT:    lwz 3, 0(3)
2003; EFPU2-NEXT:    stw 26, 72(1) # 4-byte Folded Spill
2004; EFPU2-NEXT:    stw 27, 76(1) # 4-byte Folded Spill
2005; EFPU2-NEXT:    stw 28, 80(1) # 4-byte Folded Spill
2006; EFPU2-NEXT:    stw 29, 84(1) # 4-byte Folded Spill
2007; EFPU2-NEXT:    stw 30, 88(1) # 4-byte Folded Spill
2008; EFPU2-NEXT:    evstdd 26, 16(1) # 8-byte Folded Spill
2009; EFPU2-NEXT:    evstdd 27, 24(1) # 8-byte Folded Spill
2010; EFPU2-NEXT:    evstdd 28, 32(1) # 8-byte Folded Spill
2011; EFPU2-NEXT:    evstdd 29, 40(1) # 8-byte Folded Spill
2012; EFPU2-NEXT:    evstdd 30, 48(1) # 8-byte Folded Spill
2013; EFPU2-NEXT:    mr 30, 4
2014; EFPU2-NEXT:    bl __extendsfdf2
2015; EFPU2-NEXT:    mr 28, 3
2016; EFPU2-NEXT:    lwz 3, 0(30)
2017; EFPU2-NEXT:    mr 29, 4
2018; EFPU2-NEXT:    bl __extendsfdf2
2019; EFPU2-NEXT:    mr 30, 4
2020; EFPU2-NEXT:    mr 27, 3
2021; EFPU2-NEXT:    bl foo
2022; EFPU2-NEXT:    mr 26, 3
2023; EFPU2-NEXT:    mr 3, 28
2024; EFPU2-NEXT:    mr 4, 29
2025; EFPU2-NEXT:    bl foo
2026; EFPU2-NEXT:    mr 3, 26
2027; EFPU2-NEXT:    bl __floatsidf
2028; EFPU2-NEXT:    mr 6, 4
2029; EFPU2-NEXT:    mr 5, 3
2030; EFPU2-NEXT:    mr 3, 27
2031; EFPU2-NEXT:    mr 4, 30
2032; EFPU2-NEXT:    bl __muldf3
2033; EFPU2-NEXT:    bl __truncdfsf2
2034; EFPU2-NEXT:    stw 3, 0(3)
2035; EFPU2-NEXT:    evldd 30, 48(1) # 8-byte Folded Reload
2036; EFPU2-NEXT:    evldd 29, 40(1) # 8-byte Folded Reload
2037; EFPU2-NEXT:    evldd 28, 32(1) # 8-byte Folded Reload
2038; EFPU2-NEXT:    evldd 27, 24(1) # 8-byte Folded Reload
2039; EFPU2-NEXT:    evldd 26, 16(1) # 8-byte Folded Reload
2040; EFPU2-NEXT:    lwz 30, 88(1) # 4-byte Folded Reload
2041; EFPU2-NEXT:    lwz 29, 84(1) # 4-byte Folded Reload
2042; EFPU2-NEXT:    lwz 28, 80(1) # 4-byte Folded Reload
2043; EFPU2-NEXT:    lwz 27, 76(1) # 4-byte Folded Reload
2044; EFPU2-NEXT:    lwz 26, 72(1) # 4-byte Folded Reload
2045; EFPU2-NEXT:    lwz 0, 100(1)
2046; EFPU2-NEXT:    addi 1, 1, 96
2047; EFPU2-NEXT:    mtlr 0
2048; EFPU2-NEXT:    blr
2049entry:
2050  %0 = getelementptr %struct.a, %struct.a* %f, i32 0, i32 0
2051  %1 = load float, float* undef
2052  %conv = fpext float %1 to double
2053  %2 = load float, float* %0
2054  %g = fpext float %2 to double
2055  %3 = call i32 @foo(double %g)
2056  %h = call i32 @foo(double %conv)
2057  %n = sitofp i32 %3 to double
2058  %k = fmul double %g, %n
2059  %l = fptrunc double %k to float
2060  store float %l, float* undef
2061  ret void
2062}
2063attributes #0 = { nounwind }
2064
2065;--- hwdouble.ll
2066; split into separate file because the efd* instructions are invalid on efpu2
2067define i32 @test_dasmconst(double %x) #0 {
2068; SPE-LABEL: test_dasmconst:
2069; SPE:       # %bb.0: # %entry
2070; SPE-NEXT:    stwu 1, -16(1)
2071; SPE-NEXT:    evmergelo 3, 3, 4
2072; SPE-NEXT:    evstdd 3, 8(1)
2073; SPE-NEXT:    #APP
2074; SPE-NEXT:    efdctsi 3, 3
2075; SPE-NEXT:    #NO_APP
2076; SPE-NEXT:    addi 1, 1, 16
2077; SPE-NEXT:    blr
2078entry:
2079  %x.addr = alloca double, align 8
2080  store double %x, double* %x.addr, align 8
2081  %0 = load double, double* %x.addr, align 8
2082  %1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
2083  ret i32 %1
2084}
2085attributes #0 = { nounwind }
2086