1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = local_unnamed_addr global i16 0, align 2
10
11; Function Attrs: norecurse nounwind readnone
12define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
13; CHECK-LABEL: test_llgtus:
14; CHECK:       # %bb.0: # %entry
15; CHECK-NEXT:    sub r3, r4, r3
16; CHECK-NEXT:    rldicl r3, r3, 1, 63
17; CHECK-NEXT:    blr
18entry:
19  %cmp = icmp ugt i16 %a, %b
20  %conv3 = zext i1 %cmp to i64
21  ret i64 %conv3
22}
23
24; Function Attrs: norecurse nounwind readnone
25define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
26; CHECK-LABEL: test_llgtus_sext:
27; CHECK:       # %bb.0: # %entry
28; CHECK-NEXT:    sub r3, r4, r3
29; CHECK-NEXT:    sradi r3, r3, 63
30; CHECK-NEXT:    blr
31entry:
32  %cmp = icmp ugt i16 %a, %b
33  %conv3 = sext i1 %cmp to i64
34  ret i64 %conv3
35}
36
37; Function Attrs: norecurse nounwind readnone
38define i64 @test_llgtus_z(i16 zeroext %a) {
39; CHECK-LABEL: test_llgtus_z:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    cntlzw r3, r3
42; CHECK-NEXT:    srwi r3, r3, 5
43; CHECK-NEXT:    xori r3, r3, 1
44; CHECK-NEXT:    blr
45entry:
46  %cmp = icmp ne i16 %a, 0
47  %conv2 = zext i1 %cmp to i64
48  ret i64 %conv2
49}
50
51; Function Attrs: norecurse nounwind readnone
52define i64 @test_llgtus_sext_z(i16 zeroext %a) {
53; CHECK-LABEL: test_llgtus_sext_z:
54; CHECK:       # %bb.0: # %entry
55; CHECK-NEXT:    cntlzw r3, r3
56; CHECK-NEXT:    srwi r3, r3, 5
57; CHECK-NEXT:    xori r3, r3, 1
58; CHECK-NEXT:    neg r3, r3
59; CHECK-NEXT:    blr
60entry:
61  %cmp = icmp ne i16 %a, 0
62  %conv2 = sext i1 %cmp to i64
63  ret i64 %conv2
64}
65
66; Function Attrs: norecurse nounwind
67define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
68; CHECK-LABEL: test_llgtus_store:
69; CHECK:       # %bb.0: # %entry
70; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
71; CHECK-NEXT:    sub r3, r4, r3
72; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
73; CHECK-NEXT:    rldicl r3, r3, 1, 63
74; CHECK-NEXT:    sth r3, 0(r5)
75; CHECK-NEXT:    blr
76entry:
77  %cmp = icmp ugt i16 %a, %b
78  %conv3 = zext i1 %cmp to i16
79  store i16 %conv3, i16* @glob, align 2
80  ret void
81}
82
83; Function Attrs: norecurse nounwind
84define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
85; CHECK-LABEL: test_llgtus_sext_store:
86; CHECK:       # %bb.0: # %entry
87; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
88; CHECK-NEXT:    sub r3, r4, r3
89; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
90; CHECK-NEXT:    sradi r3, r3, 63
91; CHECK-NEXT:    sth r3, 0(r5)
92; CHECK-NEXT:    blr
93entry:
94  %cmp = icmp ugt i16 %a, %b
95  %conv3 = sext i1 %cmp to i16
96  store i16 %conv3, i16* @glob, align 2
97  ret void
98}
99
100; Function Attrs: norecurse nounwind
101define void @test_llgtus_z_store(i16 zeroext %a) {
102; CHECK-LABEL: test_llgtus_z_store:
103; CHECK:       # %bb.0: # %entry
104; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
105; CHECK-NEXT:    cntlzw r3, r3
106; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
107; CHECK-NEXT:    srwi r3, r3, 5
108; CHECK-NEXT:    xori r3, r3, 1
109; CHECK-NEXT:    sth r3, 0(r4)
110; CHECK-NEXT:    blr
111entry:
112  %cmp = icmp ne i16 %a, 0
113  %conv2 = zext i1 %cmp to i16
114  store i16 %conv2, i16* @glob, align 2
115  ret void
116}
117
118; Function Attrs: norecurse nounwind
119define void @test_llgtus_sext_z_store(i16 zeroext %a) {
120; CHECK-LABEL: test_llgtus_sext_z_store:
121; CHECK:       # %bb.0: # %entry
122; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
123; CHECK-NEXT:    cntlzw r3, r3
124; CHECK-NEXT:    srwi r3, r3, 5
125; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
126; CHECK-NEXT:    xori r3, r3, 1
127; CHECK-NEXT:    neg r3, r3
128; CHECK-NEXT:    sth r3, 0(r4)
129; CHECK-NEXT:    blr
130entry:
131  %cmp = icmp ne i16 %a, 0
132  %conv2 = sext i1 %cmp to i16
133  store i16 %conv2, i16* @glob, align 2
134  ret void
135}
136
137