1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
3; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefixes=CHECK-NOVSX,CHECK-NOVSX-BE
4; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
5; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefixes=CHECK-NOVSX,CHECK-NOVSX-LE
6
7define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
8; CHECK-VSX-LABEL: test1:
9; CHECK-VSX:       # %bb.0: # %entry
10; CHECK-VSX-NEXT:    xvcmpeqsp vs0, v4, v5
11; CHECK-VSX-NEXT:    xxsel v2, v3, v2, vs0
12; CHECK-VSX-NEXT:    blr
13;
14; CHECK-NOVSX-LABEL: test1:
15; CHECK-NOVSX:       # %bb.0: # %entry
16; CHECK-NOVSX-NEXT:    vcmpeqfp v4, v4, v5
17; CHECK-NOVSX-NEXT:    vsel v2, v3, v2, v4
18; CHECK-NOVSX-NEXT:    blr
19entry:
20  %m = fcmp oeq <4 x float> %c, %d
21  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
22  ret <4 x float> %v
23}
24
25define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
26; CHECK-VSX-LABEL: test2:
27; CHECK-VSX:       # %bb.0: # %entry
28; CHECK-VSX-NEXT:    xvcmpeqdp v4, v4, v5
29; CHECK-VSX-NEXT:    xxsel v2, v3, v2, v4
30; CHECK-VSX-NEXT:    blr
31;
32; CHECK-NOVSX-LABEL: test2:
33; CHECK-NOVSX:       # %bb.0: # %entry
34; CHECK-NOVSX-NEXT:    fcmpu cr0, f5, f7
35; CHECK-NOVSX-NEXT:    beq cr0, .LBB1_2
36; CHECK-NOVSX-NEXT:  # %bb.1: # %entry
37; CHECK-NOVSX-NEXT:    fmr f1, f3
38; CHECK-NOVSX-NEXT:  .LBB1_2: # %entry
39; CHECK-NOVSX-NEXT:    fcmpu cr0, f6, f8
40; CHECK-NOVSX-NEXT:    beqlr cr0
41; CHECK-NOVSX-NEXT:  # %bb.3: # %entry
42; CHECK-NOVSX-NEXT:    fmr f2, f4
43; CHECK-NOVSX-NEXT:    blr
44entry:
45  %m = fcmp oeq <2 x double> %c, %d
46  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
47  ret <2 x double> %v
48}
49
50define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
51; CHECK-VSX-LABEL: test3:
52; CHECK-VSX:       # %bb.0: # %entry
53; CHECK-VSX-NEXT:    vcmpequb v4, v4, v5
54; CHECK-VSX-NEXT:    xxsel v2, v3, v2, v4
55; CHECK-VSX-NEXT:    blr
56;
57; CHECK-NOVSX-LABEL: test3:
58; CHECK-NOVSX:       # %bb.0: # %entry
59; CHECK-NOVSX-NEXT:    vcmpequb v4, v4, v5
60; CHECK-NOVSX-NEXT:    vsel v2, v3, v2, v4
61; CHECK-NOVSX-NEXT:    blr
62entry:
63  %m = icmp eq <16 x i8> %c, %d
64  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
65  ret <16 x i8> %v
66}
67
68define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
69; CHECK-VSX-LABEL: test4:
70; CHECK-VSX:       # %bb.0: # %entry
71; CHECK-VSX-NEXT:    vcmpequh v4, v4, v5
72; CHECK-VSX-NEXT:    xxsel v2, v3, v2, v4
73; CHECK-VSX-NEXT:    blr
74;
75; CHECK-NOVSX-LABEL: test4:
76; CHECK-NOVSX:       # %bb.0: # %entry
77; CHECK-NOVSX-NEXT:    vcmpequh v4, v4, v5
78; CHECK-NOVSX-NEXT:    vsel v2, v3, v2, v4
79; CHECK-NOVSX-NEXT:    blr
80entry:
81  %m = icmp eq <8 x i16> %c, %d
82  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
83  ret <8 x i16> %v
84}
85
86define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
87; CHECK-VSX-LABEL: test5:
88; CHECK-VSX:       # %bb.0: # %entry
89; CHECK-VSX-NEXT:    vcmpequw v4, v4, v5
90; CHECK-VSX-NEXT:    xxsel v2, v3, v2, v4
91; CHECK-VSX-NEXT:    blr
92;
93; CHECK-NOVSX-LABEL: test5:
94; CHECK-NOVSX:       # %bb.0: # %entry
95; CHECK-NOVSX-NEXT:    vcmpequw v4, v4, v5
96; CHECK-NOVSX-NEXT:    vsel v2, v3, v2, v4
97; CHECK-NOVSX-NEXT:    blr
98entry:
99  %m = icmp eq <4 x i32> %c, %d
100  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
101  ret <4 x i32> %v
102}
103
104define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
105; CHECK-VSX-LABEL: test6:
106; CHECK-VSX:       # %bb.0: # %entry
107; CHECK-VSX-NEXT:    vcmpequd v4, v4, v5
108; CHECK-VSX-NEXT:    xxsel v2, v3, v2, v4
109; CHECK-VSX-NEXT:    blr
110;
111; CHECK-NOVSX-LABEL: test6:
112; CHECK-NOVSX:       # %bb.0: # %entry
113; CHECK-NOVSX-NEXT:    vcmpequd v4, v4, v5
114; CHECK-NOVSX-NEXT:    vsel v2, v3, v2, v4
115; CHECK-NOVSX-NEXT:    blr
116entry:
117  %m = icmp eq <2 x i64> %c, %d
118  %v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
119  ret <2 x i64> %v
120}
121
122define <1 x i128> @test7(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c, <1 x i128> %d) {
123; CHECK-VSX-LABEL: test7:
124; CHECK-VSX:       # %bb.0: # %entry
125; CHECK-VSX-NEXT:    xxswapd vs0, v5
126; CHECK-VSX-NEXT:    xxswapd vs1, v4
127; CHECK-VSX-NEXT:    mfvsrd r3, v5
128; CHECK-VSX-NEXT:    mfvsrd r4, v4
129; CHECK-VSX-NEXT:    mffprd r5, f0
130; CHECK-VSX-NEXT:    mffprd r6, f1
131; CHECK-VSX-NEXT:    xor r3, r4, r3
132; CHECK-VSX-NEXT:    xor r4, r6, r5
133; CHECK-VSX-NEXT:    or. r3, r4, r3
134; CHECK-VSX-NEXT:    bclr 12, eq, 0
135; CHECK-VSX-NEXT:  # %bb.1: # %entry
136; CHECK-VSX-NEXT:    vmr v2, v3
137; CHECK-VSX-NEXT:    blr
138;
139; CHECK-NOVSX-BE-LABEL: test7:
140; CHECK-NOVSX-BE:       # %bb.0: # %entry
141; CHECK-NOVSX-BE-NEXT:    addi r3, r1, -16
142; CHECK-NOVSX-BE-NEXT:    addi r4, r1, -32
143; CHECK-NOVSX-BE-NEXT:    stvx v5, 0, r3
144; CHECK-NOVSX-BE-NEXT:    stvx v4, 0, r4
145; CHECK-NOVSX-BE-NEXT:    ld r3, -16(r1)
146; CHECK-NOVSX-BE-NEXT:    ld r4, -32(r1)
147; CHECK-NOVSX-BE-NEXT:    ld r5, -8(r1)
148; CHECK-NOVSX-BE-NEXT:    ld r6, -24(r1)
149; CHECK-NOVSX-BE-NEXT:    xor r3, r4, r3
150; CHECK-NOVSX-BE-NEXT:    xor r4, r6, r5
151; CHECK-NOVSX-BE-NEXT:    or. r3, r4, r3
152; CHECK-NOVSX-BE-NEXT:    bclr 12, eq, 0
153; CHECK-NOVSX-BE-NEXT:  # %bb.1: # %entry
154; CHECK-NOVSX-BE-NEXT:    vmr v2, v3
155; CHECK-NOVSX-BE-NEXT:    blr
156;
157; CHECK-NOVSX-LE-LABEL: test7:
158; CHECK-NOVSX-LE:       # %bb.0: # %entry
159; CHECK-NOVSX-LE-NEXT:    addi r3, r1, -16
160; CHECK-NOVSX-LE-NEXT:    addi r4, r1, -32
161; CHECK-NOVSX-LE-NEXT:    stvx v5, 0, r3
162; CHECK-NOVSX-LE-NEXT:    stvx v4, 0, r4
163; CHECK-NOVSX-LE-NEXT:    ld r3, -8(r1)
164; CHECK-NOVSX-LE-NEXT:    ld r4, -24(r1)
165; CHECK-NOVSX-LE-NEXT:    ld r5, -16(r1)
166; CHECK-NOVSX-LE-NEXT:    ld r6, -32(r1)
167; CHECK-NOVSX-LE-NEXT:    xor r3, r4, r3
168; CHECK-NOVSX-LE-NEXT:    xor r4, r6, r5
169; CHECK-NOVSX-LE-NEXT:    or. r3, r4, r3
170; CHECK-NOVSX-LE-NEXT:    bclr 12, eq, 0
171; CHECK-NOVSX-LE-NEXT:  # %bb.1: # %entry
172; CHECK-NOVSX-LE-NEXT:    vmr v2, v3
173; CHECK-NOVSX-LE-NEXT:    blr
174entry:
175  %m = icmp eq <1 x i128> %c, %d
176  %v = select <1 x i1> %m, <1 x i128> %a, <1 x i128> %b
177  ret <1 x i128> %v
178}
179