1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
3# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m4 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM4
4# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m5 -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM5
5
6sdiv	w0, w1, w2
7udiv	x1, x2, x3
8
9mul	w2, w3, w4
10msub	x3, x4, x5, x6
11
12smull	x4, w5, w6
13umulh	x5, x6, x7
14
15# ALL:      Iterations:        100
16# ALL-NEXT: Instructions:      600
17
18# EM3-NEXT: Total Cycles:      3305
19# EM4-NEXT: Total Cycles:      3303
20# EM5-NEXT: Total Cycles:      2603
21
22# ALL-NEXT: Total uOps:        600
23
24# ALL:      Dispatch Width:    6
25
26# EM3-NEXT: uOps Per Cycle:    0.18
27# EM3-NEXT: IPC:               0.18
28# EM3-NEXT: Block RThroughput: 33.0
29
30# EM4-NEXT: uOps Per Cycle:    0.18
31# EM4-NEXT: IPC:               0.18
32# EM4-NEXT: Block RThroughput: 33.0
33
34# EM5-NEXT: uOps Per Cycle:    0.23
35# EM5-NEXT: IPC:               0.23
36# EM5-NEXT: Block RThroughput: 26.0
37
38# ALL:      Instruction Info:
39# ALL-NEXT: [1]: #uOps
40# ALL-NEXT: [2]: Latency
41# ALL-NEXT: [3]: RThroughput
42# ALL-NEXT: [4]: MayLoad
43# ALL-NEXT: [5]: MayStore
44# ALL-NEXT: [6]: HasSideEffects (U)
45
46# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
47
48# EM3-NEXT:  1      12    12.00                       sdiv	w0, w1, w2
49# EM3-NEXT:  1      21    21.00                       udiv	x1, x2, x3
50# EM3-NEXT:  1      3     0.50                        mul	w2, w3, w4
51# EM3-NEXT:  1      4     1.00                        msub	x3, x4, x5, x6
52# EM3-NEXT:  1      3     0.50                        smull	x4, w5, w6
53# EM3-NEXT:  1      4     1.00                        umulh	x5, x6, x7
54
55# EM4-NEXT:  1      12    12.00                       sdiv	w0, w1, w2
56# EM4-NEXT:  1      21    21.00                       udiv	x1, x2, x3
57# EM4-NEXT:  1      3     0.50                        mul	w2, w3, w4
58# EM4-NEXT:  1      4     1.00                        msub	x3, x4, x5, x6
59# EM4-NEXT:  1      3     0.50                        smull	x4, w5, w6
60# EM4-NEXT:  1      4     1.00                        umulh	x5, x6, x7
61
62# EM5-NEXT:  1      10    10.00                       sdiv	w0, w1, w2
63# EM5-NEXT:  1      16    16.00                       udiv	x1, x2, x3
64# EM5-NEXT:  1      2     0.50                        mul	w2, w3, w4
65# EM5-NEXT:  1      3     1.00                        msub	x3, x4, x5, x6
66# EM5-NEXT:  1      2     0.50                        smull	x4, w5, w6
67# EM5-NEXT:  1      3     1.00                        umulh	x5, x6, x7
68