1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces which should be 10// implemented by each target which is using a TableGen based code generator. 11// 12//===----------------------------------------------------------------------===// 13 14// Include all information about LLVM intrinsics. 15include "llvm/IR/Intrinsics.td" 16 17//===----------------------------------------------------------------------===// 18// Register file description - These classes are used to fill in the target 19// description classes. 20 21class HwMode<string FS> { 22 // A string representing subtarget features that turn on this HW mode. 23 // For example, "+feat1,-feat2" will indicate that the mode is active 24 // when "feat1" is enabled and "feat2" is disabled at the same time. 25 // Any other features are not checked. 26 // When multiple modes are used, they should be mutually exclusive, 27 // otherwise the results are unpredictable. 28 string Features = FS; 29} 30 31// A special mode recognized by tablegen. This mode is considered active 32// when no other mode is active. For targets that do not use specific hw 33// modes, this is the only mode. 34def DefaultMode : HwMode<"">; 35 36// A class used to associate objects with HW modes. It is only intended to 37// be used as a base class, where the derived class should contain a member 38// "Objects", which is a list of the same length as the list of modes. 39// The n-th element on the Objects list will be associated with the n-th 40// element on the Modes list. 41class HwModeSelect<list<HwMode> Ms> { 42 list<HwMode> Modes = Ms; 43} 44 45// A common class that implements a counterpart of ValueType, which is 46// dependent on a HW mode. This class inherits from ValueType itself, 47// which makes it possible to use objects of this class where ValueType 48// objects could be used. This is specifically applicable to selection 49// patterns. 50class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 51 : HwModeSelect<Ms>, ValueType<0, 0> { 52 // The length of this list must be the same as the length of Ms. 53 list<ValueType> Objects = Ts; 54} 55 56// A class representing the register size, spill size and spill alignment 57// in bits of a register. 58class RegInfo<int RS, int SS, int SA> { 59 int RegSize = RS; // Register size in bits. 60 int SpillSize = SS; // Spill slot size in bits. 61 int SpillAlignment = SA; // Spill slot alignment in bits. 62} 63 64// The register size/alignment information, parameterized by a HW mode. 65class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 66 : HwModeSelect<Ms> { 67 // The length of this list must be the same as the length of Ms. 68 list<RegInfo> Objects = Ts; 69} 70 71// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 72class SubRegIndex<int size, int offset = 0> { 73 string Namespace = ""; 74 75 // Size - Size (in bits) of the sub-registers represented by this index. 76 int Size = size; 77 78 // Offset - Offset of the first bit that is part of this sub-register index. 79 // Set it to -1 if the same index is used to represent sub-registers that can 80 // be at different offsets (for example when using an index to access an 81 // element in a register tuple). 82 int Offset = offset; 83 84 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 85 // This indicates that this SubRegIndex is the result of composing A and B. 86 // See ComposedSubRegIndex. 87 list<SubRegIndex> ComposedOf = []; 88 89 // CoveringSubRegIndices - A list of two or more sub-register indexes that 90 // cover this sub-register. 91 // 92 // This field should normally be left blank as TableGen can infer it. 93 // 94 // TableGen automatically detects sub-registers that straddle the registers 95 // in the SubRegs field of a Register definition. For example: 96 // 97 // Q0 = dsub_0 -> D0, dsub_1 -> D1 98 // Q1 = dsub_0 -> D2, dsub_1 -> D3 99 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 100 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 101 // 102 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 103 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 104 // CoveringSubRegIndices = [dsub_1, dsub_2]. 105 list<SubRegIndex> CoveringSubRegIndices = []; 106} 107 108// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 109// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 110class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 111 : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1, 112 !eq(B.Offset, -1): -1, 113 true: !add(A.Offset, B.Offset))> { 114 // See SubRegIndex. 115 let ComposedOf = [A, B]; 116} 117 118// RegAltNameIndex - The alternate name set to use for register operands of 119// this register class when printing. 120class RegAltNameIndex { 121 string Namespace = ""; 122 123 // A set to be used if the name for a register is not defined in this set. 124 // This allows creating name sets with only a few alternative names. 125 RegAltNameIndex FallbackRegAltNameIndex = ?; 126} 127def NoRegAltName : RegAltNameIndex; 128 129// Register - You should define one instance of this class for each register 130// in the target machine. String n will become the "name" of the register. 131class Register<string n, list<string> altNames = []> { 132 string Namespace = ""; 133 string AsmName = n; 134 list<string> AltNames = altNames; 135 136 // Aliases - A list of registers that this register overlaps with. A read or 137 // modification of this register can potentially read or modify the aliased 138 // registers. 139 list<Register> Aliases = []; 140 141 // SubRegs - A list of registers that are parts of this register. Note these 142 // are "immediate" sub-registers and the registers within the list do not 143 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 144 // not [AX, AH, AL]. 145 list<Register> SubRegs = []; 146 147 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 148 // to address it. Sub-sub-register indices are automatically inherited from 149 // SubRegs. 150 list<SubRegIndex> SubRegIndices = []; 151 152 // RegAltNameIndices - The alternate name indices which are valid for this 153 // register. 154 list<RegAltNameIndex> RegAltNameIndices = []; 155 156 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 157 // These values can be determined by locating the <target>.h file in the 158 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 159 // order of these names correspond to the enumeration used by gcc. A value of 160 // -1 indicates that the gcc number is undefined and -2 that register number 161 // is invalid for this mode/flavour. 162 list<int> DwarfNumbers = []; 163 164 // CostPerUse - Additional cost of instructions using this register compared 165 // to other registers in its class. The register allocator will try to 166 // minimize the number of instructions using a register with a CostPerUse. 167 // This is used by the ARC target, by the ARM Thumb and x86-64 targets, where 168 // some registers require larger instruction encodings, by the RISC-V target, 169 // where some registers preclude using some C instructions. By making it a 170 // list, targets can have multiple cost models associated with each register 171 // and can choose one specific cost model per Machine Function by overriding 172 // TargetRegisterInfo::getRegisterCostTableIndex. Every target register will 173 // finally have an equal number of cost values which is the max of costPerUse 174 // values specified. Any mismatch in the cost values for a register will be 175 // filled with zeros. Restricted the cost type to uint8_t in the 176 // generated table. It will considerably reduce the table size. 177 list<int> CostPerUse = [0]; 178 179 // CoveredBySubRegs - When this bit is set, the value of this register is 180 // completely determined by the value of its sub-registers. For example, the 181 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 182 // covered by its sub-register AX. 183 bit CoveredBySubRegs = false; 184 185 // HWEncoding - The target specific hardware encoding for this register. 186 bits<16> HWEncoding = 0; 187 188 bit isArtificial = false; 189} 190 191// RegisterWithSubRegs - This can be used to define instances of Register which 192// need to specify sub-registers. 193// List "subregs" specifies which registers are sub-registers to this one. This 194// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 195// This allows the code generator to be careful not to put two values with 196// overlapping live ranges into registers which alias. 197class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 198 let SubRegs = subregs; 199} 200 201// DAGOperand - An empty base class that unifies RegisterClass's and other forms 202// of Operand's that are legal as type qualifiers in DAG patterns. This should 203// only ever be used for defining multiclasses that are polymorphic over both 204// RegisterClass's and other Operand's. 205class DAGOperand { 206 string OperandNamespace = "MCOI"; 207 string DecoderMethod = ""; 208} 209 210// RegisterClass - Now that all of the registers are defined, and aliases 211// between registers are defined, specify which registers belong to which 212// register classes. This also defines the default allocation order of 213// registers by register allocators. 214// 215class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 216 dag regList, RegAltNameIndex idx = NoRegAltName> 217 : DAGOperand { 218 string Namespace = namespace; 219 220 // The register size/alignment information, parameterized by a HW mode. 221 RegInfoByHwMode RegInfos; 222 223 // RegType - Specify the list ValueType of the registers in this register 224 // class. Note that all registers in a register class must have the same 225 // ValueTypes. This is a list because some targets permit storing different 226 // types in same register, for example vector values with 128-bit total size, 227 // but different count/size of items, like SSE on x86. 228 // 229 list<ValueType> RegTypes = regTypes; 230 231 // Size - Specify the spill size in bits of the registers. A default value of 232 // zero lets tablegen pick an appropriate size. 233 int Size = 0; 234 235 // Alignment - Specify the alignment required of the registers when they are 236 // stored or loaded to memory. 237 // 238 int Alignment = alignment; 239 240 // CopyCost - This value is used to specify the cost of copying a value 241 // between two registers in this register class. The default value is one 242 // meaning it takes a single instruction to perform the copying. A negative 243 // value means copying is extremely expensive or impossible. 244 int CopyCost = 1; 245 246 // MemberList - Specify which registers are in this class. If the 247 // allocation_order_* method are not specified, this also defines the order of 248 // allocation used by the register allocator. 249 // 250 dag MemberList = regList; 251 252 // AltNameIndex - The alternate register name to use when printing operands 253 // of this register class. Every register in the register class must have 254 // a valid alternate name for the given index. 255 RegAltNameIndex altNameIndex = idx; 256 257 // isAllocatable - Specify that the register class can be used for virtual 258 // registers and register allocation. Some register classes are only used to 259 // model instruction operand constraints, and should have isAllocatable = 0. 260 bit isAllocatable = true; 261 262 // AltOrders - List of alternative allocation orders. The default order is 263 // MemberList itself, and that is good enough for most targets since the 264 // register allocators automatically remove reserved registers and move 265 // callee-saved registers to the end. 266 list<dag> AltOrders = []; 267 268 // AltOrderSelect - The body of a function that selects the allocation order 269 // to use in a given machine function. The code will be inserted in a 270 // function like this: 271 // 272 // static inline unsigned f(const MachineFunction &MF) { ... } 273 // 274 // The function should return 0 to select the default order defined by 275 // MemberList, 1 to select the first AltOrders entry and so on. 276 code AltOrderSelect = [{}]; 277 278 // Specify allocation priority for register allocators using a greedy 279 // heuristic. Classes with higher priority values are assigned first. This is 280 // useful as it is sometimes beneficial to assign registers to highly 281 // constrained classes first. The value has to be in the range [0,63]. 282 int AllocationPriority = 0; 283 284 // Generate register pressure set for this register class and any class 285 // synthesized from it. Set to 0 to inhibit unneeded pressure sets. 286 bit GeneratePressureSet = true; 287 288 // Weight override for register pressure calculation. This is the value 289 // TargetRegisterClass::getRegClassWeight() will return. The weight is in 290 // units of pressure for this register class. If unset tablegen will 291 // calculate a weight based on a number of register units in this register 292 // class registers. The weight is per register. 293 int Weight = ?; 294 295 // The diagnostic type to present when referencing this operand in a match 296 // failure error message. If this is empty, the default Match_InvalidOperand 297 // diagnostic type will be used. If this is "<name>", a Match_<name> enum 298 // value will be generated and used for this operand type. The target 299 // assembly parser is responsible for converting this into a user-facing 300 // diagnostic message. 301 string DiagnosticType = ""; 302 303 // A diagnostic message to emit when an invalid value is provided for this 304 // register class when it is being used an an assembly operand. If this is 305 // non-empty, an anonymous diagnostic type enum value will be generated, and 306 // the assembly matcher will provide a function to map from diagnostic types 307 // to message strings. 308 string DiagnosticString = ""; 309} 310 311// The memberList in a RegisterClass is a dag of set operations. TableGen 312// evaluates these set operations and expand them into register lists. These 313// are the most common operation, see test/TableGen/SetTheory.td for more 314// examples of what is possible: 315// 316// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 317// register class, or a sub-expression. This is also the way to simply list 318// registers. 319// 320// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 321// 322// (and GPR, CSR) - Set intersection. All registers from the first set that are 323// also in the second set. 324// 325// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 326// numbered registers. Takes an optional 4th operand which is a stride to use 327// when generating the sequence. 328// 329// (shl GPR, 4) - Remove the first N elements. 330// 331// (trunc GPR, 4) - Truncate after the first N elements. 332// 333// (rotl GPR, 1) - Rotate N places to the left. 334// 335// (rotr GPR, 1) - Rotate N places to the right. 336// 337// (decimate GPR, 2) - Pick every N'th element, starting with the first. 338// 339// (interleave A, B, ...) - Interleave the elements from each argument list. 340// 341// All of these operators work on ordered sets, not lists. That means 342// duplicates are removed from sub-expressions. 343 344// Set operators. The rest is defined in TargetSelectionDAG.td. 345def sequence; 346def decimate; 347def interleave; 348 349// RegisterTuples - Automatically generate super-registers by forming tuples of 350// sub-registers. This is useful for modeling register sequence constraints 351// with pseudo-registers that are larger than the architectural registers. 352// 353// The sub-register lists are zipped together: 354// 355// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 356// 357// Generates the same registers as: 358// 359// let SubRegIndices = [sube, subo] in { 360// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 361// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 362// } 363// 364// The generated pseudo-registers inherit super-classes and fields from their 365// first sub-register. Most fields from the Register class are inferred, and 366// the AsmName and Dwarf numbers are cleared. 367// 368// RegisterTuples instances can be used in other set operations to form 369// register classes and so on. This is the only way of using the generated 370// registers. 371// 372// RegNames may be specified to supply asm names for the generated tuples. 373// If used must have the same size as the list of produced registers. 374class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs, 375 list<string> RegNames = []> { 376 // SubRegs - N lists of registers to be zipped up. Super-registers are 377 // synthesized from the first element of each SubRegs list, the second 378 // element and so on. 379 list<dag> SubRegs = Regs; 380 381 // SubRegIndices - N SubRegIndex instances. This provides the names of the 382 // sub-registers in the synthesized super-registers. 383 list<SubRegIndex> SubRegIndices = Indices; 384 385 // List of asm names for the generated tuple registers. 386 list<string> RegAsmNames = RegNames; 387} 388 389 390//===----------------------------------------------------------------------===// 391// DwarfRegNum - This class provides a mapping of the llvm register enumeration 392// to the register numbering used by gcc and gdb. These values are used by a 393// debug information writer to describe where values may be located during 394// execution. 395class DwarfRegNum<list<int> Numbers> { 396 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 397 // These values can be determined by locating the <target>.h file in the 398 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 399 // order of these names correspond to the enumeration used by gcc. A value of 400 // -1 indicates that the gcc number is undefined and -2 that register number 401 // is invalid for this mode/flavour. 402 list<int> DwarfNumbers = Numbers; 403} 404 405// DwarfRegAlias - This class declares that a given register uses the same dwarf 406// numbers as another one. This is useful for making it clear that the two 407// registers do have the same number. It also lets us build a mapping 408// from dwarf register number to llvm register. 409class DwarfRegAlias<Register reg> { 410 Register DwarfAlias = reg; 411} 412 413//===----------------------------------------------------------------------===// 414// Pull in the common support for MCPredicate (portable scheduling predicates). 415// 416include "llvm/Target/TargetInstrPredicate.td" 417 418//===----------------------------------------------------------------------===// 419// Pull in the common support for scheduling 420// 421include "llvm/Target/TargetSchedule.td" 422 423class Predicate; // Forward def 424 425class InstructionEncoding { 426 // Size of encoded instruction. 427 int Size; 428 429 // The "namespace" in which this instruction exists, on targets like ARM 430 // which multiple ISA namespaces exist. 431 string DecoderNamespace = ""; 432 433 // List of predicates which will be turned into isel matching code. 434 list<Predicate> Predicates = []; 435 436 string DecoderMethod = ""; 437 438 // Is the instruction decoder method able to completely determine if the 439 // given instruction is valid or not. If the TableGen definition of the 440 // instruction specifies bitpattern A??B where A and B are static bits, the 441 // hasCompleteDecoder flag says whether the decoder method fully handles the 442 // ?? space, i.e. if it is a final arbiter for the instruction validity. 443 // If not then the decoder attempts to continue decoding when the decoder 444 // method fails. 445 // 446 // This allows to handle situations where the encoding is not fully 447 // orthogonal. Example: 448 // * InstA with bitpattern 0b0000????, 449 // * InstB with bitpattern 0b000000?? but the associated decoder method 450 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 451 // 452 // The decoder tries to decode a bitpattern that matches both InstA and 453 // InstB bitpatterns first as InstB (because it is the most specific 454 // encoding). In the default case (hasCompleteDecoder = 1), when 455 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 456 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 457 // DecodeInstB() is not able to determine if all possible values of ?? are 458 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 459 // decode the bitpattern as InstA too. 460 bit hasCompleteDecoder = true; 461} 462 463// Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies 464// an EncodingByHwMode, its Inst and Size members are ignored and Ts are used 465// to encode and decode based on HwMode. 466class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []> 467 : HwModeSelect<Ms> { 468 // The length of this list must be the same as the length of Ms. 469 list<InstructionEncoding> Objects = Ts; 470} 471 472//===----------------------------------------------------------------------===// 473// Instruction set description - These classes correspond to the C++ classes in 474// the Target/TargetInstrInfo.h file. 475// 476class Instruction : InstructionEncoding { 477 string Namespace = ""; 478 479 dag OutOperandList; // An dag containing the MI def operand list. 480 dag InOperandList; // An dag containing the MI use operand list. 481 string AsmString = ""; // The .s format to print the instruction with. 482 483 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty, 484 // the Inst member of this Instruction is ignored. 485 EncodingByHwMode EncodingInfos; 486 487 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 488 // otherwise, uninitialized. 489 list<dag> Pattern; 490 491 // The follow state will eventually be inferred automatically from the 492 // instruction pattern. 493 494 list<Register> Uses = []; // Default to using no non-operand registers 495 list<Register> Defs = []; // Default to modifying no non-operand registers 496 497 // Predicates - List of predicates which will be turned into isel matching 498 // code. 499 list<Predicate> Predicates = []; 500 501 // Size - Size of encoded instruction, or zero if the size cannot be determined 502 // from the opcode. 503 int Size = 0; 504 505 // Code size, for instruction selection. 506 // FIXME: What does this actually mean? 507 int CodeSize = 0; 508 509 // Added complexity passed onto matching pattern. 510 int AddedComplexity = 0; 511 512 // Indicates if this is a pre-isel opcode that should be 513 // legalized/regbankselected/selected. 514 bit isPreISelOpcode = false; 515 516 // These bits capture information about the high-level semantics of the 517 // instruction. 518 bit isReturn = false; // Is this instruction a return instruction? 519 bit isBranch = false; // Is this instruction a branch instruction? 520 bit isEHScopeReturn = false; // Does this instruction end an EH scope? 521 bit isIndirectBranch = false; // Is this instruction an indirect branch? 522 bit isCompare = false; // Is this instruction a comparison instruction? 523 bit isMoveImm = false; // Is this instruction a move immediate instruction? 524 bit isMoveReg = false; // Is this instruction a move register instruction? 525 bit isBitcast = false; // Is this instruction a bitcast instruction? 526 bit isSelect = false; // Is this instruction a select instruction? 527 bit isBarrier = false; // Can control flow fall through this instruction? 528 bit isCall = false; // Is this instruction a call instruction? 529 bit isAdd = false; // Is this instruction an add instruction? 530 bit isTrap = false; // Is this instruction a trap instruction? 531 bit canFoldAsLoad = false; // Can this be folded as a simple memory operand? 532 bit mayLoad = ?; // Is it possible for this inst to read memory? 533 bit mayStore = ?; // Is it possible for this inst to write memory? 534 bit mayRaiseFPException = false; // Can this raise a floating-point exception? 535 bit isConvertibleToThreeAddress = false; // Can this 2-addr instruction promote? 536 bit isCommutable = false; // Is this 3 operand instruction commutable? 537 bit isTerminator = false; // Is this part of the terminator for a basic block? 538 bit isReMaterializable = false; // Is this instruction re-materializable? 539 bit isPredicable = false; // 1 means this instruction is predicable 540 // even if it does not have any operand 541 // tablegen can identify as a predicate 542 bit isUnpredicable = false; // 1 means this instruction is not predicable 543 // even if it _does_ have a predicate operand 544 bit hasDelaySlot = false; // Does this instruction have an delay slot? 545 bit usesCustomInserter = false; // Pseudo instr needing special help. 546 bit hasPostISelHook = false; // To be *adjusted* after isel by target hook. 547 bit hasCtrlDep = false; // Does this instruction r/w ctrl-flow chains? 548 bit isNotDuplicable = false; // Is it unsafe to duplicate this instruction? 549 bit isConvergent = false; // Is this instruction convergent? 550 bit isAuthenticated = false; // Does this instruction authenticate a pointer? 551 bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction. 552 bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement? 553 bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement? 554 bit isRegSequence = false; // Is this instruction a kind of reg sequence? 555 // If so, make sure to override 556 // TargetInstrInfo::getRegSequenceLikeInputs. 557 bit isPseudo = false; // Is this instruction a pseudo-instruction? 558 // If so, won't have encoding information for 559 // the [MC]CodeEmitter stuff. 560 bit isExtractSubreg = false; // Is this instruction a kind of extract subreg? 561 // If so, make sure to override 562 // TargetInstrInfo::getExtractSubregLikeInputs. 563 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg? 564 // If so, make sure to override 565 // TargetInstrInfo::getInsertSubregLikeInputs. 566 bit variadicOpsAreDefs = false; // Are variadic operands definitions? 567 568 // Does the instruction have side effects that are not captured by any 569 // operands of the instruction or other flags? 570 bit hasSideEffects = ?; 571 572 // Is this instruction a "real" instruction (with a distinct machine 573 // encoding), or is it a pseudo instruction used for codegen modeling 574 // purposes. 575 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 576 // instructions can (and often do) still have encoding information 577 // associated with them. Once we've migrated all of them over to true 578 // pseudo-instructions that are lowered to real instructions prior to 579 // the printer/emitter, we can remove this attribute and just use isPseudo. 580 // 581 // The intended use is: 582 // isPseudo: Does not have encoding information and should be expanded, 583 // at the latest, during lowering to MCInst. 584 // 585 // isCodeGenOnly: Does have encoding information and can go through to the 586 // CodeEmitter unchanged, but duplicates a canonical instruction 587 // definition's encoding and should be ignored when constructing the 588 // assembler match tables. 589 bit isCodeGenOnly = false; 590 591 // Is this instruction a pseudo instruction for use by the assembler parser. 592 bit isAsmParserOnly = false; 593 594 // This instruction is not expected to be queried for scheduling latencies 595 // and therefore needs no scheduling information even for a complete 596 // scheduling model. 597 bit hasNoSchedulingInfo = false; 598 599 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 600 601 // Scheduling information from TargetSchedule.td. 602 list<SchedReadWrite> SchedRW; 603 604 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 605 606 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 607 /// be encoded into the output machineinstr. 608 string DisableEncoding = ""; 609 610 string PostEncoderMethod = ""; 611 612 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 613 bits<64> TSFlags = 0; 614 615 ///@name Assembler Parser Support 616 ///@{ 617 618 string AsmMatchConverter = ""; 619 620 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 621 /// two-operand matcher inst-alias for a three operand instruction. 622 /// For example, the arm instruction "add r3, r3, r5" can be written 623 /// as "add r3, r5". The constraint is of the same form as a tied-operand 624 /// constraint. For example, "$Rn = $Rd". 625 string TwoOperandAliasConstraint = ""; 626 627 /// Assembler variant name to use for this instruction. If specified then 628 /// instruction will be presented only in MatchTable for this variant. If 629 /// not specified then assembler variants will be determined based on 630 /// AsmString 631 string AsmVariantName = ""; 632 633 ///@} 634 635 /// UseNamedOperandTable - If set, the operand indices of this instruction 636 /// can be queried via the getNamedOperandIdx() function which is generated 637 /// by TableGen. 638 bit UseNamedOperandTable = false; 639 640 /// Should generate helper functions that help you to map a logical operand's 641 /// index to the underlying MIOperand's index. 642 /// In most architectures logical operand indicies are equal to 643 /// MIOperand indicies, but for some CISC architectures, a logical operand 644 /// might be consist of multiple MIOperand (e.g. a logical operand that 645 /// uses complex address mode). 646 bit UseLogicalOperandMappings = false; 647 648 /// Should FastISel ignore this instruction. For certain ISAs, they have 649 /// instructions which map to the same ISD Opcode, value type operands and 650 /// instruction selection predicates. FastISel cannot handle such cases, but 651 /// SelectionDAG can. 652 bit FastISelShouldIgnore = false; 653} 654 655/// Defines an additional encoding that disassembles to the given instruction 656/// Like Instruction, the Inst and SoftFail fields are omitted to allow targets 657// to specify their size. 658class AdditionalEncoding<Instruction I> : InstructionEncoding { 659 Instruction AliasOf = I; 660} 661 662/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 663/// Which instruction it expands to and how the operands map from the 664/// pseudo. 665class PseudoInstExpansion<dag Result> { 666 dag ResultInst = Result; // The instruction to generate. 667 bit isPseudo = true; 668} 669 670/// Predicates - These are extra conditionals which are turned into instruction 671/// selector matching code. Currently each predicate is just a string. 672class Predicate<string cond> { 673 string CondString = cond; 674 675 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 676 /// matcher, this is true. Targets should set this by inheriting their 677 /// feature from the AssemblerPredicate class in addition to Predicate. 678 bit AssemblerMatcherPredicate = false; 679 680 /// AssemblerCondDag - Set of subtarget features being tested used 681 /// as alternative condition string used for assembler matcher. Must be used 682 /// with (all_of) to indicate that all features must be present, or (any_of) 683 /// to indicate that at least one must be. The required lack of presence of 684 /// a feature can be tested using a (not) node including the feature. 685 /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0". 686 /// "(all_of (not ModeThumb))" is translated to 687 /// "(Bits & ModeThumb) == 0". 688 /// "(all_of ModeThumb, FeatureThumb2)" is translated to 689 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 690 /// "(any_of ModeTumb, FeatureThumb2)" is translated to 691 /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0". 692 /// all_of and any_of cannot be combined in a single dag, instead multiple 693 /// predicates can be placed onto Instruction definitions. 694 dag AssemblerCondDag; 695 696 /// PredicateName - User-level name to use for the predicate. Mainly for use 697 /// in diagnostics such as missing feature errors in the asm matcher. 698 string PredicateName = ""; 699 700 /// Setting this to '1' indicates that the predicate must be recomputed on 701 /// every function change. Most predicates can leave this at '0'. 702 /// 703 /// Ignored by SelectionDAG, it always recomputes the predicate on every use. 704 bit RecomputePerFunction = false; 705} 706 707/// NoHonorSignDependentRounding - This predicate is true if support for 708/// sign-dependent-rounding is not enabled. 709def NoHonorSignDependentRounding 710 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 711 712class Requires<list<Predicate> preds> { 713 list<Predicate> Predicates = preds; 714} 715 716/// ops definition - This is just a simple marker used to identify the operand 717/// list for an instruction. outs and ins are identical both syntactically and 718/// semantically; they are used to define def operands and use operands to 719/// improve readability. This should be used like this: 720/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 721def ops; 722def outs; 723def ins; 724 725/// variable_ops definition - Mark this instruction as taking a variable number 726/// of operands. 727def variable_ops; 728 729 730/// PointerLikeRegClass - Values that are designed to have pointer width are 731/// derived from this. TableGen treats the register class as having a symbolic 732/// type that it doesn't know, and resolves the actual regclass to use by using 733/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 734class PointerLikeRegClass<int Kind> { 735 int RegClassKind = Kind; 736} 737 738 739/// ptr_rc definition - Mark this operand as being a pointer value whose 740/// register class is resolved dynamically via a callback to TargetInstrInfo. 741/// FIXME: We should probably change this to a class which contain a list of 742/// flags. But currently we have but one flag. 743def ptr_rc : PointerLikeRegClass<0>; 744 745/// unknown definition - Mark this operand as being of unknown type, causing 746/// it to be resolved by inference in the context it is used. 747class unknown_class; 748def unknown : unknown_class; 749 750/// AsmOperandClass - Representation for the kinds of operands which the target 751/// specific parser can create and the assembly matcher may need to distinguish. 752/// 753/// Operand classes are used to define the order in which instructions are 754/// matched, to ensure that the instruction which gets matched for any 755/// particular list of operands is deterministic. 756/// 757/// The target specific parser must be able to classify a parsed operand into a 758/// unique class which does not partially overlap with any other classes. It can 759/// match a subset of some other class, in which case the super class field 760/// should be defined. 761class AsmOperandClass { 762 /// The name to use for this class, which should be usable as an enum value. 763 string Name = ?; 764 765 /// The super classes of this operand. 766 list<AsmOperandClass> SuperClasses = []; 767 768 /// The name of the method on the target specific operand to call to test 769 /// whether the operand is an instance of this class. If not set, this will 770 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 771 /// signature should be: 772 /// bool isFoo() const; 773 string PredicateMethod = ?; 774 775 /// The name of the method on the target specific operand to call to add the 776 /// target specific operand to an MCInst. If not set, this will default to 777 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 778 /// signature should be: 779 /// void addFooOperands(MCInst &Inst, unsigned N) const; 780 string RenderMethod = ?; 781 782 /// The name of the method on the target specific operand to call to custom 783 /// handle the operand parsing. This is useful when the operands do not relate 784 /// to immediates or registers and are very instruction specific (as flags to 785 /// set in a processor register, coprocessor number, ...). 786 string ParserMethod = ?; 787 788 // The diagnostic type to present when referencing this operand in a 789 // match failure error message. By default, use a generic "invalid operand" 790 // diagnostic. The target AsmParser maps these codes to text. 791 string DiagnosticType = ""; 792 793 /// A diagnostic message to emit when an invalid value is provided for this 794 /// operand. 795 string DiagnosticString = ""; 796 797 /// Set to 1 if this operand is optional and not always required. Typically, 798 /// the AsmParser will emit an error when it finishes parsing an 799 /// instruction if it hasn't matched all the operands yet. However, this 800 /// error will be suppressed if all of the remaining unmatched operands are 801 /// marked as IsOptional. 802 /// 803 /// Optional arguments must be at the end of the operand list. 804 bit IsOptional = false; 805 806 /// The name of the method on the target specific asm parser that returns the 807 /// default operand for this optional operand. This method is only used if 808 /// IsOptional == 1. If not set, this will default to "defaultFooOperands", 809 /// where Foo is the AsmOperandClass name. The method signature should be: 810 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const; 811 string DefaultMethod = ?; 812} 813 814def ImmAsmOperand : AsmOperandClass { 815 let Name = "Imm"; 816} 817 818/// Operand Types - These provide the built-in operand types that may be used 819/// by a target. Targets can optionally provide their own operand types as 820/// needed, though this should not be needed for RISC targets. 821class Operand<ValueType ty> : DAGOperand { 822 ValueType Type = ty; 823 string PrintMethod = "printOperand"; 824 string EncoderMethod = ""; 825 bit hasCompleteDecoder = true; 826 string OperandType = "OPERAND_UNKNOWN"; 827 dag MIOperandInfo = (ops); 828 829 // MCOperandPredicate - Optionally, a code fragment operating on 830 // const MCOperand &MCOp, and returning a bool, to indicate if 831 // the value of MCOp is valid for the specific subclass of Operand 832 code MCOperandPredicate; 833 834 // ParserMatchClass - The "match class" that operands of this type fit 835 // in. Match classes are used to define the order in which instructions are 836 // match, to ensure that which instructions gets matched is deterministic. 837 // 838 // The target specific parser must be able to classify an parsed operand into 839 // a unique class, which does not partially overlap with any other classes. It 840 // can match a subset of some other class, in which case the AsmOperandClass 841 // should declare the other operand as one of its super classes. 842 AsmOperandClass ParserMatchClass = ImmAsmOperand; 843} 844 845class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 846 : DAGOperand { 847 // RegClass - The register class of the operand. 848 RegisterClass RegClass = regclass; 849 // PrintMethod - The target method to call to print register operands of 850 // this type. The method normally will just use an alt-name index to look 851 // up the name to print. Default to the generic printOperand(). 852 string PrintMethod = pm; 853 854 // EncoderMethod - The target method name to call to encode this register 855 // operand. 856 string EncoderMethod = ""; 857 858 // ParserMatchClass - The "match class" that operands of this type fit 859 // in. Match classes are used to define the order in which instructions are 860 // match, to ensure that which instructions gets matched is deterministic. 861 // 862 // The target specific parser must be able to classify an parsed operand into 863 // a unique class, which does not partially overlap with any other classes. It 864 // can match a subset of some other class, in which case the AsmOperandClass 865 // should declare the other operand as one of its super classes. 866 AsmOperandClass ParserMatchClass; 867 868 string OperandType = "OPERAND_REGISTER"; 869 870 // When referenced in the result of a CodeGen pattern, GlobalISel will 871 // normally copy the matched operand to the result. When this is set, it will 872 // emit a special copy that will replace zero-immediates with the specified 873 // zero-register. 874 Register GIZeroRegister = ?; 875} 876 877let OperandType = "OPERAND_IMMEDIATE" in { 878def i1imm : Operand<i1>; 879def i8imm : Operand<i8>; 880def i16imm : Operand<i16>; 881def i32imm : Operand<i32>; 882def i64imm : Operand<i64>; 883 884def f32imm : Operand<f32>; 885def f64imm : Operand<f64>; 886} 887 888// Register operands for generic instructions don't have an MVT, but do have 889// constraints linking the operands (e.g. all operands of a G_ADD must 890// have the same LLT). 891class TypedOperand<string Ty> : Operand<untyped> { 892 let OperandType = Ty; 893 bit IsPointer = false; 894 bit IsImmediate = false; 895} 896 897def type0 : TypedOperand<"OPERAND_GENERIC_0">; 898def type1 : TypedOperand<"OPERAND_GENERIC_1">; 899def type2 : TypedOperand<"OPERAND_GENERIC_2">; 900def type3 : TypedOperand<"OPERAND_GENERIC_3">; 901def type4 : TypedOperand<"OPERAND_GENERIC_4">; 902def type5 : TypedOperand<"OPERAND_GENERIC_5">; 903 904let IsPointer = true in { 905 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">; 906 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">; 907 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">; 908 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">; 909 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">; 910 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">; 911} 912 913// untyped_imm is for operands where isImm() will be true. It currently has no 914// special behaviour and is only used for clarity. 915def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> { 916 let IsImmediate = true; 917} 918 919/// zero_reg definition - Special node to stand for the zero register. 920/// 921def zero_reg; 922 923/// undef_tied_input - Special node to indicate an input register tied 924/// to an output which defaults to IMPLICIT_DEF. 925def undef_tied_input; 926 927/// All operands which the MC layer classifies as predicates should inherit from 928/// this class in some manner. This is already handled for the most commonly 929/// used PredicateOperand, but may be useful in other circumstances. 930class PredicateOp; 931 932/// OperandWithDefaultOps - This Operand class can be used as the parent class 933/// for an Operand that needs to be initialized with a default value if 934/// no value is supplied in a pattern. This class can be used to simplify the 935/// pattern definitions for instructions that have target specific flags 936/// encoded as immediate operands. 937class OperandWithDefaultOps<ValueType ty, dag defaultops> 938 : Operand<ty> { 939 dag DefaultOps = defaultops; 940} 941 942/// PredicateOperand - This can be used to define a predicate operand for an 943/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 944/// AlwaysVal specifies the value of this predicate when set to "always 945/// execute". 946class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 947 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 948 let MIOperandInfo = OpTypes; 949} 950 951/// OptionalDefOperand - This is used to define a optional definition operand 952/// for an instruction. DefaultOps is the register the operand represents if 953/// none is supplied, e.g. zero_reg. 954class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 955 : OperandWithDefaultOps<ty, defaultops> { 956 let MIOperandInfo = OpTypes; 957} 958 959 960// InstrInfo - This class should only be instantiated once to provide parameters 961// which are global to the target machine. 962// 963class InstrInfo { 964 // Target can specify its instructions in either big or little-endian formats. 965 // For instance, while both Sparc and PowerPC are big-endian platforms, the 966 // Sparc manual specifies its instructions in the format [31..0] (big), while 967 // PowerPC specifies them using the format [0..31] (little). 968 bit isLittleEndianEncoding = false; 969 970 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 971 // by default, and TableGen will infer their value from the instruction 972 // pattern when possible. 973 // 974 // Normally, TableGen will issue an error it it can't infer the value of a 975 // property that hasn't been set explicitly. When guessInstructionProperties 976 // is set, it will guess a safe value instead. 977 // 978 // This option is a temporary migration help. It will go away. 979 bit guessInstructionProperties = true; 980 981 // TableGen's instruction encoder generator has support for matching operands 982 // to bit-field variables both by name and by position. While matching by 983 // name is preferred, this is currently not possible for complex operands, 984 // and some targets still reply on the positional encoding rules. When 985 // generating a decoder for such targets, the positional encoding rules must 986 // be used by the decoder generator as well. 987 // 988 // This option is temporary; it will go away once the TableGen decoder 989 // generator has better support for complex operands and targets have 990 // migrated away from using positionally encoded operands. 991 bit decodePositionallyEncodedOperands = false; 992 993 // When set, this indicates that there will be no overlap between those 994 // operands that are matched by ordering (positional operands) and those 995 // matched by name. 996 // 997 // This option is temporary; it will go away once the TableGen decoder 998 // generator has better support for complex operands and targets have 999 // migrated away from using positionally encoded operands. 1000 bit noNamedPositionallyEncodedOperands = false; 1001} 1002 1003// Standard Pseudo Instructions. 1004// This list must match TargetOpcodes.def. 1005// Only these instructions are allowed in the TargetOpcode namespace. 1006// Ensure mayLoad and mayStore have a default value, so as not to break 1007// targets that set guessInstructionProperties=0. Any local definition of 1008// mayLoad/mayStore takes precedence over these default values. 1009class StandardPseudoInstruction : Instruction { 1010 let mayLoad = false; 1011 let mayStore = false; 1012 let isCodeGenOnly = true; 1013 let isPseudo = true; 1014 let hasNoSchedulingInfo = true; 1015 let Namespace = "TargetOpcode"; 1016} 1017def PHI : StandardPseudoInstruction { 1018 let OutOperandList = (outs unknown:$dst); 1019 let InOperandList = (ins variable_ops); 1020 let AsmString = "PHINODE"; 1021 let hasSideEffects = false; 1022} 1023def INLINEASM : StandardPseudoInstruction { 1024 let OutOperandList = (outs); 1025 let InOperandList = (ins variable_ops); 1026 let AsmString = ""; 1027 let hasSideEffects = false; // Note side effect is encoded in an operand. 1028} 1029def INLINEASM_BR : StandardPseudoInstruction { 1030 let OutOperandList = (outs); 1031 let InOperandList = (ins variable_ops); 1032 let AsmString = ""; 1033 // Unlike INLINEASM, this is always treated as having side-effects. 1034 let hasSideEffects = true; 1035 // Despite potentially branching, this instruction is intentionally _not_ 1036 // marked as a terminator or a branch. 1037} 1038def CFI_INSTRUCTION : StandardPseudoInstruction { 1039 let OutOperandList = (outs); 1040 let InOperandList = (ins i32imm:$id); 1041 let AsmString = ""; 1042 let hasCtrlDep = true; 1043 let hasSideEffects = false; 1044 let isNotDuplicable = true; 1045} 1046def EH_LABEL : StandardPseudoInstruction { 1047 let OutOperandList = (outs); 1048 let InOperandList = (ins i32imm:$id); 1049 let AsmString = ""; 1050 let hasCtrlDep = true; 1051 let hasSideEffects = false; 1052 let isNotDuplicable = true; 1053} 1054def GC_LABEL : StandardPseudoInstruction { 1055 let OutOperandList = (outs); 1056 let InOperandList = (ins i32imm:$id); 1057 let AsmString = ""; 1058 let hasCtrlDep = true; 1059 let hasSideEffects = false; 1060 let isNotDuplicable = true; 1061} 1062def ANNOTATION_LABEL : StandardPseudoInstruction { 1063 let OutOperandList = (outs); 1064 let InOperandList = (ins i32imm:$id); 1065 let AsmString = ""; 1066 let hasCtrlDep = true; 1067 let hasSideEffects = false; 1068 let isNotDuplicable = true; 1069} 1070def KILL : StandardPseudoInstruction { 1071 let OutOperandList = (outs); 1072 let InOperandList = (ins variable_ops); 1073 let AsmString = ""; 1074 let hasSideEffects = false; 1075} 1076def EXTRACT_SUBREG : StandardPseudoInstruction { 1077 let OutOperandList = (outs unknown:$dst); 1078 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 1079 let AsmString = ""; 1080 let hasSideEffects = false; 1081} 1082def INSERT_SUBREG : StandardPseudoInstruction { 1083 let OutOperandList = (outs unknown:$dst); 1084 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 1085 let AsmString = ""; 1086 let hasSideEffects = false; 1087 let Constraints = "$supersrc = $dst"; 1088} 1089def IMPLICIT_DEF : StandardPseudoInstruction { 1090 let OutOperandList = (outs unknown:$dst); 1091 let InOperandList = (ins); 1092 let AsmString = ""; 1093 let hasSideEffects = false; 1094 let isReMaterializable = true; 1095 let isAsCheapAsAMove = true; 1096} 1097def SUBREG_TO_REG : StandardPseudoInstruction { 1098 let OutOperandList = (outs unknown:$dst); 1099 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 1100 let AsmString = ""; 1101 let hasSideEffects = false; 1102} 1103def COPY_TO_REGCLASS : StandardPseudoInstruction { 1104 let OutOperandList = (outs unknown:$dst); 1105 let InOperandList = (ins unknown:$src, i32imm:$regclass); 1106 let AsmString = ""; 1107 let hasSideEffects = false; 1108 let isAsCheapAsAMove = true; 1109} 1110def DBG_VALUE : StandardPseudoInstruction { 1111 let OutOperandList = (outs); 1112 let InOperandList = (ins variable_ops); 1113 let AsmString = "DBG_VALUE"; 1114 let hasSideEffects = false; 1115} 1116def DBG_VALUE_LIST : StandardPseudoInstruction { 1117 let OutOperandList = (outs); 1118 let InOperandList = (ins variable_ops); 1119 let AsmString = "DBG_VALUE_LIST"; 1120 let hasSideEffects = 0; 1121} 1122def DBG_INSTR_REF : StandardPseudoInstruction { 1123 let OutOperandList = (outs); 1124 let InOperandList = (ins variable_ops); 1125 let AsmString = "DBG_INSTR_REF"; 1126 let hasSideEffects = false; 1127} 1128def DBG_PHI : StandardPseudoInstruction { 1129 let OutOperandList = (outs); 1130 let InOperandList = (ins variable_ops); 1131 let AsmString = "DBG_PHI"; 1132 let hasSideEffects = 0; 1133} 1134def DBG_LABEL : StandardPseudoInstruction { 1135 let OutOperandList = (outs); 1136 let InOperandList = (ins unknown:$label); 1137 let AsmString = "DBG_LABEL"; 1138 let hasSideEffects = false; 1139} 1140def REG_SEQUENCE : StandardPseudoInstruction { 1141 let OutOperandList = (outs unknown:$dst); 1142 let InOperandList = (ins unknown:$supersrc, variable_ops); 1143 let AsmString = ""; 1144 let hasSideEffects = false; 1145 let isAsCheapAsAMove = true; 1146} 1147def COPY : StandardPseudoInstruction { 1148 let OutOperandList = (outs unknown:$dst); 1149 let InOperandList = (ins unknown:$src); 1150 let AsmString = ""; 1151 let hasSideEffects = false; 1152 let isAsCheapAsAMove = true; 1153 let hasNoSchedulingInfo = false; 1154} 1155def BUNDLE : StandardPseudoInstruction { 1156 let OutOperandList = (outs); 1157 let InOperandList = (ins variable_ops); 1158 let AsmString = "BUNDLE"; 1159 let hasSideEffects = false; 1160} 1161def LIFETIME_START : StandardPseudoInstruction { 1162 let OutOperandList = (outs); 1163 let InOperandList = (ins i32imm:$id); 1164 let AsmString = "LIFETIME_START"; 1165 let hasSideEffects = false; 1166} 1167def LIFETIME_END : StandardPseudoInstruction { 1168 let OutOperandList = (outs); 1169 let InOperandList = (ins i32imm:$id); 1170 let AsmString = "LIFETIME_END"; 1171 let hasSideEffects = false; 1172} 1173def PSEUDO_PROBE : StandardPseudoInstruction { 1174 let OutOperandList = (outs); 1175 let InOperandList = (ins i64imm:$guid, i64imm:$index, i8imm:$type, i32imm:$attr); 1176 let AsmString = "PSEUDO_PROBE"; 1177 let hasSideEffects = 1; 1178} 1179def ARITH_FENCE : StandardPseudoInstruction { 1180 let OutOperandList = (outs unknown:$dst); 1181 let InOperandList = (ins unknown:$src); 1182 let AsmString = ""; 1183 let hasSideEffects = false; 1184 let Constraints = "$src = $dst"; 1185} 1186 1187def STACKMAP : StandardPseudoInstruction { 1188 let OutOperandList = (outs); 1189 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 1190 let hasSideEffects = true; 1191 let isCall = true; 1192 let mayLoad = true; 1193 let usesCustomInserter = true; 1194} 1195def PATCHPOINT : StandardPseudoInstruction { 1196 let OutOperandList = (outs unknown:$dst); 1197 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 1198 i32imm:$nargs, i32imm:$cc, variable_ops); 1199 let hasSideEffects = true; 1200 let isCall = true; 1201 let mayLoad = true; 1202 let usesCustomInserter = true; 1203} 1204def STATEPOINT : StandardPseudoInstruction { 1205 let OutOperandList = (outs variable_ops); 1206 let InOperandList = (ins variable_ops); 1207 let usesCustomInserter = true; 1208 let mayLoad = true; 1209 let mayStore = true; 1210 let hasSideEffects = true; 1211 let isCall = true; 1212} 1213def LOAD_STACK_GUARD : StandardPseudoInstruction { 1214 let OutOperandList = (outs ptr_rc:$dst); 1215 let InOperandList = (ins); 1216 let mayLoad = true; 1217 bit isReMaterializable = true; 1218 let hasSideEffects = false; 1219 bit isPseudo = true; 1220} 1221def PREALLOCATED_SETUP : StandardPseudoInstruction { 1222 let OutOperandList = (outs); 1223 let InOperandList = (ins i32imm:$a); 1224 let usesCustomInserter = true; 1225 let hasSideEffects = true; 1226} 1227def PREALLOCATED_ARG : StandardPseudoInstruction { 1228 let OutOperandList = (outs ptr_rc:$loc); 1229 let InOperandList = (ins i32imm:$a, i32imm:$b); 1230 let usesCustomInserter = true; 1231 let hasSideEffects = true; 1232} 1233def LOCAL_ESCAPE : StandardPseudoInstruction { 1234 // This instruction is really just a label. It has to be part of the chain so 1235 // that it doesn't get dropped from the DAG, but it produces nothing and has 1236 // no side effects. 1237 let OutOperandList = (outs); 1238 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 1239 let hasSideEffects = false; 1240 let hasCtrlDep = true; 1241} 1242def FAULTING_OP : StandardPseudoInstruction { 1243 let OutOperandList = (outs unknown:$dst); 1244 let InOperandList = (ins variable_ops); 1245 let usesCustomInserter = true; 1246 let hasSideEffects = true; 1247 let mayLoad = true; 1248 let mayStore = true; 1249 let isTerminator = true; 1250 let isBranch = true; 1251} 1252def PATCHABLE_OP : StandardPseudoInstruction { 1253 let OutOperandList = (outs); 1254 let InOperandList = (ins variable_ops); 1255 let usesCustomInserter = true; 1256 let mayLoad = true; 1257 let mayStore = true; 1258 let hasSideEffects = true; 1259} 1260def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { 1261 let OutOperandList = (outs); 1262 let InOperandList = (ins); 1263 let AsmString = "# XRay Function Enter."; 1264 let usesCustomInserter = true; 1265 let hasSideEffects = true; 1266} 1267def PATCHABLE_RET : StandardPseudoInstruction { 1268 let OutOperandList = (outs); 1269 let InOperandList = (ins variable_ops); 1270 let AsmString = "# XRay Function Patchable RET."; 1271 let usesCustomInserter = true; 1272 let hasSideEffects = true; 1273 let isTerminator = true; 1274 let isReturn = true; 1275} 1276def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { 1277 let OutOperandList = (outs); 1278 let InOperandList = (ins); 1279 let AsmString = "# XRay Function Exit."; 1280 let usesCustomInserter = true; 1281 let hasSideEffects = true; 1282 let isReturn = false; // Original return instruction will follow 1283} 1284def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { 1285 let OutOperandList = (outs); 1286 let InOperandList = (ins variable_ops); 1287 let AsmString = "# XRay Tail Call Exit."; 1288 let usesCustomInserter = true; 1289 let hasSideEffects = true; 1290 let isReturn = true; 1291} 1292def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { 1293 let OutOperandList = (outs); 1294 let InOperandList = (ins ptr_rc:$event, unknown:$size); 1295 let AsmString = "# XRay Custom Event Log."; 1296 let usesCustomInserter = true; 1297 let isCall = true; 1298 let mayLoad = true; 1299 let mayStore = true; 1300 let hasSideEffects = true; 1301} 1302def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction { 1303 let OutOperandList = (outs); 1304 let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size); 1305 let AsmString = "# XRay Typed Event Log."; 1306 let usesCustomInserter = true; 1307 let isCall = true; 1308 let mayLoad = true; 1309 let mayStore = true; 1310 let hasSideEffects = true; 1311} 1312def FENTRY_CALL : StandardPseudoInstruction { 1313 let OutOperandList = (outs); 1314 let InOperandList = (ins); 1315 let AsmString = "# FEntry call"; 1316 let usesCustomInserter = true; 1317 let isCall = true; 1318 let mayLoad = true; 1319 let mayStore = true; 1320 let hasSideEffects = true; 1321} 1322def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction { 1323 let OutOperandList = (outs); 1324 let InOperandList = (ins variable_ops); 1325 let AsmString = ""; 1326 let hasSideEffects = true; 1327} 1328 1329// Generic opcodes used in GlobalISel. 1330include "llvm/Target/GenericOpcodes.td" 1331 1332//===----------------------------------------------------------------------===// 1333// AsmParser - This class can be implemented by targets that wish to implement 1334// .s file parsing. 1335// 1336// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 1337// syntax on X86 for example). 1338// 1339class AsmParser { 1340 // AsmParserClassName - This specifies the suffix to use for the asmparser 1341 // class. Generated AsmParser classes are always prefixed with the target 1342 // name. 1343 string AsmParserClassName = "AsmParser"; 1344 1345 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 1346 // function of the AsmParser class to call on every matched instruction. 1347 // This can be used to perform target specific instruction post-processing. 1348 string AsmParserInstCleanup = ""; 1349 1350 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 1351 // written register name matcher 1352 bit ShouldEmitMatchRegisterName = true; 1353 1354 // Set to true if the target needs a generated 'alternative register name' 1355 // matcher. 1356 // 1357 // This generates a function which can be used to lookup registers from 1358 // their aliases. This function will fail when called on targets where 1359 // several registers share the same alias (i.e. not a 1:1 mapping). 1360 bit ShouldEmitMatchRegisterAltName = false; 1361 1362 // Set to true if MatchRegisterName and MatchRegisterAltName functions 1363 // should be generated even if there are duplicate register names. The 1364 // target is responsible for coercing aliased registers as necessary 1365 // (e.g. in validateTargetOperandClass), and there are no guarantees about 1366 // which numeric register identifier will be returned in the case of 1367 // multiple matches. 1368 bit AllowDuplicateRegisterNames = false; 1369 1370 // HasMnemonicFirst - Set to false if target instructions don't always 1371 // start with a mnemonic as the first token. 1372 bit HasMnemonicFirst = true; 1373 1374 // ReportMultipleNearMisses - 1375 // When 0, the assembly matcher reports an error for one encoding or operand 1376 // that did not match the parsed instruction. 1377 // When 1, the assembly matcher returns a list of encodings that were close 1378 // to matching the parsed instruction, so to allow more detailed error 1379 // messages. 1380 bit ReportMultipleNearMisses = false; 1381} 1382def DefaultAsmParser : AsmParser; 1383 1384//===----------------------------------------------------------------------===// 1385// AsmParserVariant - Subtargets can have multiple different assembly parsers 1386// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 1387// implemented by targets to describe such variants. 1388// 1389class AsmParserVariant { 1390 // Variant - AsmParsers can be of multiple different variants. Variants are 1391 // used to support targets that need to parse multiple formats for the 1392 // assembly language. 1393 int Variant = 0; 1394 1395 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 1396 string Name = ""; 1397 1398 // CommentDelimiter - If given, the delimiter string used to recognize 1399 // comments which are hard coded in the .td assembler strings for individual 1400 // instructions. 1401 string CommentDelimiter = ""; 1402 1403 // RegisterPrefix - If given, the token prefix which indicates a register 1404 // token. This is used by the matcher to automatically recognize hard coded 1405 // register tokens as constrained registers, instead of tokens, for the 1406 // purposes of matching. 1407 string RegisterPrefix = ""; 1408 1409 // TokenizingCharacters - Characters that are standalone tokens 1410 string TokenizingCharacters = "[]*!"; 1411 1412 // SeparatorCharacters - Characters that are not tokens 1413 string SeparatorCharacters = " \t,"; 1414 1415 // BreakCharacters - Characters that start new identifiers 1416 string BreakCharacters = ""; 1417} 1418def DefaultAsmParserVariant : AsmParserVariant; 1419 1420// Operators for combining SubtargetFeatures in AssemblerPredicates 1421def any_of; 1422def all_of; 1423 1424/// AssemblerPredicate - This is a Predicate that can be used when the assembler 1425/// matches instructions and aliases. 1426class AssemblerPredicate<dag cond, string name = ""> { 1427 bit AssemblerMatcherPredicate = true; 1428 dag AssemblerCondDag = cond; 1429 string PredicateName = name; 1430} 1431 1432/// TokenAlias - This class allows targets to define assembler token 1433/// operand aliases. That is, a token literal operand which is equivalent 1434/// to another, canonical, token literal. For example, ARM allows: 1435/// vmov.u32 s4, #0 -> vmov.i32, #0 1436/// 'u32' is a more specific designator for the 32-bit integer type specifier 1437/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 1438/// def : TokenAlias<".u32", ".i32">; 1439/// 1440/// This works by marking the match class of 'From' as a subclass of the 1441/// match class of 'To'. 1442class TokenAlias<string From, string To> { 1443 string FromToken = From; 1444 string ToToken = To; 1445} 1446 1447/// MnemonicAlias - This class allows targets to define assembler mnemonic 1448/// aliases. This should be used when all forms of one mnemonic are accepted 1449/// with a different mnemonic. For example, X86 allows: 1450/// sal %al, 1 -> shl %al, 1 1451/// sal %ax, %cl -> shl %ax, %cl 1452/// sal %eax, %cl -> shl %eax, %cl 1453/// etc. Though "sal" is accepted with many forms, all of them are directly 1454/// translated to a shl, so it can be handled with (in the case of X86, it 1455/// actually has one for each suffix as well): 1456/// def : MnemonicAlias<"sal", "shl">; 1457/// 1458/// Mnemonic aliases are mapped before any other translation in the match phase, 1459/// and do allow Requires predicates, e.g.: 1460/// 1461/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1462/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1463/// 1464/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1465/// 1466/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1467/// 1468/// If no variant (e.g., "att" or "intel") is specified then the alias is 1469/// applied unconditionally. 1470class MnemonicAlias<string From, string To, string VariantName = ""> { 1471 string FromMnemonic = From; 1472 string ToMnemonic = To; 1473 string AsmVariantName = VariantName; 1474 1475 // Predicates - Predicates that must be true for this remapping to happen. 1476 list<Predicate> Predicates = []; 1477} 1478 1479/// InstAlias - This defines an alternate assembly syntax that is allowed to 1480/// match an instruction that has a different (more canonical) assembly 1481/// representation. 1482class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> { 1483 string AsmString = Asm; // The .s format to match the instruction with. 1484 dag ResultInst = Result; // The MCInst to generate. 1485 1486 // This determines which order the InstPrinter detects aliases for 1487 // printing. A larger value makes the alias more likely to be 1488 // emitted. The Instruction's own definition is notionally 0.5, so 0 1489 // disables printing and 1 enables it if there are no conflicting aliases. 1490 int EmitPriority = Emit; 1491 1492 // Predicates - Predicates that must be true for this to match. 1493 list<Predicate> Predicates = []; 1494 1495 // If the instruction specified in Result has defined an AsmMatchConverter 1496 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1497 // function when converting the OperandVector into an MCInst instead of the 1498 // function that is generated by the dag Result. 1499 // Setting this to 0 will cause the alias to ignore the Result instruction's 1500 // defined AsmMatchConverter and instead use the function generated by the 1501 // dag Result. 1502 bit UseInstAsmMatchConverter = true; 1503 1504 // Assembler variant name to use for this alias. If not specified then 1505 // assembler variants will be determined based on AsmString 1506 string AsmVariantName = VariantName; 1507} 1508 1509//===----------------------------------------------------------------------===// 1510// AsmWriter - This class can be implemented by targets that need to customize 1511// the format of the .s file writer. 1512// 1513// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1514// on X86 for example). 1515// 1516class AsmWriter { 1517 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1518 // class. Generated AsmWriter classes are always prefixed with the target 1519 // name. 1520 string AsmWriterClassName = "InstPrinter"; 1521 1522 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1523 // the various print methods. 1524 // FIXME: Remove after all ports are updated. 1525 int PassSubtarget = 0; 1526 1527 // Variant - AsmWriters can be of multiple different variants. Variants are 1528 // used to support targets that need to emit assembly code in ways that are 1529 // mostly the same for different targets, but have minor differences in 1530 // syntax. If the asmstring contains {|} characters in them, this integer 1531 // will specify which alternative to use. For example "{x|y|z}" with Variant 1532 // == 1, will expand to "y". 1533 int Variant = 0; 1534} 1535def DefaultAsmWriter : AsmWriter; 1536 1537 1538//===----------------------------------------------------------------------===// 1539// Target - This class contains the "global" target information 1540// 1541class Target { 1542 // InstructionSet - Instruction set description for this target. 1543 InstrInfo InstructionSet; 1544 1545 // AssemblyParsers - The AsmParser instances available for this target. 1546 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1547 1548 /// AssemblyParserVariants - The AsmParserVariant instances available for 1549 /// this target. 1550 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1551 1552 // AssemblyWriters - The AsmWriter instances available for this target. 1553 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1554 1555 // AllowRegisterRenaming - Controls whether this target allows 1556 // post-register-allocation renaming of registers. This is done by 1557 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1 1558 // for all opcodes if this flag is set to 0. 1559 int AllowRegisterRenaming = 0; 1560} 1561 1562//===----------------------------------------------------------------------===// 1563// SubtargetFeature - A characteristic of the chip set. 1564// 1565class SubtargetFeature<string n, string a, string v, string d, 1566 list<SubtargetFeature> i = []> { 1567 // Name - Feature name. Used by command line (-mattr=) to determine the 1568 // appropriate target chip. 1569 // 1570 string Name = n; 1571 1572 // Attribute - Attribute to be set by feature. 1573 // 1574 string Attribute = a; 1575 1576 // Value - Value the attribute to be set to by feature. 1577 // 1578 string Value = v; 1579 1580 // Desc - Feature description. Used by command line (-mattr=) to display help 1581 // information. 1582 // 1583 string Desc = d; 1584 1585 // Implies - Features that this feature implies are present. If one of those 1586 // features isn't set, then this one shouldn't be set either. 1587 // 1588 list<SubtargetFeature> Implies = i; 1589} 1590 1591/// Specifies a Subtarget feature that this instruction is deprecated on. 1592class Deprecated<SubtargetFeature dep> { 1593 SubtargetFeature DeprecatedFeatureMask = dep; 1594} 1595 1596/// A custom predicate used to determine if an instruction is 1597/// deprecated or not. 1598class ComplexDeprecationPredicate<string dep> { 1599 string ComplexDeprecationPredicate = dep; 1600} 1601 1602//===----------------------------------------------------------------------===// 1603// Processor chip sets - These values represent each of the chip sets supported 1604// by the scheduler. Each Processor definition requires corresponding 1605// instruction itineraries. 1606// 1607class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f, 1608 list<SubtargetFeature> tunef = []> { 1609 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1610 // appropriate target chip. 1611 // 1612 string Name = n; 1613 1614 // SchedModel - The machine model for scheduling and instruction cost. 1615 // 1616 SchedMachineModel SchedModel = NoSchedModel; 1617 1618 // ProcItin - The scheduling information for the target processor. 1619 // 1620 ProcessorItineraries ProcItin = pi; 1621 1622 // Features - list of 1623 list<SubtargetFeature> Features = f; 1624 1625 // TuneFeatures - list of features for tuning for this CPU. If the target 1626 // supports -mtune, this should contain the list of features used to make 1627 // microarchitectural optimization decisions for a given processor. While 1628 // Features should contain the architectural features for the processor. 1629 list<SubtargetFeature> TuneFeatures = tunef; 1630} 1631 1632// ProcessorModel allows subtargets to specify the more general 1633// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1634// gradually move to this newer form. 1635// 1636// Although this class always passes NoItineraries to the Processor 1637// class, the SchedMachineModel may still define valid Itineraries. 1638class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f, 1639 list<SubtargetFeature> tunef = []> 1640 : Processor<n, NoItineraries, f, tunef> { 1641 let SchedModel = m; 1642} 1643 1644//===----------------------------------------------------------------------===// 1645// InstrMapping - This class is used to create mapping tables to relate 1646// instructions with each other based on the values specified in RowFields, 1647// ColFields, KeyCol and ValueCols. 1648// 1649class InstrMapping { 1650 // FilterClass - Used to limit search space only to the instructions that 1651 // define the relationship modeled by this InstrMapping record. 1652 string FilterClass; 1653 1654 // RowFields - List of fields/attributes that should be same for all the 1655 // instructions in a row of the relation table. Think of this as a set of 1656 // properties shared by all the instructions related by this relationship 1657 // model and is used to categorize instructions into subgroups. For instance, 1658 // if we want to define a relation that maps 'Add' instruction to its 1659 // predicated forms, we can define RowFields like this: 1660 // 1661 // let RowFields = BaseOp 1662 // All add instruction predicated/non-predicated will have to set their BaseOp 1663 // to the same value. 1664 // 1665 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1666 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1667 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1668 list<string> RowFields = []; 1669 1670 // List of fields/attributes that are same for all the instructions 1671 // in a column of the relation table. 1672 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1673 // based on the 'predSense' values. All the instruction in a specific 1674 // column have the same value and it is fixed for the column according 1675 // to the values set in 'ValueCols'. 1676 list<string> ColFields = []; 1677 1678 // Values for the fields/attributes listed in 'ColFields'. 1679 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1680 // that models this relation) should be non-predicated. 1681 // In the example above, 'Add' is the key instruction. 1682 list<string> KeyCol = []; 1683 1684 // List of values for the fields/attributes listed in 'ColFields', one for 1685 // each column in the relation table. 1686 // 1687 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1688 // table. First column requires all the instructions to have predSense 1689 // set to 'true' and second column requires it to be 'false'. 1690 list<list<string> > ValueCols = []; 1691} 1692 1693//===----------------------------------------------------------------------===// 1694// Pull in the common support for calling conventions. 1695// 1696include "llvm/Target/TargetCallingConv.td" 1697 1698//===----------------------------------------------------------------------===// 1699// Pull in the common support for DAG isel generation. 1700// 1701include "llvm/Target/TargetSelectionDAG.td" 1702 1703//===----------------------------------------------------------------------===// 1704// Pull in the common support for Global ISel register bank info generation. 1705// 1706include "llvm/Target/GlobalISel/RegisterBank.td" 1707 1708//===----------------------------------------------------------------------===// 1709// Pull in the common support for DAG isel generation. 1710// 1711include "llvm/Target/GlobalISel/Target.td" 1712 1713//===----------------------------------------------------------------------===// 1714// Pull in the common support for the Global ISel DAG-based selector generation. 1715// 1716include "llvm/Target/GlobalISel/SelectionDAGCompat.td" 1717 1718//===----------------------------------------------------------------------===// 1719// Pull in the common support for Pfm Counters generation. 1720// 1721include "llvm/Target/TargetPfmCounters.td" 1722