1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s 3--- | 4 define i32 @jt_test(i32 %x) { 5 entry: 6 switch i32 %x, label %return [ 7 i32 75, label %sw.bb 8 i32 34, label %sw.bb 9 i32 56, label %sw.bb 10 i32 35, label %sw.bb 11 i32 40, label %sw.bb 12 i32 4, label %sw.bb1 13 i32 5, label %sw.bb1 14 i32 6, label %sw.bb1 15 ] 16 17 sw.bb: 18 %add = add nsw i32 %x, 42 19 br label %return 20 21 sw.bb1: 22 %mul = mul nsw i32 %x, 3 23 br label %return 24 25 return: 26 %retval.0 = phi i32 [ %mul, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ] 27 ret i32 %retval.0 28 } 29 30... 31--- 32name: jt_test 33alignment: 4 34legalized: true 35regBankSelected: true 36tracksRegLiveness: true 37machineFunctionInfo: {} 38jumpTable: 39 kind: block-address 40 entries: 41 - id: 0 42 blocks: [ '%bb.3', '%bb.3', '%bb.3', '%bb.4', '%bb.4', '%bb.4', 43 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 44 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 45 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 46 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 47 '%bb.2', '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 48 '%bb.2', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 49 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 50 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2', '%bb.4', 51 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 52 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', 53 '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.4', '%bb.2' ] 54body: | 55 ; CHECK-LABEL: name: jt_test 56 ; CHECK: bb.0.entry: 57 ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) 58 ; CHECK: liveins: $w0 59 ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0 60 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr 61 ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv 62 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32 63 ; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv 64 ; CHECK: Bcc 8, %bb.4, implicit $nzcv 65 ; CHECK: bb.1.entry: 66 ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) 67 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr 68 ; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0 69 ; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0 70 ; CHECK: BR %18 71 ; CHECK: bb.2.sw.bb: 72 ; CHECK: successors: %bb.4(0x80000000) 73 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = nsw ADDWri [[COPY]], 42, 0 74 ; CHECK: B %bb.4 75 ; CHECK: bb.3.sw.bb1: 76 ; CHECK: successors: %bb.4(0x80000000) 77 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3 78 ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[COPY]], [[MOVi32imm]], $wzr 79 ; CHECK: bb.4.return: 80 ; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[MADDWrrr]], %bb.3, [[ADDWri]], %bb.2, [[COPY1]], %bb.0, [[COPY2]], %bb.1 81 ; CHECK: $w0 = COPY [[PHI]] 82 ; CHECK: RET_ReallyLR implicit $w0 83 bb.1.entry: 84 liveins: $w0 85 86 %0:gpr(s32) = COPY $w0 87 %4:gpr(s32) = G_CONSTANT i32 71 88 %8:gpr(s32) = G_CONSTANT i32 3 89 %10:gpr(s32) = G_CONSTANT i32 42 90 %13:gpr(s32) = G_CONSTANT i32 0 91 %1:gpr(s32) = G_CONSTANT i32 4 92 %2:gpr(s32) = G_SUB %0, %1 93 %3:gpr(s64) = G_ZEXT %2(s32) 94 %5:gpr(s64) = G_ZEXT %4(s32) 95 %14:gpr(s32) = G_ICMP intpred(ugt), %3(s64), %5 96 %6:gpr(s1) = G_TRUNC %14(s32) 97 G_BRCOND %6(s1), %bb.4 98 99 bb.5.entry: 100 successors: %bb.3, %bb.4, %bb.2 101 102 %17:gpr(s32) = G_CONSTANT i32 0 103 %7:gpr(p0) = G_JUMP_TABLE %jump-table.0 104 G_BRJT %7(p0), %jump-table.0, %3(s64) 105 106 bb.2.sw.bb: 107 %16:gpr(s32) = G_CONSTANT i32 42 108 %11:gpr(s32) = nsw G_ADD %0, %16 109 G_BR %bb.4 110 111 bb.3.sw.bb1: 112 %15:gpr(s32) = G_CONSTANT i32 3 113 %9:gpr(s32) = nsw G_MUL %0, %15 114 115 bb.4.return: 116 %12:gpr(s32) = G_PHI %9(s32), %bb.3, %11(s32), %bb.2, %13(s32), %bb.1, %17(s32), %bb.5 117 $w0 = COPY %12(s32) 118 RET_ReallyLR implicit $w0 119 120... 121