1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            logical_imm_64_and
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $x0
12    ; CHECK-LABEL: name: logical_imm_64_and
13    ; CHECK: liveins: $x0
14    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
15    ; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
16    ; CHECK: $x0 = COPY [[ANDXri]]
17    ; CHECK: RET_ReallyLR implicit $x0
18    %0:gpr(s64) = COPY $x0
19    %1:gpr(s64) = G_CONSTANT i64 1
20    %2:gpr(s64) = G_AND %0, %1:gpr(s64)
21    $x0 = COPY %2:gpr(s64)
22    RET_ReallyLR implicit $x0
23...
24---
25name:            logical_imm_64_or
26legalized:       true
27regBankSelected: true
28tracksRegLiveness: true
29body:             |
30  bb.0:
31    liveins: $x0
32    ; CHECK-LABEL: name: logical_imm_64_or
33    ; CHECK: liveins: $x0
34    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
35    ; CHECK: [[ORRXri:%[0-9]+]]:gpr64sp = ORRXri [[COPY]], 4096
36    ; CHECK: $x0 = COPY [[ORRXri]]
37    ; CHECK: RET_ReallyLR implicit $x0
38    %0:gpr(s64) = COPY $x0
39    %1:gpr(s64) = G_CONSTANT i64 1
40    %2:gpr(s64) = G_OR %0, %1:gpr(s64)
41    $x0 = COPY %2:gpr(s64)
42    RET_ReallyLR implicit $x0
43...
44---
45name:            logical_imm_64_xor
46legalized:       true
47regBankSelected: true
48tracksRegLiveness: true
49body:             |
50  bb.0:
51    liveins: $x0
52    ; CHECK-LABEL: name: logical_imm_64_xor
53    ; CHECK: liveins: $x0
54    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
55    ; CHECK: [[EORXri:%[0-9]+]]:gpr64sp = EORXri [[COPY]], 4096
56    ; CHECK: $x0 = COPY [[EORXri]]
57    ; CHECK: RET_ReallyLR implicit $x0
58    %0:gpr(s64) = COPY $x0
59    %1:gpr(s64) = G_CONSTANT i64 1
60    %2:gpr(s64) = G_XOR %0, %1:gpr(s64)
61    $x0 = COPY %2:gpr(s64)
62    RET_ReallyLR implicit $x0
63...
64---
65name:            logical_imm_32_and
66legalized:       true
67regBankSelected: true
68tracksRegLiveness: true
69body:             |
70  bb.0:
71    liveins: $w0
72    ; CHECK-LABEL: name: logical_imm_32_and
73    ; CHECK: liveins: $w0
74    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
75    ; CHECK: [[ANDWri:%[0-9]+]]:gpr32sp = ANDWri [[COPY]], 0
76    ; CHECK: $w0 = COPY [[ANDWri]]
77    ; CHECK: RET_ReallyLR implicit $w0
78    %0:gpr(s32) = COPY $w0
79    %1:gpr(s32) = G_CONSTANT i32 1
80    %2:gpr(s32) = G_AND %0, %1:gpr(s32)
81    $w0 = COPY %2:gpr(s32)
82    RET_ReallyLR implicit $w0
83...
84---
85name:            logical_imm_32_or
86legalized:       true
87regBankSelected: true
88tracksRegLiveness: true
89body:             |
90  bb.0:
91    liveins: $w0
92    ; CHECK-LABEL: name: logical_imm_32_or
93    ; CHECK: liveins: $w0
94    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
95    ; CHECK: [[ORRWri:%[0-9]+]]:gpr32sp = ORRWri [[COPY]], 0
96    ; CHECK: $w0 = COPY [[ORRWri]]
97    ; CHECK: RET_ReallyLR implicit $w0
98    %0:gpr(s32) = COPY $w0
99    %1:gpr(s32) = G_CONSTANT i32 1
100    %2:gpr(s32) = G_OR %0, %1:gpr(s32)
101    $w0 = COPY %2:gpr(s32)
102    RET_ReallyLR implicit $w0
103...
104---
105name:            logical_imm_32_xor
106legalized:       true
107regBankSelected: true
108tracksRegLiveness: true
109body:             |
110  bb.0:
111    liveins: $w0
112    ; CHECK-LABEL: name: logical_imm_32_xor
113    ; CHECK: liveins: $w0
114    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
115    ; CHECK: [[EORWri:%[0-9]+]]:gpr32sp = EORWri [[COPY]], 0
116    ; CHECK: $w0 = COPY [[EORWri]]
117    ; CHECK: RET_ReallyLR implicit $w0
118    %0:gpr(s32) = COPY $w0
119    %1:gpr(s32) = G_CONSTANT i32 1
120    %2:gpr(s32) = G_XOR %0, %1:gpr(s32)
121    $w0 = COPY %2:gpr(s32)
122    RET_ReallyLR implicit $w0
123...
124