1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -amdgpu-enable-lower-module-lds=0 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -amdgpu-enable-lower-module-lds=0 -filetype=obj < %s | llvm-readobj -r --syms - | FileCheck -check-prefixes=ELF %s 3 4@lds.external = external unnamed_addr addrspace(3) global [0 x i32] 5@lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8 6 7; ELF: Relocations [ 8; ELF-NEXT: Section (3) .rel.text { 9; ELF-NEXT: 0x{{[0-9a-f]*}} R_AMDGPU_ABS32 lds.external 10; ELF-NEXT: 0x{{[0-9a-f]*}} R_AMDGPU_ABS32 lds.defined 11; ELF-NEXT: } 12; ELF-NEXT: ] 13 14; ELF: Symbol { 15; ELF: Name: lds.external 16; ELF-NEXT: Value: 0x4 17; ELF-NEXT: Size: 0 18; ELF-NEXT: Binding: Global (0x1) 19; ELF-NEXT: Type: Object (0x1) 20; ELF-NEXT: Other: 0 21; ELF-NEXT: Section: Processor Specific (0xFF00) 22; ELF-NEXT: } 23 24; ELF: Symbol { 25; ELF: Name: lds.defined 26; ELF-NEXT: Value: 0x8 27; ELF-NEXT: Size: 32 28; ELF-NEXT: Binding: Global (0x1) 29; ELF-NEXT: Type: Object (0x1) 30; ELF-NEXT: Other: 0 31; ELF-NEXT: Section: Processor Specific (0xFF00) 32; ELF-NEXT: } 33 34; GCN-LABEL: {{^}}test_basic: 35; GCN: v_mov_b32_e32 v1, lds.external@abs32@lo ; encoding: [0xff,0x02,0x02,0x7e,A,A,A,A] 36; GCN-NEXT: ; fixup A - offset: 4, value: lds.external@abs32@lo, kind: FK_Data_4{{$}} 37; 38; GCN: s_add_i32 s0, s0, lds.defined@abs32@lo ; encoding: [0x00,0xff,0x00,0x81,A,A,A,A] 39; GCN-NEXT: ; fixup A - offset: 4, value: lds.defined@abs32@lo, kind: FK_Data_4{{$}} 40; 41; GCN: .globl lds.external 42; GCN: .amdgpu_lds lds.external, 0, 4 43; GCN: .globl lds.defined 44; GCN: .amdgpu_lds lds.defined, 32, 8 45define amdgpu_gs float @test_basic(i32 inreg %wave, i32 %arg1) #0 { 46main_body: 47 %gep0 = getelementptr [0 x i32], [0 x i32] addrspace(3)* @lds.external, i32 0, i32 %arg1 48 %tmp = load i32, i32 addrspace(3)* %gep0 49 50 %gep1 = getelementptr [8 x i32], [8 x i32] addrspace(3)* @lds.defined, i32 0, i32 %wave 51 store i32 123, i32 addrspace(3)* %gep1 52 53 %r = bitcast i32 %tmp to float 54 ret float %r 55} 56 57; Function Attrs: convergent nounwind readnone 58declare i64 @llvm.amdgcn.icmp.i64.i32(i32, i32, i32) #4 59 60attributes #0 = { "no-signed-zeros-fp-math"="true" } 61attributes #4 = { convergent nounwind readnone } 62