1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 3 4; Test that doing a shift of a pointer with a constant add will be 5; folded into the constant offset addressing mode even if the add has 6; multiple uses. This is relevant to accessing 2 separate, adjacent 7; LDS globals. 8 9 10declare i32 @llvm.amdgcn.workitem.id.x() #1 11 12@lds0 = addrspace(3) global [512 x float] undef, align 4 13@lds1 = addrspace(3) global [512 x float] undef, align 4 14 15 16; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8 17 18; GCN-LABEL: {{^}}load_shl_base_lds_0: 19; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 20; GCN: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 21; GCN: s_endpgm 22define amdgpu_kernel void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 23 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 24 %idx.0 = add nsw i32 %tid.x, 2 25 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 26 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 27 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 28 store float %val0, float addrspace(1)* %out 29 ret void 30} 31 32; Make sure once the first use is folded into the addressing mode, the 33; remaining add use goes through the normal shl + add constant fold. 34 35; GCN-LABEL: {{^}}load_shl_base_lds_1: 36; GCN: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 2, {{v[0-9]+}} 37; GCN: ds_read_b32 [[RESULT:v[0-9]+]], [[OFS]] offset:8 38; GCN: v_add_{{[iu]}}32_e32 [[ADDUSE:v[0-9]+]], vcc, 8, v{{[0-9]+}} 39; GCN-DAG: buffer_store_dword [[RESULT]] 40; GCN-DAG: buffer_store_dword [[ADDUSE]] 41; GCN: s_endpgm 42define amdgpu_kernel void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 43 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 44 %idx.0 = add nsw i32 %tid.x, 2 45 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 46 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 47 %shl_add_use = shl i32 %idx.0, 2 48 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4 49 store float %val0, float addrspace(1)* %out 50 ret void 51} 52 53@maxlds = addrspace(3) global [65536 x i8] undef, align 4 54 55; GCN-LABEL: {{^}}load_shl_base_lds_max_offset 56; GCN: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535 57; GCN: s_endpgm 58define amdgpu_kernel void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 { 59 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 60 %idx.0 = add nsw i32 %tid.x, 65535 61 %arrayidx0 = getelementptr inbounds [65536 x i8], [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0 62 %val0 = load i8, i8 addrspace(3)* %arrayidx0 63 store i32 %idx.0, i32 addrspace(1)* %add_use 64 store i8 %val0, i8 addrspace(1)* %out 65 ret void 66} 67 68; The two globals are placed adjacent in memory, so the same base 69; pointer can be used with an offset into the second one. 70 71; GCN-LABEL: {{^}}load_shl_base_lds_2: 72; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 73; GCN: s_mov_b32 m0, -1 74; GCN: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 75; GCN: s_endpgm 76define amdgpu_kernel void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { 77 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 78 %idx.0 = add nsw i32 %tid.x, 64 79 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 80 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 81 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0 82 %val1 = load float, float addrspace(3)* %arrayidx1, align 4 83 %sum = fadd float %val0, %val1 84 store float %sum, float addrspace(1)* %out, align 4 85 ret void 86} 87 88; GCN-LABEL: {{^}}store_shl_base_lds_0: 89; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 90; GCN: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 91; GCN: s_endpgm 92define amdgpu_kernel void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 93 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 94 %idx.0 = add nsw i32 %tid.x, 2 95 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 96 store float 1.0, float addrspace(3)* %arrayidx0, align 4 97 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 98 ret void 99} 100 101 102; -------------------------------------------------------------------------------- 103; Atomics. 104 105@lds2 = addrspace(3) global [512 x i32] undef, align 4 106 107; define amdgpu_kernel void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 108; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 109; %idx.0 = add nsw i32 %tid.x, 2 110; %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 111; %val = load atomic i32, i32 addrspace(3)* %arrayidx0 seq_cst, align 4 112; store i32 %val, i32 addrspace(1)* %out, align 4 113; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 114; ret void 115; } 116 117 118; GCN-LABEL: {{^}}atomic_cmpxchg_shl_base_lds_0: 119; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 120; GCN: ds_cmpst_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8 121; GCN: s_endpgm 122define amdgpu_kernel void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 { 123 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 124 %idx.0 = add nsw i32 %tid.x, 2 125 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 126 %pair = cmpxchg i32 addrspace(3)* %arrayidx0, i32 7, i32 %swap seq_cst monotonic 127 %result = extractvalue { i32, i1 } %pair, 0 128 store i32 %result, i32 addrspace(1)* %out, align 4 129 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 130 ret void 131} 132 133; GCN-LABEL: {{^}}atomic_swap_shl_base_lds_0: 134; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 135; GCN: ds_wrxchg_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 136; GCN: s_endpgm 137define amdgpu_kernel void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 138 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 139 %idx.0 = add nsw i32 %tid.x, 2 140 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 141 %val = atomicrmw xchg i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 142 store i32 %val, i32 addrspace(1)* %out, align 4 143 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 144 ret void 145} 146 147; GCN-LABEL: {{^}}atomic_add_shl_base_lds_0: 148; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 149; GCN: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 150; GCN: s_endpgm 151define amdgpu_kernel void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 152 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 153 %idx.0 = add nsw i32 %tid.x, 2 154 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 155 %val = atomicrmw add i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 156 store i32 %val, i32 addrspace(1)* %out, align 4 157 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 158 ret void 159} 160 161; GCN-LABEL: {{^}}atomic_sub_shl_base_lds_0: 162; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 163; GCN: ds_sub_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 164; GCN: s_endpgm 165define amdgpu_kernel void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 166 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 167 %idx.0 = add nsw i32 %tid.x, 2 168 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 169 %val = atomicrmw sub i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 170 store i32 %val, i32 addrspace(1)* %out, align 4 171 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 172 ret void 173} 174 175; GCN-LABEL: {{^}}atomic_and_shl_base_lds_0: 176; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 177; GCN: ds_and_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 178; GCN: s_endpgm 179define amdgpu_kernel void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 180 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 181 %idx.0 = add nsw i32 %tid.x, 2 182 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 183 %val = atomicrmw and i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 184 store i32 %val, i32 addrspace(1)* %out, align 4 185 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 186 ret void 187} 188 189; GCN-LABEL: {{^}}atomic_or_shl_base_lds_0: 190; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 191; GCN: ds_or_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 192; GCN: s_endpgm 193define amdgpu_kernel void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 194 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 195 %idx.0 = add nsw i32 %tid.x, 2 196 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 197 %val = atomicrmw or i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 198 store i32 %val, i32 addrspace(1)* %out, align 4 199 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 200 ret void 201} 202 203; GCN-LABEL: {{^}}atomic_xor_shl_base_lds_0: 204; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 205; GCN: ds_xor_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 206; GCN: s_endpgm 207define amdgpu_kernel void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 208 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 209 %idx.0 = add nsw i32 %tid.x, 2 210 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 211 %val = atomicrmw xor i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 212 store i32 %val, i32 addrspace(1)* %out, align 4 213 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 214 ret void 215} 216 217; define amdgpu_kernel void @atomic_nand_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 218; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 219; %idx.0 = add nsw i32 %tid.x, 2 220; %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 221; %val = atomicrmw nand i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 222; store i32 %val, i32 addrspace(1)* %out, align 4 223; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 224; ret void 225; } 226 227; GCN-LABEL: {{^}}atomic_min_shl_base_lds_0: 228; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 229; GCN: ds_min_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 230; GCN: s_endpgm 231define amdgpu_kernel void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 232 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 233 %idx.0 = add nsw i32 %tid.x, 2 234 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 235 %val = atomicrmw min i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 236 store i32 %val, i32 addrspace(1)* %out, align 4 237 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 238 ret void 239} 240 241; GCN-LABEL: {{^}}atomic_max_shl_base_lds_0: 242; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 243; GCN: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 244; GCN: s_endpgm 245define amdgpu_kernel void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 246 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 247 %idx.0 = add nsw i32 %tid.x, 2 248 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 249 %val = atomicrmw max i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 250 store i32 %val, i32 addrspace(1)* %out, align 4 251 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 252 ret void 253} 254 255; GCN-LABEL: {{^}}atomic_umin_shl_base_lds_0: 256; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 257; GCN: ds_min_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 258; GCN: s_endpgm 259define amdgpu_kernel void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 260 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 261 %idx.0 = add nsw i32 %tid.x, 2 262 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 263 %val = atomicrmw umin i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 264 store i32 %val, i32 addrspace(1)* %out, align 4 265 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 266 ret void 267} 268 269; GCN-LABEL: {{^}}atomic_umax_shl_base_lds_0: 270; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} 271; GCN: ds_max_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 272; GCN: s_endpgm 273define amdgpu_kernel void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { 274 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 275 %idx.0 = add nsw i32 %tid.x, 2 276 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 277 %val = atomicrmw umax i32 addrspace(3)* %arrayidx0, i32 3 seq_cst 278 store i32 %val, i32 addrspace(1)* %out, align 4 279 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4 280 ret void 281} 282 283; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_lds: 284; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 285; GCN: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:32 286 287; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 288; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} offset:64 289define void @shl_add_ptr_combine_2use_lds(i32 %idx) #0 { 290 %idx.add = add nuw i32 %idx, 4 291 %shl0 = shl i32 %idx.add, 3 292 %shl1 = shl i32 %idx.add, 4 293 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)* 294 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)* 295 store volatile i32 9, i32 addrspace(3)* %ptr0 296 store volatile i32 10, i32 addrspace(3)* %ptr1 297 ret void 298} 299 300; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_lds_offset: 301; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 302; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 303; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:65528 304; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD1:v[0-9]+]], vcc, 0x1fff0, [[SCALE1]] 305; GCN: ds_write_b32 [[ADD1]], v{{[0-9]+$}} 306define void @shl_add_ptr_combine_2use_max_lds_offset(i32 %idx) #0 { 307 %idx.add = add nuw i32 %idx, 8191 308 %shl0 = shl i32 %idx.add, 3 309 %shl1 = shl i32 %idx.add, 4 310 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)* 311 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)* 312 store volatile i32 9, i32 addrspace(3)* %ptr0 313 store volatile i32 10, i32 addrspace(3)* %ptr1 314 ret void 315} 316 317; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_lds_offset: 318; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1000, v0 319; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]] 320; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]] 321; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+$}} 322; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+$}} 323define void @shl_add_ptr_combine_2use_both_max_lds_offset(i32 %idx) #0 { 324 %idx.add = add nuw i32 %idx, 4096 325 %shl0 = shl i32 %idx.add, 4 326 %shl1 = shl i32 %idx.add, 5 327 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)* 328 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)* 329 store volatile i32 9, i32 addrspace(3)* %ptr0 330 store volatile i32 10, i32 addrspace(3)* %ptr1 331 ret void 332} 333 334; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_private: 335; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 2, v0 336; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen offset:16 337 338; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 3, v0 339; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], 0 offen offset:32 340define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 { 341 %idx = zext i16 %idx.arg to i32 342 %idx.add = add nuw i32 %idx, 4 343 %shl0 = shl i32 %idx.add, 2 344 %shl1 = shl i32 %idx.add, 3 345 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)* 346 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)* 347 store volatile i32 9, i32 addrspace(5)* %ptr0 348 store volatile i32 10, i32 addrspace(5)* %ptr1 349 ret void 350} 351 352; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_private_offset: 353; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 354; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 355; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen offset:4088 356; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1ff0, [[SCALE1]] 357; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[0:3], 0 offen{{$}} 358define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #0 { 359 %idx = zext i16 %idx.arg to i32 360 %idx.add = add nuw i32 %idx, 511 361 %shl0 = shl i32 %idx.add, 3 362 %shl1 = shl i32 %idx.add, 4 363 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)* 364 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)* 365 store volatile i32 9, i32 addrspace(5)* %ptr0 366 store volatile i32 10, i32 addrspace(5)* %ptr1 367 ret void 368} 369; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_private_offset: 370; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x100, v0 371; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]] 372; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]] 373; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen{{$}} 374; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], 0 offen{{$}} 375define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 { 376 %idx = zext i16 %idx.arg to i32 377 %idx.add = add nuw i32 %idx, 256 378 %shl0 = shl i32 %idx.add, 4 379 %shl1 = shl i32 %idx.add, 5 380 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)* 381 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)* 382 store volatile i32 9, i32 addrspace(5)* %ptr0 383 store volatile i32 10, i32 addrspace(5)* %ptr1 384 ret void 385} 386 387; FIXME: This or should fold into an offset on the write 388; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds: 389; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 390; GCN: v_or_b32_e32 [[SCALE1:v[0-9]+]], 32, [[SCALE0]] 391; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} 392 393; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 394; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} offset:64 395define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 { 396 %idx.add = or i32 %idx, 4 397 %shl0 = shl i32 %idx.add, 3 398 %shl1 = shl i32 %idx.add, 4 399 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)* 400 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)* 401 store volatile i32 9, i32 addrspace(3)* %ptr0 402 store volatile i32 10, i32 addrspace(3)* %ptr1 403 ret void 404} 405 406; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_max_lds_offset: 407; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 408; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 409; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:65528 410; GCN-DAG: v_or_b32_e32 [[ADD1:v[0-9]+]], 0x1fff0, [[SCALE1]] 411; GCN: ds_write_b32 [[ADD1]], v{{[0-9]+$}} 412define void @shl_or_ptr_combine_2use_max_lds_offset(i32 %idx) #0 { 413 %idx.add = or i32 %idx, 8191 414 %shl0 = shl i32 %idx.add, 3 415 %shl1 = shl i32 %idx.add, 4 416 %ptr0 = inttoptr i32 %shl0 to i32 addrspace(3)* 417 %ptr1 = inttoptr i32 %shl1 to i32 addrspace(3)* 418 store volatile i32 9, i32 addrspace(3)* %ptr0 419 store volatile i32 10, i32 addrspace(3)* %ptr1 420 ret void 421} 422 423attributes #0 = { nounwind } 424attributes #1 = { nounwind readnone } 425