1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx1010 -amdgpu-opt-vgpr-liverange=true -stop-after=si-opt-vgpr-liverange -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4; a normal if-else 5define amdgpu_ps float @else1(i32 %z, float %v) #0 { 6 ; SI-LABEL: name: else1 7 ; SI: bb.0.main_body: 8 ; SI: successors: %bb.3(0x40000000), %bb.1(0x40000000) 9 ; SI: liveins: $vgpr0, $vgpr1 10 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1 11 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 12 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec 13 ; SI: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 14 ; SI: S_BRANCH %bb.3 15 ; SI: bb.1.Flow: 16 ; SI: successors: %bb.2(0x40000000), %bb.4(0x40000000) 17 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %13:vgpr_32, %bb.0, %4, %bb.3 18 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, undef %15:vgpr_32, %bb.3 19 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 20 ; SI: S_BRANCH %bb.2 21 ; SI: bb.2.if: 22 ; SI: successors: %bb.4(0x80000000) 23 ; SI: %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], [[PHI1]], implicit $mode, implicit $exec 24 ; SI: S_BRANCH %bb.4 25 ; SI: bb.3.else: 26 ; SI: successors: %bb.1(0x80000000) 27 ; SI: %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, killed [[COPY]], implicit $mode, implicit $exec 28 ; SI: S_BRANCH %bb.1 29 ; SI: bb.4.end: 30 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2 31 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec 32 ; SI: $vgpr0 = COPY killed [[PHI2]] 33 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0 34main_body: 35 %cc = icmp sgt i32 %z, 5 36 br i1 %cc, label %if, label %else 37 38if: 39 %v.if = fmul float %v, 2.0 40 br label %end 41 42else: 43 %v.else = fmul float %v, 3.0 44 br label %end 45 46end: 47 %r = phi float [ %v.if, %if ], [ %v.else, %else ] 48 ret float %r 49} 50 51 52; %v was used after if-else 53define amdgpu_ps float @else2(i32 %z, float %v) #0 { 54 ; SI-LABEL: name: else2 55 ; SI: bb.0.main_body: 56 ; SI: successors: %bb.3(0x40000000), %bb.1(0x40000000) 57 ; SI: liveins: $vgpr0, $vgpr1 58 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1 59 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 60 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY1]], implicit $exec 61 ; SI: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 62 ; SI: S_BRANCH %bb.3 63 ; SI: bb.1.Flow: 64 ; SI: successors: %bb.2(0x40000000), %bb.4(0x40000000) 65 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %15:vgpr_32, %bb.0, %4, %bb.3 66 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 67 ; SI: S_BRANCH %bb.2 68 ; SI: bb.2.if: 69 ; SI: successors: %bb.4(0x80000000) 70 ; SI: %3:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[COPY]], [[COPY]], implicit $mode, implicit $exec 71 ; SI: S_BRANCH %bb.4 72 ; SI: bb.3.else: 73 ; SI: successors: %bb.1(0x80000000) 74 ; SI: %4:vgpr_32 = nofpexcept V_MUL_F32_e32 1077936128, [[COPY]], implicit $mode, implicit $exec 75 ; SI: S_BRANCH %bb.1 76 ; SI: bb.4.end: 77 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.1, %3, %bb.2 78 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, %3, %bb.2 79 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec 80 ; SI: %14:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI1]], killed [[PHI2]], implicit $mode, implicit $exec 81 ; SI: $vgpr0 = COPY killed %14 82 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0 83main_body: 84 %cc = icmp sgt i32 %z, 5 85 br i1 %cc, label %if, label %else 86 87if: 88 %v.if = fmul float %v, 2.0 89 br label %end 90 91else: 92 %v.else = fmul float %v, 3.0 93 br label %end 94 95end: 96 %r0 = phi float [ %v.if, %if ], [ %v, %else ] 97 %r1 = phi float [ %v.if, %if ], [ %v.else, %else ] 98 %r2 = fadd float %r0, %r1 99 ret float %r2 100} 101 102; if-else inside loop, %x can be optimized, but %v cannot be. 103define amdgpu_ps float @else3(i32 %z, float %v, i32 inreg %bound, i32 %x0) #0 { 104 ; SI-LABEL: name: else3 105 ; SI: bb.0.entry: 106 ; SI: successors: %bb.1(0x80000000) 107 ; SI: liveins: $vgpr0, $vgpr1, $sgpr0, $vgpr2 108 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2 109 ; SI: [[COPY1:%[0-9]+]]:sgpr_32 = COPY killed $sgpr0 110 ; SI: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1 111 ; SI: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 112 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY3]], implicit $exec 113 ; SI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 114 ; SI: bb.1.for.body: 115 ; SI: successors: %bb.4(0x40000000), %bb.2(0x40000000) 116 ; SI: [[PHI:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %14, %bb.5 117 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %13, %bb.5 118 ; SI: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[V_CMP_GT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 119 ; SI: S_BRANCH %bb.4 120 ; SI: bb.2.Flow: 121 ; SI: successors: %bb.3(0x40000000), %bb.5(0x40000000) 122 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI undef %34:vgpr_32, %bb.1, %10, %bb.4 123 ; SI: [[PHI3:%[0-9]+]]:vgpr_32 = PHI undef %35:vgpr_32, %bb.1, %9, %bb.4 124 ; SI: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[PHI1]], %bb.1, undef %38:vgpr_32, %bb.4 125 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 126 ; SI: S_BRANCH %bb.3 127 ; SI: bb.3.if: 128 ; SI: successors: %bb.5(0x80000000) 129 ; SI: %7:vgpr_32 = nofpexcept V_MUL_F32_e32 [[PHI]], [[COPY2]], implicit $mode, implicit $exec 130 ; SI: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 1, killed [[PHI4]], implicit $exec 131 ; SI: S_BRANCH %bb.5 132 ; SI: bb.4.else: 133 ; SI: successors: %bb.2(0x80000000) 134 ; SI: %9:vgpr_32 = nofpexcept V_MUL_F32_e32 [[COPY2]], [[PHI1]], implicit $mode, implicit $exec 135 ; SI: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 killed [[PHI1]], 3, implicit $exec 136 ; SI: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed [[V_MUL_LO_U32_e64_]] 137 ; SI: S_BRANCH %bb.2 138 ; SI: bb.5.if.end: 139 ; SI: successors: %bb.6(0x04000000), %bb.1(0x7c000000) 140 ; SI: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI3]], %bb.2, %7, %bb.3 141 ; SI: [[PHI6:%[0-9]+]]:vgpr_32 = PHI [[PHI2]], %bb.2, [[V_ADD_U32_e32_]], %bb.3 142 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec 143 ; SI: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 1, [[PHI6]], implicit $exec 144 ; SI: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 killed [[PHI]], 1, implicit-def dead $scc 145 ; SI: S_CMP_LT_I32 [[S_ADD_I32_]], [[COPY1]], implicit-def $scc 146 ; SI: S_CBRANCH_SCC1 %bb.1, implicit killed $scc 147 ; SI: S_BRANCH %bb.6 148 ; SI: bb.6.for.end: 149 ; SI: %33:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI6]], killed [[PHI5]], implicit $mode, implicit $exec 150 ; SI: $vgpr0 = COPY killed %33 151 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0 152entry: 153; %break = icmp sgt i32 %bound, 0 154; br i1 %break, label %for.body, label %for.end 155 br label %for.body 156 157for.body: 158 %i = phi i32 [ 0, %entry ], [ %inc, %if.end ] 159 %x = phi i32 [ %x0, %entry ], [ %xinc, %if.end ] 160 %cc = icmp sgt i32 %z, 5 161 br i1 %cc, label %if, label %else 162 163if: 164 %i.tmp = bitcast i32 %i to float 165 %v.if = fmul float %v, %i.tmp 166 %x.if = add i32 %x, 1 167 br label %if.end 168 169else: 170 %x.tmp = bitcast i32 %x to float 171 %v.else = fmul float %v, %x.tmp 172 %x.else = mul i32 %x, 3 173 br label %if.end 174 175if.end: 176 %v.endif = phi float [ %v.if, %if ], [ %v.else, %else ] 177 %x.endif = phi i32 [ %x.if, %if ], [ %x.else, %else ] 178 179 %xinc = add i32 %x.endif, 1 180 %inc = add i32 %i, 1 181 %cond = icmp slt i32 %inc, %bound 182 br i1 %cond, label %for.body, label %for.end 183 184for.end: 185 %x_float = bitcast i32 %x.endif to float 186 %r = fadd float %x_float, %v.endif 187 ret float %r 188} 189 190; a loop inside an if-else 191define amdgpu_ps float @loop(i32 %z, float %v, i32 inreg %bound, float(float)* %extern_func, float(float)* %extern_func2) #0 { 192 ; SI-LABEL: name: loop 193 ; SI: bb.0.main_body: 194 ; SI: successors: %bb.5(0x40000000), %bb.1(0x40000000) 195 ; SI: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 196 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr5 197 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4 198 ; SI: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3 199 ; SI: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2 200 ; SI: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1 201 ; SI: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 202 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY5]], implicit $exec 203 ; SI: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 204 ; SI: S_BRANCH %bb.5 205 ; SI: bb.1.Flow: 206 ; SI: successors: %bb.2(0x40000000), %bb.8(0x40000000) 207 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %29:vgpr_32, %bb.0, %4, %bb.7 208 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY4]], %bb.0, undef %45:vgpr_32, %bb.7 209 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %47:vgpr_32, %bb.7 210 ; SI: [[PHI3:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %49:vgpr_32, %bb.7 211 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 212 ; SI: S_BRANCH %bb.2 213 ; SI: bb.2.if: 214 ; SI: successors: %bb.3(0x80000000) 215 ; SI: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[PHI2]], %subreg.sub0, killed [[PHI3]], %subreg.sub1 216 ; SI: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo 217 ; SI: bb.3: 218 ; SI: successors: %bb.3(0x40000000), %bb.4(0x40000000) 219 ; SI: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %51:vreg_64, %bb.3, [[REG_SEQUENCE]], %bb.2 220 ; SI: [[PHI5:%[0-9]+]]:vgpr_32 = PHI undef %53:vgpr_32, %bb.3, [[PHI1]], %bb.2 221 ; SI: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec 222 ; SI: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec 223 ; SI: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1 224 ; SI: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], killed [[PHI4]], implicit $exec 225 ; SI: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_]], implicit-def $exec, implicit-def dead $scc, implicit $exec 226 ; SI: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 227 ; SI: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 228 ; SI: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY killed [[COPY6]] 229 ; SI: $vgpr0 = COPY killed [[PHI5]] 230 ; SI: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE1]], 0, csr_amdgpu_highregs, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0 231 ; SI: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 232 ; SI: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 233 ; SI: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc 234 ; SI: SI_WATERFALL_LOOP %bb.3, implicit $exec 235 ; SI: bb.4: 236 ; SI: successors: %bb.8(0x80000000) 237 ; SI: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]] 238 ; SI: [[COPY8:%[0-9]+]]:vgpr_32 = COPY killed [[COPY7]] 239 ; SI: S_BRANCH %bb.8 240 ; SI: bb.5.else: 241 ; SI: successors: %bb.6(0x80000000) 242 ; SI: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0, killed [[COPY]], %subreg.sub1 243 ; SI: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo 244 ; SI: bb.6: 245 ; SI: successors: %bb.6(0x40000000), %bb.7(0x40000000) 246 ; SI: [[PHI6:%[0-9]+]]:vreg_64 = PHI undef %55:vreg_64, %bb.6, [[REG_SEQUENCE2]], %bb.5 247 ; SI: [[PHI7:%[0-9]+]]:vgpr_32 = PHI undef %57:vgpr_32, %bb.6, [[COPY4]], %bb.5 248 ; SI: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI6]].sub0, implicit $exec 249 ; SI: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI6]].sub1, implicit $exec 250 ; SI: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1 251 ; SI: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], killed [[PHI6]], implicit $exec 252 ; SI: [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec 253 ; SI: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 254 ; SI: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 255 ; SI: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY killed [[COPY9]] 256 ; SI: $vgpr0 = COPY killed [[PHI7]] 257 ; SI: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE3]], 0, csr_amdgpu_highregs, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0 258 ; SI: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 259 ; SI: [[COPY10:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 260 ; SI: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_1]], implicit-def dead $scc 261 ; SI: SI_WATERFALL_LOOP %bb.6, implicit $exec 262 ; SI: bb.7: 263 ; SI: successors: %bb.1(0x80000000) 264 ; SI: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_1]] 265 ; SI: [[COPY11:%[0-9]+]]:vgpr_32 = COPY killed [[COPY10]] 266 ; SI: S_BRANCH %bb.1 267 ; SI: bb.8.end: 268 ; SI: [[PHI8:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[COPY8]], %bb.4 269 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec 270 ; SI: $vgpr0 = COPY killed [[PHI8]] 271 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0 272main_body: 273 %cc = icmp sgt i32 %z, 5 274 br i1 %cc, label %if, label %else 275 276if: 277 %v.if = call amdgpu_gfx float %extern_func(float %v) 278 br label %end 279 280else: 281 %v.else = call amdgpu_gfx float %extern_func2(float %v) 282 br label %end 283 284end: 285 %r = phi float [ %v.if, %if ], [ %v.else, %else ] 286 ret float %r 287} 288 289; a loop inside an if-else, but the variable is still in use after the if-else 290define amdgpu_ps float @loop_with_use(i32 %z, float %v, i32 inreg %bound, float(float)* %extern_func, float(float)* %extern_func2) #0 { 291 ; SI-LABEL: name: loop_with_use 292 ; SI: bb.0.main_body: 293 ; SI: successors: %bb.5(0x40000000), %bb.1(0x40000000) 294 ; SI: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 295 ; SI: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr5 296 ; SI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr4 297 ; SI: [[COPY2:%[0-9]+]]:vgpr_32 = COPY killed $vgpr3 298 ; SI: [[COPY3:%[0-9]+]]:vgpr_32 = COPY killed $vgpr2 299 ; SI: [[COPY4:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1 300 ; SI: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 301 ; SI: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_I32_e64 6, killed [[COPY5]], implicit $exec 302 ; SI: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_GT_I32_e64_]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 303 ; SI: S_BRANCH %bb.5 304 ; SI: bb.1.Flow: 305 ; SI: successors: %bb.2(0x40000000), %bb.8(0x40000000) 306 ; SI: [[PHI:%[0-9]+]]:vgpr_32 = PHI undef %30:vgpr_32, %bb.0, %4, %bb.7 307 ; SI: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[COPY3]], %bb.0, undef %46:vgpr_32, %bb.7 308 ; SI: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[COPY2]], %bb.0, undef %48:vgpr_32, %bb.7 309 ; SI: [[SI_ELSE:%[0-9]+]]:sreg_32 = SI_ELSE killed [[SI_IF]], %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec 310 ; SI: S_BRANCH %bb.2 311 ; SI: bb.2.if: 312 ; SI: successors: %bb.3(0x80000000) 313 ; SI: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[PHI1]], %subreg.sub0, killed [[PHI2]], %subreg.sub1 314 ; SI: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo 315 ; SI: bb.3: 316 ; SI: successors: %bb.3(0x40000000), %bb.4(0x40000000) 317 ; SI: [[PHI3:%[0-9]+]]:vreg_64 = PHI undef %50:vreg_64, %bb.3, [[REG_SEQUENCE]], %bb.2 318 ; SI: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI3]].sub0, implicit $exec 319 ; SI: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI3]].sub1, implicit $exec 320 ; SI: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_1]], %subreg.sub1 321 ; SI: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE1]], killed [[PHI3]], implicit $exec 322 ; SI: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_]], implicit-def $exec, implicit-def dead $scc, implicit $exec 323 ; SI: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 324 ; SI: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 325 ; SI: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY killed [[COPY6]] 326 ; SI: $vgpr0 = COPY [[COPY4]] 327 ; SI: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE1]], 0, csr_amdgpu_highregs, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0 328 ; SI: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 329 ; SI: [[COPY7:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 330 ; SI: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc 331 ; SI: SI_WATERFALL_LOOP %bb.3, implicit $exec 332 ; SI: bb.4: 333 ; SI: successors: %bb.8(0x80000000) 334 ; SI: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_]] 335 ; SI: [[COPY8:%[0-9]+]]:vgpr_32 = COPY killed [[COPY7]] 336 ; SI: S_BRANCH %bb.8 337 ; SI: bb.5.else: 338 ; SI: successors: %bb.6(0x80000000) 339 ; SI: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[COPY1]], %subreg.sub0, killed [[COPY]], %subreg.sub1 340 ; SI: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo 341 ; SI: bb.6: 342 ; SI: successors: %bb.6(0x40000000), %bb.7(0x40000000) 343 ; SI: [[PHI4:%[0-9]+]]:vreg_64 = PHI undef %52:vreg_64, %bb.6, [[REG_SEQUENCE2]], %bb.5 344 ; SI: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI4]].sub0, implicit $exec 345 ; SI: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI4]].sub1, implicit $exec 346 ; SI: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_2]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_3]], %subreg.sub1 347 ; SI: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[REG_SEQUENCE3]], killed [[PHI4]], implicit $exec 348 ; SI: [[S_AND_SAVEEXEC_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[V_CMP_EQ_U64_e64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec 349 ; SI: ADJCALLSTACKUP 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 350 ; SI: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 351 ; SI: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY killed [[COPY9]] 352 ; SI: $vgpr0 = COPY [[COPY4]] 353 ; SI: dead $sgpr30_sgpr31 = SI_CALL killed [[REG_SEQUENCE3]], 0, csr_amdgpu_highregs, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $vgpr0, implicit-def $vgpr0 354 ; SI: ADJCALLSTACKDOWN 0, 0, implicit-def dead $scc, implicit-def $sgpr32, implicit $sgpr32 355 ; SI: [[COPY10:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0 356 ; SI: $exec_lo = S_XOR_B32_term $exec_lo, killed [[S_AND_SAVEEXEC_B32_1]], implicit-def dead $scc 357 ; SI: SI_WATERFALL_LOOP %bb.6, implicit $exec 358 ; SI: bb.7: 359 ; SI: successors: %bb.1(0x80000000) 360 ; SI: $exec_lo = S_MOV_B32 killed [[S_MOV_B32_1]] 361 ; SI: [[COPY11:%[0-9]+]]:vgpr_32 = COPY killed [[COPY10]] 362 ; SI: S_BRANCH %bb.1 363 ; SI: bb.8.end: 364 ; SI: [[PHI5:%[0-9]+]]:vgpr_32 = PHI [[PHI]], %bb.1, [[COPY8]], %bb.4 365 ; SI: SI_END_CF killed [[SI_ELSE]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec 366 ; SI: %27:vgpr_32 = nofpexcept V_ADD_F32_e32 killed [[PHI5]], killed [[COPY4]], implicit $mode, implicit $exec 367 ; SI: $vgpr0 = COPY killed %27 368 ; SI: SI_RETURN_TO_EPILOG killed $vgpr0 369main_body: 370 %cc = icmp sgt i32 %z, 5 371 br i1 %cc, label %if, label %else 372 373if: 374 %v.if = call amdgpu_gfx float %extern_func(float %v) 375 br label %end 376 377else: 378 %v.else = call amdgpu_gfx float %extern_func2(float %v) 379 br label %end 380 381end: 382 %r = phi float [ %v.if, %if ], [ %v.else, %else ] 383 %r2 = fadd float %r, %v 384 ret float %r2 385} 386 387attributes #0 = { nounwind } 388