1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 define dso_local arm_aapcs_vfpcc float @insert_after_vdup_1(float* nocapture readonly %a, float* nocapture readonly %b, float %init, i32 %N) { 6 entry: 7 %cmp8.not = icmp eq i32 %N, 0 8 %0 = add i32 %N, 3 9 %1 = lshr i32 %0, 2 10 %2 = shl nuw i32 %1, 2 11 %3 = add i32 %2, -4 12 %4 = lshr i32 %3, 2 13 %5 = add nuw nsw i32 %4, 1 14 br i1 %cmp8.not, label %for.cond.cleanup, label %vector.ph 15 16 vector.ph: ; preds = %entry 17 %6 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %init, i32 0 18 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 19 br label %vector.body 20 21 vector.body: ; preds = %vector.body, %vector.ph 22 %lsr.iv13 = phi float* [ %scevgep14, %vector.body ], [ %b, %vector.ph ] 23 %lsr.iv = phi float* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 24 %vec.phi = phi <4 x float> [ %6, %vector.ph ], [ %13, %vector.body ] 25 %7 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ] 26 %8 = phi i32 [ %N, %vector.ph ], [ %10, %vector.body ] 27 %lsr.iv12 = bitcast float* %lsr.iv to <4 x float>* 28 %lsr.iv1315 = bitcast float* %lsr.iv13 to <4 x float>* 29 %9 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8) 30 %10 = sub i32 %8, 4 31 %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %lsr.iv12, i32 4, <4 x i1> %9, <4 x float> undef) 32 %wide.masked.load11 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %lsr.iv1315, i32 4, <4 x i1> %9, <4 x float> undef) 33 %11 = fmul fast <4 x float> %wide.masked.load11, %wide.masked.load 34 %12 = fadd fast <4 x float> %11, %vec.phi 35 %13 = select <4 x i1> %9, <4 x float> %12, <4 x float> %vec.phi 36 %scevgep = getelementptr float, float* %lsr.iv, i32 4 37 %scevgep14 = getelementptr float, float* %lsr.iv13, i32 4 38 %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1) 39 %15 = icmp ne i32 %14, 0 40 br i1 %15, label %vector.body, label %middle.block 41 42 middle.block: ; preds = %vector.body 43 %16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13) 44 br label %for.cond.cleanup 45 46 for.cond.cleanup: ; preds = %middle.block, %entry 47 %res.0.lcssa = phi float [ %init, %entry ], [ %16, %middle.block ] 48 ret float %res.0.lcssa 49 } 50 51 ; Function Attrs: norecurse nounwind readonly 52 define dso_local arm_aapcs_vfpcc float @insert_after_vdup_2(float* nocapture readonly %a, float* nocapture readonly %b, float %init, i32 %N) local_unnamed_addr #0 { 53 entry: 54 %shr = lshr i32 %N, 2 55 %cmp9.not = icmp eq i32 %shr, 0 56 %0 = add nuw nsw i32 %shr, 3 57 %1 = lshr i32 %0, 2 58 %2 = shl nuw nsw i32 %1, 2 59 %3 = add nsw i32 %2, -4 60 %4 = lshr i32 %3, 2 61 %5 = add nuw nsw i32 %4, 1 62 br i1 %cmp9.not, label %for.cond.cleanup, label %vector.ph 63 64 vector.ph: ; preds = %entry 65 %6 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %init, i32 0 66 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 67 br label %vector.body 68 69 vector.body: ; preds = %vector.body, %vector.ph 70 %lsr.iv14 = phi float* [ %scevgep15, %vector.body ], [ %b, %vector.ph ] 71 %lsr.iv = phi float* [ %scevgep, %vector.body ], [ %a, %vector.ph ] 72 %vec.phi = phi <4 x float> [ %6, %vector.ph ], [ %13, %vector.body ] 73 %7 = phi i32 [ %start, %vector.ph ], [ %14, %vector.body ] 74 %8 = phi i32 [ %shr, %vector.ph ], [ %10, %vector.body ] 75 %lsr.iv13 = bitcast float* %lsr.iv to <4 x float>* 76 %lsr.iv1416 = bitcast float* %lsr.iv14 to <4 x float>* 77 %9 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %8) 78 %10 = sub i32 %8, 4 79 %wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %lsr.iv13, i32 4, <4 x i1> %9, <4 x float> undef) 80 %wide.masked.load12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %lsr.iv1416, i32 4, <4 x i1> %9, <4 x float> undef) 81 %11 = fmul fast <4 x float> %wide.masked.load12, %wide.masked.load 82 %12 = fadd fast <4 x float> %11, %vec.phi 83 %13 = select <4 x i1> %9, <4 x float> %12, <4 x float> %vec.phi 84 %scevgep = getelementptr float, float* %lsr.iv, i32 4 85 %scevgep15 = getelementptr float, float* %lsr.iv14, i32 4 86 %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %7, i32 1) 87 %15 = icmp ne i32 %14, 0 88 br i1 %15, label %vector.body, label %middle.block 89 90 middle.block: ; preds = %vector.body 91 %16 = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 0.000000e+00, <4 x float> %13) 92 br label %for.cond.cleanup 93 94 for.cond.cleanup: ; preds = %middle.block, %entry 95 %res.0.lcssa = phi float [ %init, %entry ], [ %16, %middle.block ] 96 ret float %res.0.lcssa 97 } 98 99 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) 100 declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) 101 declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>) 102 declare i32 @llvm.start.loop.iterations.i32(i32) 103 declare i32 @llvm.loop.decrement.reg.i32(i32, i32) 104 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 105 106... 107--- 108name: insert_after_vdup_1 109alignment: 4 110tracksRegLiveness: true 111registers: [] 112liveins: 113 - { reg: '$r0', virtual-reg: '' } 114 - { reg: '$r1', virtual-reg: '' } 115 - { reg: '$s0', virtual-reg: '' } 116 - { reg: '$r2', virtual-reg: '' } 117frameInfo: 118 stackSize: 8 119 offsetAdjustment: 0 120 maxAlignment: 4 121 localFrameSize: 0 122 savePoint: '' 123 restorePoint: '' 124fixedStack: [] 125stack: 126 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 127 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 128 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 129 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 130 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 131 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 132callSites: [] 133constants: 134 - id: 0 135 value: 'float 0.000000e+00' 136 alignment: 4 137 isTargetSpecific: false 138machineFunctionInfo: {} 139body: | 140 ; CHECK-LABEL: name: insert_after_vdup_1 141 ; CHECK: bb.0.entry: 142 ; CHECK: successors: %bb.1(0x80000000) 143 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7, $s0 144 ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 145 ; CHECK: t2IT 0, 8, implicit-def $itstate 146 ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 147 ; CHECK: bb.1.vector.ph: 148 ; CHECK: successors: %bb.2(0x80000000) 149 ; CHECK: liveins: $lr, $r0, $r1, $r2, $s0 150 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 151 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 152 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 153 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 154 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 155 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 156 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 157 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 158 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 159 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 160 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 161 ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 162 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 163 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 164 ; CHECK: bb.2.vector.body: 165 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 166 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 167 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 168 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 169 ; CHECK: MVE_VPST 2, implicit $vpr 170 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv12, align 4) 171 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1315, align 4) 172 ; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr 173 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 174 ; CHECK: bb.3.middle.block: 175 ; CHECK: liveins: $q1 176 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 177 ; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 178 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 179 ; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 180 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 181 ; CHECK: bb.4 (align 4): 182 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 183 bb.0.entry: 184 successors: %bb.1(0x80000000) 185 liveins: $r0, $r1, $r2, $s0, $lr 186 187 tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 188 t2IT 0, 8, implicit-def $itstate 189 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 190 191 bb.1.vector.ph: 192 successors: %bb.2(0x80000000) 193 liveins: $r0, $r1, $r2, $s0, $lr 194 195 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 196 frame-setup CFI_INSTRUCTION def_cfa_offset 8 197 frame-setup CFI_INSTRUCTION offset $lr, -4 198 frame-setup CFI_INSTRUCTION offset $r7, -8 199 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 200 frame-setup CFI_INSTRUCTION def_cfa_register $r7 201 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 202 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 203 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 204 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 205 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 206 renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 207 $lr = t2DoLoopStart renamable $lr 208 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 209 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 210 211 bb.2.vector.body: 212 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 213 liveins: $lr, $q1, $r0, $r1, $r2 214 215 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 216 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 217 renamable $lr = t2LoopDec killed renamable $lr, 1 218 MVE_VPST 2, implicit $vpr 219 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv12, align 4) 220 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1315, align 4) 221 renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr 222 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 223 tB %bb.3, 14 /* CC::al */, $noreg 224 225 bb.3.middle.block: 226 liveins: $q1 227 228 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 229 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 230 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 231 $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 232 tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 233 234 bb.4 (align 4): 235 CONSTPOOL_ENTRY 0, %const.0, 4 236 237... 238--- 239name: insert_after_vdup_2 240alignment: 4 241tracksRegLiveness: true 242registers: [] 243liveins: 244 - { reg: '$r0', virtual-reg: '' } 245 - { reg: '$r1', virtual-reg: '' } 246 - { reg: '$s0', virtual-reg: '' } 247 - { reg: '$r2', virtual-reg: '' } 248frameInfo: 249 stackSize: 8 250 offsetAdjustment: 0 251 maxAlignment: 4 252 savePoint: '' 253 restorePoint: '' 254fixedStack: [] 255stack: 256 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 257 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true, 258 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 259 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 260 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 261 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 262callSites: [] 263constants: 264 - id: 0 265 value: 'float 0.000000e+00' 266 alignment: 4 267 isTargetSpecific: false 268machineFunctionInfo: {} 269body: | 270 ; CHECK-LABEL: name: insert_after_vdup_2 271 ; CHECK: bb.0.entry: 272 ; CHECK: successors: %bb.1(0x80000000) 273 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7, $s0 274 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 275 ; CHECK: t2CMPrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, implicit-def $cpsr 276 ; CHECK: t2IT 0, 8, implicit-def $itstate 277 ; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 278 ; CHECK: bb.1.vector.ph: 279 ; CHECK: successors: %bb.2(0x80000000) 280 ; CHECK: liveins: $lr, $r0, $r1, $r2, $s0 281 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 282 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 283 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 284 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 285 ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 286 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 287 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg 288 ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 289 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 290 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 291 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 292 ; CHECK: renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 293 ; CHECK: renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 294 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 295 ; CHECK: renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg 296 ; CHECK: $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 297 ; CHECK: bb.2.vector.body: 298 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 299 ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 300 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 301 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 302 ; CHECK: MVE_VPST 2, implicit $vpr 303 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) 304 ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) 305 ; CHECK: renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr 306 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 307 ; CHECK: bb.3.middle.block: 308 ; CHECK: liveins: $q1 309 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 310 ; CHECK: renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit killed $q1 311 ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 312 ; CHECK: $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 313 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 314 ; CHECK: bb.4 (align 4): 315 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4 316 bb.0.entry: 317 successors: %bb.1(0x80000000) 318 liveins: $r0, $r1, $r2, $s0, $lr 319 320 renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 321 t2CMPrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, implicit-def $cpsr 322 t2IT 0, 8, implicit-def $itstate 323 tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $s0, implicit killed $itstate 324 325 bb.1.vector.ph: 326 successors: %bb.2(0x80000000) 327 liveins: $r0, $r1, $r2, $s0, $lr 328 329 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $lr, implicit-def $sp, implicit $sp 330 frame-setup CFI_INSTRUCTION def_cfa_offset 8 331 frame-setup CFI_INSTRUCTION offset $lr, -4 332 frame-setup CFI_INSTRUCTION offset $r7, -8 333 $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg 334 frame-setup CFI_INSTRUCTION def_cfa_register $r7 335 renamable $r3, dead $cpsr = tMOVi8 3, 14 /* CC::al */, $noreg 336 renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg 337 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 338 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 339 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 340 renamable $lr = t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 341 renamable $r3 = tLDRpci %const.0, 14 /* CC::al */, $noreg :: (load (s32) from constant-pool) 342 $lr = t2DoLoopStart renamable $lr 343 renamable $q1 = MVE_VDUP32 killed renamable $r3, 0, $noreg, undef renamable $q1 344 renamable $r2, dead $cpsr = tLSRri killed renamable $r2, 2, 14 /* CC::al */, $noreg 345 $s4 = VMOVS killed $s0, 14 /* CC::al */, $noreg, implicit killed $q1, implicit-def $q1 346 347 bb.2.vector.body: 348 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 349 liveins: $lr, $q1, $r0, $r1, $r2 350 351 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 352 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 353 renamable $lr = t2LoopDec killed renamable $lr, 1 354 MVE_VPST 2, implicit $vpr 355 renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv13, align 4) 356 renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1416, align 4) 357 renamable $q1 = MVE_VFMAf32 killed renamable $q1, killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr 358 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 359 tB %bb.3, 14 /* CC::al */, $noreg 360 361 bb.3.middle.block: 362 liveins: $q1 363 364 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS renamable $s6, renamable $s7, 14 /* CC::al */, $noreg 365 renamable $s2 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s4, killed renamable $s5, 14 /* CC::al */, $noreg, implicit $q1 366 renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s2, killed renamable $s0, 14 /* CC::al */, $noreg 367 $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r7, def $lr 368 tBX_RET 14 /* CC::al */, $noreg, implicit killed $s0 369 370 bb.4 (align 4): 371 CONSTPOOL_ENTRY 0, %const.0, 4 372 373... 374