1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6  target triple = "thumbv8.1m.main"
7
8  define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
9  entry:
10    %scevgep = getelementptr i32, i32* %q, i32 -1
11    %scevgep3 = getelementptr i32, i32* %p, i32 -1
12    %start = call i32 @llvm.start.loop.iterations.i32(i32 %n)
13    br label %preheader
14
15  preheader:
16    br label %while.body
17
18  while.body:                                       ; preds = %while.body, %entry
19    %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %preheader ]
20    %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %preheader ]
21    %0 = phi i32 [ %start, %preheader ], [ %2, %while.body ]
22    %scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
23    %scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
24    %1 = load i32, i32* %scevgep6, align 4
25    store i32 %1, i32* %scevgep2, align 4
26    %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
27    %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
28    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
29    %3 = icmp ne i32 %2, 0
30    br i1 %3, label %while.body, label %while.end
31
32  while.end:                                        ; preds = %while.body
33    ret i32 0
34  }
35
36  declare i32 @llvm.start.loop.iterations.i32(i32) #0
37  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
38
39  attributes #0 = { noduplicate nounwind }
40  attributes #1 = { nounwind }
41
42...
43---
44name:            do_copy
45alignment:       2
46exposesReturnsTwice: false
47legalized:       false
48regBankSelected: false
49selected:        false
50failedISel:      false
51tracksRegLiveness: true
52hasWinCFI:       false
53registers:       []
54liveins:
55  - { reg: '$r0', virtual-reg: '' }
56  - { reg: '$r1', virtual-reg: '' }
57  - { reg: '$r2', virtual-reg: '' }
58frameInfo:
59  isFrameAddressTaken: false
60  isReturnAddressTaken: false
61  hasStackMap:     false
62  hasPatchPoint:   false
63  stackSize:       8
64  offsetAdjustment: 0
65  maxAlignment:    4
66  adjustsStack:    false
67  hasCalls:        false
68  stackProtector:  ''
69  maxCallFrameSize: 0
70  cvBytesOfCalleeSavedRegisters: 0
71  hasOpaqueSPAdjustment: false
72  hasVAStart:      false
73  hasMustTailInVarArgFunc: false
74  localFrameSize:  0
75  savePoint:       ''
76  restorePoint:    ''
77fixedStack:      []
78stack:
79  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
80      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
81      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
82  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
83      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
84      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
85callSites:       []
86constants:       []
87machineFunctionInfo: {}
88body:             |
89  ; CHECK-LABEL: name: do_copy
90  ; CHECK: bb.0.entry:
91  ; CHECK:   successors: %bb.1(0x80000000)
92  ; CHECK:   liveins: $r0, $r2, $r7
93  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, implicit-def $sp, implicit $sp
94  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
95  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
96  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
97  ; CHECK:   $lr = t2DLS killed $r0
98  ; CHECK:   renamable $r0 = t2SUBri killed renamable $lr, 4, 14 /* CC::al */, $noreg, def dead $cpsr
99  ; CHECK:   renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
100  ; CHECK: bb.1.preheader:
101  ; CHECK:   successors: %bb.2(0x80000000)
102  ; CHECK:   liveins: $r0, $r1
103  ; CHECK:   $lr = tMOVr $r0, 14 /* CC::al */, $noreg
104  ; CHECK: bb.2.while.body:
105  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
106  ; CHECK:   liveins: $lr, $r0, $r1
107  ; CHECK:   renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.scevgep6)
108  ; CHECK:   early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.scevgep2)
109  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
110  ; CHECK: bb.3.while.end:
111  ; CHECK:   $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
112  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
113  bb.0.entry:
114    successors: %bb.1(0x80000000)
115    liveins: $r0, $r1, $r2, $r7, $lr
116
117    frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp
118    frame-setup CFI_INSTRUCTION def_cfa_offset 8
119    frame-setup CFI_INSTRUCTION offset $lr, -4
120    frame-setup CFI_INSTRUCTION offset $r7, -8
121    $lr = t2DoLoopStart $r0
122    renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def $cpsr
123    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
124
125  bb.1.preheader:
126    successors: %bb.2(0x80000000)
127    liveins: $r0, $r1
128    $lr = tMOVr $r0, 14, $noreg
129
130  bb.2.while.body:
131    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
132    liveins: $lr, $r0, $r1
133
134    renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.scevgep6)
135    early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store (s32) into %ir.scevgep2)
136    renamable $lr = t2LoopDec killed renamable $lr, 1
137    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
138    tB %bb.3, 14, $noreg
139
140  bb.3.while.end:
141    $r0, dead $cpsr = tMOVi8 0, 14, $noreg
142    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
143
144...
145