1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s 3 4--- | 5 @_ZL3arr = internal global [10 x i32] [i32 1, i32 2, i32 3, i32 5, i32 5, i32 5, i32 -2, i32 0, i32 -8, i32 -1], align 4 6 @.str = private unnamed_addr constant [5 x i8] c"%d, \00", align 1 7 8 define arm_aapcs_vfpcc void @vpt_block(i32* nocapture %A, i32 %n, i32 %x) { 9 entry: 10 %cmp9 = icmp sgt i32 %n, 0 11 %0 = add i32 %n, 3 12 %1 = lshr i32 %0, 2 13 %2 = shl nuw i32 %1, 2 14 %3 = add i32 %2, -4 15 %4 = lshr i32 %3, 2 16 %5 = add nuw nsw i32 %4, 1 17 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 18 19 vector.ph: ; preds = %entry 20 %sub = sub nsw i32 0, %x 21 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 22 br label %vector.body 23 24 vector.body: ; preds = %vector.body, %vector.ph 25 %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %A, %vector.ph ] 26 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 27 %7 = phi i32 [ %n, %vector.ph ], [ %9, %vector.body ] 28 %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* 29 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 30 %9 = sub i32 %7, 4 31 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef) 32 %10 = insertelement <4 x i32> undef, i32 %x, i32 0 33 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 34 %12 = icmp slt <4 x i32> %wide.masked.load, %11 35 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 36 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 37 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 38 %16 = and <4 x i1> %12, %15 39 %17 = and <4 x i1> %16, %8 40 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17) 41 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4 42 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 43 %19 = icmp ne i32 %18, 0 44 br i1 %19, label %vector.body, label %for.cond.cleanup 45 46 for.cond.cleanup: ; preds = %vector.body, %entry 47 ret void 48 } 49 50 define arm_aapcs_vfpcc void @different_vcpt_reaching_def(i32* nocapture %A, i32 %n, i32 %x) { 51 ; Intentionally left blank - see MIR sequence below. 52 entry: 53 unreachable 54 vector.ph: 55 unreachable 56 vector.body: 57 unreachable 58 for.cond.cleanup: 59 unreachable 60 } 61 62 define arm_aapcs_vfpcc void @different_vcpt_operand(i32* nocapture %A, i32 %n, i32 %x) { 63 ; Intentionally left blank - see MIR sequence below. 64 entry: 65 unreachable 66 vector.ph: 67 unreachable 68 vector.body: 69 unreachable 70 for.cond.cleanup: 71 unreachable 72 } 73 74 define arm_aapcs_vfpcc void @else_vcpt(i32* nocapture %data, i32 %N, i32 %T) { 75 entry: 76 %cmp9 = icmp sgt i32 %N, 0 77 %0 = add i32 %N, 3 78 %1 = lshr i32 %0, 2 79 %2 = shl nuw i32 %1, 2 80 %3 = add i32 %2, -4 81 %4 = lshr i32 %3, 2 82 %5 = add nuw nsw i32 %4, 1 83 br i1 %cmp9, label %vector.ph, label %for.cond.cleanup 84 85 vector.ph: ; preds = %entry 86 %sub = sub nsw i32 0, %T 87 %start = call i32 @llvm.start.loop.iterations.i32(i32 %5) 88 br label %vector.body 89 90 vector.body: ; preds = %vector.body, %vector.ph 91 %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %data, %vector.ph ] 92 %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ] 93 %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ] 94 %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>* 95 %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7) 96 %9 = sub i32 %7, 4 97 %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef) 98 %10 = insertelement <4 x i32> undef, i32 %T, i32 0 99 %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer 100 %12 = icmp slt <4 x i32> %wide.masked.load, %11 101 %13 = insertelement <4 x i32> undef, i32 %sub, i32 0 102 %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer 103 %15 = icmp sgt <4 x i32> %wide.masked.load, %14 104 %16 = or <4 x i1> %12, %15 105 %17 = and <4 x i1> %16, %8 106 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17) 107 %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4 108 %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1) 109 %19 = icmp ne i32 %18, 0 110 br i1 %19, label %vector.body, label %for.cond.cleanup 111 112 for.cond.cleanup: ; preds = %vector.body, %entry 113 ret void 114 } 115 116 define arm_aapcs_vfpcc void @loop_invariant_vpt_operands(i32* nocapture %A, i32 %n, i32 %x) { 117 ; Intentionally left blank - see MIR sequence below. 118 entry: 119 unreachable 120 vector.ph: 121 unreachable 122 vector.body: 123 unreachable 124 for.cond.cleanup: 125 unreachable 126 } 127 128 define arm_aapcs_vfpcc void @vctp_before_vpt(i32* nocapture %A, i32 %n, i32 %x) { 129 ; Intentionally left blank - see MIR sequence below. 130 entry: 131 unreachable 132 vector.ph: 133 unreachable 134 vector.body: 135 unreachable 136 for.cond.cleanup: 137 unreachable 138 } 139 140 define arm_aapcs_vfpcc void @vpt_load_vctp_store(i32* nocapture %A, i32 %n, i32 %x) { 141 ; Intentionally left blank - see MIR sequence below. 142 entry: 143 unreachable 144 vector.ph: 145 unreachable 146 vector.body: 147 unreachable 148 for.cond.cleanup: 149 unreachable 150 } 151 152 define arm_aapcs_vfpcc void @emptyblock() { 153 unreachable 154 } 155 define arm_aapcs_vfpcc void @predvcmp() { 156 unreachable 157 } 158 define arm_aapcs_vfpcc void @predvpt() { 159 unreachable 160 } 161 162 declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) 163 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) 164 declare i32 @llvm.start.loop.iterations.i32(i32) 165 declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) 166 declare <4 x i1> @llvm.arm.mve.vctp32(i32) 167... 168--- 169name: vpt_block 170alignment: 2 171exposesReturnsTwice: false 172legalized: false 173regBankSelected: false 174selected: false 175failedISel: false 176tracksRegLiveness: true 177hasWinCFI: false 178registers: [] 179liveins: 180 - { reg: '$r0', virtual-reg: '' } 181 - { reg: '$r1', virtual-reg: '' } 182 - { reg: '$r2', virtual-reg: '' } 183frameInfo: 184 isFrameAddressTaken: false 185 isReturnAddressTaken: false 186 hasStackMap: false 187 hasPatchPoint: false 188 stackSize: 8 189 offsetAdjustment: 0 190 maxAlignment: 4 191 adjustsStack: false 192 hasCalls: false 193 stackProtector: '' 194 maxCallFrameSize: 0 195 cvBytesOfCalleeSavedRegisters: 0 196 hasOpaqueSPAdjustment: false 197 hasVAStart: false 198 hasMustTailInVarArgFunc: false 199 localFrameSize: 0 200 savePoint: '' 201 restorePoint: '' 202fixedStack: [] 203stack: 204 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 205 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 206 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 207 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 208 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 209 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 210callSites: [] 211constants: [] 212machineFunctionInfo: {} 213body: | 214 ; CHECK-LABEL: name: vpt_block 215 ; CHECK: bb.0.entry: 216 ; CHECK: successors: %bb.1(0x80000000) 217 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 218 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 219 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 220 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 221 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 222 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 223 ; CHECK: t2IT 11, 8, implicit-def $itstate 224 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 225 ; CHECK: bb.1.vector.ph: 226 ; CHECK: successors: %bb.2(0x80000000) 227 ; CHECK: liveins: $r0, $r1, $r2 228 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 229 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 230 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 231 ; CHECK: bb.2.vector.body: 232 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 233 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 234 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 235 ; CHECK: MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr 236 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 237 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 238 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 239 ; CHECK: bb.3.for.cond.cleanup: 240 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 241 bb.0.entry: 242 successors: %bb.1(0x80000000) 243 liveins: $r0, $r1, $r2, $r7, $lr 244 245 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 246 frame-setup CFI_INSTRUCTION def_cfa_offset 8 247 frame-setup CFI_INSTRUCTION offset $lr, -4 248 frame-setup CFI_INSTRUCTION offset $r7, -8 249 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 250 t2IT 11, 8, implicit-def $itstate 251 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 252 253 bb.1.vector.ph: 254 successors: %bb.2(0x80000000) 255 liveins: $r0, $r1, $r2, $r7, $lr 256 257 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 258 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 259 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 260 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 261 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 262 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 263 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 264 $lr = t2DoLoopStart renamable $lr 265 266 bb.2.vector.body: 267 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 268 liveins: $lr, $q0, $r0, $r1, $r2, $r3 269 270 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 271 MVE_VPST 8, implicit $vpr 272 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 273 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 274 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 275 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 276 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 277 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 278 renamable $lr = t2LoopDec killed renamable $lr, 1 279 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 280 tB %bb.3, 14 /* CC::al */, $noreg 281 282 bb.3.for.cond.cleanup: 283 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 284... 285--- 286name: different_vcpt_reaching_def 287alignment: 2 288exposesReturnsTwice: false 289legalized: false 290regBankSelected: false 291selected: false 292failedISel: false 293tracksRegLiveness: true 294hasWinCFI: false 295registers: [] 296liveins: 297 - { reg: '$r0', virtual-reg: '' } 298 - { reg: '$r1', virtual-reg: '' } 299 - { reg: '$r2', virtual-reg: '' } 300frameInfo: 301 isFrameAddressTaken: false 302 isReturnAddressTaken: false 303 hasStackMap: false 304 hasPatchPoint: false 305 stackSize: 8 306 offsetAdjustment: 0 307 maxAlignment: 4 308 adjustsStack: false 309 hasCalls: false 310 stackProtector: '' 311 maxCallFrameSize: 0 312 cvBytesOfCalleeSavedRegisters: 0 313 hasOpaqueSPAdjustment: false 314 hasVAStart: false 315 hasMustTailInVarArgFunc: false 316 localFrameSize: 0 317 savePoint: '' 318 restorePoint: '' 319fixedStack: [] 320stack: 321 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 322 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 323 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 324 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 325 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 326 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 327callSites: [] 328constants: [] 329machineFunctionInfo: {} 330body: | 331 ; CHECK-LABEL: name: different_vcpt_reaching_def 332 ; CHECK: bb.0.entry: 333 ; CHECK: successors: %bb.1(0x80000000) 334 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 335 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 336 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 337 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 338 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 339 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 340 ; CHECK: t2IT 11, 8, implicit-def $itstate 341 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 342 ; CHECK: bb.1.vector.ph: 343 ; CHECK: successors: %bb.2(0x80000000) 344 ; CHECK: liveins: $r0, $r1, $r2 345 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 346 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 347 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 348 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 349 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 350 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 351 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 352 ; CHECK: bb.2.vector.body: 353 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 354 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 355 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 356 ; CHECK: MVE_VPST 8, implicit $vpr 357 ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr 358 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 359 ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 360 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 361 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 362 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 363 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 364 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 365 ; CHECK: bb.3.for.cond.cleanup: 366 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 367 ; 368 ; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main 369 ; VCTP's. 370 ; 371 bb.0.entry: 372 successors: %bb.1(0x80000000) 373 liveins: $r0, $r1, $r2, $r7, $lr 374 375 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 376 frame-setup CFI_INSTRUCTION def_cfa_offset 8 377 frame-setup CFI_INSTRUCTION offset $lr, -4 378 frame-setup CFI_INSTRUCTION offset $r7, -8 379 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 380 t2IT 11, 8, implicit-def $itstate 381 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 382 383 bb.1.vector.ph: 384 successors: %bb.2(0x80000000) 385 liveins: $r0, $r1, $r2, $r7, $lr 386 387 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 388 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 389 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 390 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 391 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 392 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 393 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 394 $lr = t2DoLoopStart renamable $lr 395 396 bb.2.vector.body: 397 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 398 liveins: $lr, $q0, $r0, $r1, $r2, $r3 399 400 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 401 MVE_VPST 8, implicit $vpr 402 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr 403 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 404 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 405 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 406 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 407 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 408 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 409 renamable $lr = t2LoopDec killed renamable $lr, 1 410 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 411 tB %bb.3, 14 /* CC::al */, $noreg 412 413 bb.3.for.cond.cleanup: 414 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 415... 416--- 417name: different_vcpt_operand 418alignment: 2 419exposesReturnsTwice: false 420legalized: false 421regBankSelected: false 422selected: false 423failedISel: false 424tracksRegLiveness: true 425hasWinCFI: false 426registers: [] 427liveins: 428 - { reg: '$r0', virtual-reg: '' } 429 - { reg: '$r1', virtual-reg: '' } 430 - { reg: '$r2', virtual-reg: '' } 431frameInfo: 432 isFrameAddressTaken: false 433 isReturnAddressTaken: false 434 hasStackMap: false 435 hasPatchPoint: false 436 stackSize: 8 437 offsetAdjustment: 0 438 maxAlignment: 4 439 adjustsStack: false 440 hasCalls: false 441 stackProtector: '' 442 maxCallFrameSize: 0 443 cvBytesOfCalleeSavedRegisters: 0 444 hasOpaqueSPAdjustment: false 445 hasVAStart: false 446 hasMustTailInVarArgFunc: false 447 localFrameSize: 0 448 savePoint: '' 449 restorePoint: '' 450fixedStack: [] 451stack: 452 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 453 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 454 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 455 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 456 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 457 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 458callSites: [] 459constants: [] 460machineFunctionInfo: {} 461body: | 462 ; CHECK-LABEL: name: different_vcpt_operand 463 ; CHECK: bb.0.entry: 464 ; CHECK: successors: %bb.1(0x80000000) 465 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 466 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 467 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 468 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 469 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 470 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 471 ; CHECK: t2IT 11, 8, implicit-def $itstate 472 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 473 ; CHECK: bb.1.vector.ph: 474 ; CHECK: successors: %bb.2(0x80000000) 475 ; CHECK: liveins: $r0, $r1, $r2 476 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 477 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 478 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 479 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 480 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 481 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 482 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 483 ; CHECK: bb.2.vector.body: 484 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 485 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 486 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 487 ; CHECK: MVE_VPST 8, implicit $vpr 488 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 489 ; CHECK: MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 490 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 491 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 492 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 493 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 494 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 495 ; CHECK: bb.3.for.cond.cleanup: 496 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 497 ; 498 ; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's. 499 ; 500 bb.0.entry: 501 successors: %bb.1(0x80000000) 502 liveins: $r0, $r1, $r2, $r7, $lr 503 504 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 505 frame-setup CFI_INSTRUCTION def_cfa_offset 8 506 frame-setup CFI_INSTRUCTION offset $lr, -4 507 frame-setup CFI_INSTRUCTION offset $r7, -8 508 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 509 t2IT 11, 8, implicit-def $itstate 510 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 511 512 bb.1.vector.ph: 513 successors: %bb.2(0x80000000) 514 liveins: $r0, $r1, $r2, $r7, $lr 515 516 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 517 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 518 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 519 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 520 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 521 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 522 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 523 $lr = t2DoLoopStart renamable $lr 524 525 bb.2.vector.body: 526 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 527 liveins: $lr, $q0, $r0, $r1, $r2, $r3 528 529 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 530 MVE_VPST 8, implicit $vpr 531 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 532 MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr 533 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 534 renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr 535 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 536 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 537 renamable $lr = t2LoopDec killed renamable $lr, 1 538 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 539 tB %bb.3, 14 /* CC::al */, $noreg 540 541 bb.3.for.cond.cleanup: 542 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 543... 544--- 545name: else_vcpt 546alignment: 2 547exposesReturnsTwice: false 548legalized: false 549regBankSelected: false 550selected: false 551failedISel: false 552tracksRegLiveness: true 553hasWinCFI: false 554registers: [] 555liveins: 556 - { reg: '$r0', virtual-reg: '' } 557 - { reg: '$r1', virtual-reg: '' } 558 - { reg: '$r2', virtual-reg: '' } 559frameInfo: 560 isFrameAddressTaken: false 561 isReturnAddressTaken: false 562 hasStackMap: false 563 hasPatchPoint: false 564 stackSize: 8 565 offsetAdjustment: 0 566 maxAlignment: 4 567 adjustsStack: false 568 hasCalls: false 569 stackProtector: '' 570 maxCallFrameSize: 0 571 cvBytesOfCalleeSavedRegisters: 0 572 hasOpaqueSPAdjustment: false 573 hasVAStart: false 574 hasMustTailInVarArgFunc: false 575 localFrameSize: 0 576 savePoint: '' 577 restorePoint: '' 578fixedStack: [] 579stack: 580 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 581 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 582 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 583 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 584 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 585 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 586callSites: [] 587constants: [] 588machineFunctionInfo: {} 589body: | 590 ; CHECK-LABEL: name: else_vcpt 591 ; CHECK: bb.0.entry: 592 ; CHECK: successors: %bb.1(0x80000000) 593 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 594 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 595 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 596 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 597 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 598 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 599 ; CHECK: t2IT 11, 8, implicit-def $itstate 600 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 601 ; CHECK: bb.1.vector.ph: 602 ; CHECK: successors: %bb.2(0x80000000) 603 ; CHECK: liveins: $r0, $r1, $r2 604 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 605 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 606 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 607 ; CHECK: bb.2.vector.body: 608 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 609 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 610 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 611 ; CHECK: MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr 612 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr 613 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr 614 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 615 ; CHECK: bb.3.for.cond.cleanup: 616 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 617 ; 618 ; Test including a else-predicated VCTP. 619 ; 620 bb.0.entry: 621 successors: %bb.1(0x80000000) 622 liveins: $r0, $r1, $r2, $r7, $lr 623 624 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 625 frame-setup CFI_INSTRUCTION def_cfa_offset 8 626 frame-setup CFI_INSTRUCTION offset $lr, -4 627 frame-setup CFI_INSTRUCTION offset $r7, -8 628 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 629 t2IT 11, 8, implicit-def $itstate 630 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 631 632 bb.1.vector.ph: 633 successors: %bb.2(0x80000000) 634 liveins: $r0, $r1, $r2, $r7, $lr 635 636 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 637 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 638 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 639 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 640 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 641 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 642 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 643 $lr = t2DoLoopStart renamable $lr 644 645 bb.2.vector.body: 646 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 647 liveins: $lr, $q0, $r0, $r1, $r2, $r3 648 649 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 650 MVE_VPST 8, implicit $vpr 651 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 652 MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr 653 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr 654 renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr 655 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr 656 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 657 renamable $lr = t2LoopDec killed renamable $lr, 1 658 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 659 tB %bb.3, 14 /* CC::al */, $noreg 660 661 bb.3.for.cond.cleanup: 662 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 663... 664--- 665name: loop_invariant_vpt_operands 666alignment: 2 667exposesReturnsTwice: false 668legalized: false 669regBankSelected: false 670selected: false 671failedISel: false 672tracksRegLiveness: true 673hasWinCFI: false 674registers: [] 675liveins: 676 - { reg: '$r0', virtual-reg: '' } 677 - { reg: '$r1', virtual-reg: '' } 678 - { reg: '$r2', virtual-reg: '' } 679frameInfo: 680 isFrameAddressTaken: false 681 isReturnAddressTaken: false 682 hasStackMap: false 683 hasPatchPoint: false 684 stackSize: 8 685 offsetAdjustment: 0 686 maxAlignment: 4 687 adjustsStack: false 688 hasCalls: false 689 stackProtector: '' 690 maxCallFrameSize: 0 691 cvBytesOfCalleeSavedRegisters: 0 692 hasOpaqueSPAdjustment: false 693 hasVAStart: false 694 hasMustTailInVarArgFunc: false 695 localFrameSize: 0 696 savePoint: '' 697 restorePoint: '' 698fixedStack: [] 699stack: 700 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 701 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 702 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 703 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 704 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 705 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 706callSites: [] 707constants: [] 708machineFunctionInfo: {} 709body: | 710 ; CHECK-LABEL: name: loop_invariant_vpt_operands 711 ; CHECK: bb.0.entry: 712 ; CHECK: successors: %bb.1(0x80000000) 713 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 714 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 715 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 716 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 717 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 718 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 719 ; CHECK: t2IT 11, 8, implicit-def $itstate 720 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 721 ; CHECK: bb.1.vector.ph: 722 ; CHECK: successors: %bb.2(0x80000000) 723 ; CHECK: liveins: $r0, $r1, $r2 724 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 725 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 726 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 727 ; CHECK: bb.2.vector.body: 728 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 729 ; CHECK: liveins: $lr, $q0, $r0, $r2, $r3 730 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg 731 ; CHECK: MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr 732 ; CHECK: renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 733 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 734 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 735 ; CHECK: bb.3.for.cond.cleanup: 736 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 737 bb.0.entry: 738 successors: %bb.1(0x80000000) 739 liveins: $r0, $r1, $r2, $r7, $lr 740 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 741 frame-setup CFI_INSTRUCTION def_cfa_offset 8 742 frame-setup CFI_INSTRUCTION offset $lr, -4 743 frame-setup CFI_INSTRUCTION offset $r7, -8 744 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 745 t2IT 11, 8, implicit-def $itstate 746 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 747 748 bb.1.vector.ph: 749 successors: %bb.2(0x80000000) 750 liveins: $r0, $r1, $r2, $r7, $lr 751 752 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 753 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 754 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 755 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 756 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 757 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 758 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 759 $lr = t2DoLoopStart renamable $lr 760 761 bb.2.vector.body: 762 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 763 liveins: $lr, $q0, $r0, $r1, $r2, $r3 764 765 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 766 MVE_VPST 8, implicit $vpr 767 renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr 768 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr 769 renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr 770 renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr 771 renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr 772 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 773 renamable $lr = t2LoopDec killed renamable $lr, 1 774 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 775 tB %bb.3, 14 /* CC::al */, $noreg 776 777 bb.3.for.cond.cleanup: 778 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 779... 780--- 781name: vctp_before_vpt 782alignment: 2 783exposesReturnsTwice: false 784legalized: false 785regBankSelected: false 786selected: false 787failedISel: false 788tracksRegLiveness: true 789hasWinCFI: false 790registers: [] 791liveins: 792 - { reg: '$r0', virtual-reg: '' } 793 - { reg: '$r1', virtual-reg: '' } 794 - { reg: '$r2', virtual-reg: '' } 795frameInfo: 796 isFrameAddressTaken: false 797 isReturnAddressTaken: false 798 hasStackMap: false 799 hasPatchPoint: false 800 stackSize: 8 801 offsetAdjustment: 0 802 maxAlignment: 4 803 adjustsStack: false 804 hasCalls: false 805 stackProtector: '' 806 maxCallFrameSize: 0 807 cvBytesOfCalleeSavedRegisters: 0 808 hasOpaqueSPAdjustment: false 809 hasVAStart: false 810 hasMustTailInVarArgFunc: false 811 localFrameSize: 0 812 savePoint: '' 813 restorePoint: '' 814fixedStack: [] 815stack: 816 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 817 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 818 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 819 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 820 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 821 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 822callSites: [] 823constants: [] 824machineFunctionInfo: {} 825body: | 826 ; CHECK-LABEL: name: vctp_before_vpt 827 ; CHECK: bb.0.entry: 828 ; CHECK: successors: %bb.1(0x80000000) 829 ; CHECK: liveins: $lr, $r1, $r2, $r7 830 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 831 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 832 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 833 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 834 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 835 ; CHECK: t2IT 11, 8, implicit-def $itstate 836 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 837 ; CHECK: bb.1.vector.ph: 838 ; CHECK: successors: %bb.2(0x80000000) 839 ; CHECK: liveins: $r1, $r2 840 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 841 ; CHECK: renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 842 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 843 ; CHECK: bb.2.vector.body: 844 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 845 ; CHECK: liveins: $lr, $q0, $r2, $r3 846 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr 847 ; CHECK: dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr 848 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 849 ; CHECK: bb.3.for.cond.cleanup: 850 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 851 bb.0.entry: 852 successors: %bb.1(0x80000000) 853 liveins: $r0, $r1, $r2, $r7, $lr 854 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 855 frame-setup CFI_INSTRUCTION def_cfa_offset 8 856 frame-setup CFI_INSTRUCTION offset $lr, -4 857 frame-setup CFI_INSTRUCTION offset $r7, -8 858 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 859 t2IT 11, 8, implicit-def $itstate 860 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 861 862 bb.1.vector.ph: 863 successors: %bb.2(0x80000000) 864 liveins: $r0, $r1, $r2, $r7, $lr 865 866 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 867 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 868 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 869 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 870 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 871 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 872 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 873 $lr = t2DoLoopStart renamable $lr 874 875 bb.2.vector.body: 876 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 877 liveins: $lr, $q0, $r0, $r1, $r2, $r3 878 879 MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr 880 renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr 881 renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg 882 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 883 renamable $lr = t2LoopDec killed renamable $lr, 1 884 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 885 tB %bb.3, 14 /* CC::al */, $noreg 886 887 bb.3.for.cond.cleanup: 888 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 889... 890--- 891name: vpt_load_vctp_store 892alignment: 2 893exposesReturnsTwice: false 894legalized: false 895regBankSelected: false 896selected: false 897failedISel: false 898tracksRegLiveness: true 899hasWinCFI: false 900registers: [] 901liveins: 902 - { reg: '$r0', virtual-reg: '' } 903 - { reg: '$r1', virtual-reg: '' } 904 - { reg: '$r2', virtual-reg: '' } 905frameInfo: 906 isFrameAddressTaken: false 907 isReturnAddressTaken: false 908 hasStackMap: false 909 hasPatchPoint: false 910 stackSize: 8 911 offsetAdjustment: 0 912 maxAlignment: 4 913 adjustsStack: false 914 hasCalls: false 915 stackProtector: '' 916 maxCallFrameSize: 0 917 cvBytesOfCalleeSavedRegisters: 0 918 hasOpaqueSPAdjustment: false 919 hasVAStart: false 920 hasMustTailInVarArgFunc: false 921 localFrameSize: 0 922 savePoint: '' 923 restorePoint: '' 924fixedStack: [] 925stack: 926 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 927 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 928 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 929 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 930 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 931 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 932callSites: [] 933constants: [] 934machineFunctionInfo: {} 935body: | 936 ; CHECK-LABEL: name: vpt_load_vctp_store 937 ; CHECK: bb.0.entry: 938 ; CHECK: successors: %bb.1(0x80000000) 939 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 940 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 941 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 942 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 943 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 944 ; CHECK: tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 945 ; CHECK: t2IT 11, 8, implicit-def $itstate 946 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 947 ; CHECK: bb.1.vector.ph: 948 ; CHECK: successors: %bb.2(0x80000000) 949 ; CHECK: liveins: $r0, $r1, $r2 950 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 951 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 952 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 953 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 954 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 955 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 956 ; CHECK: dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 957 ; CHECK: bb.2.vector.body: 958 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 959 ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2 960 ; CHECK: MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr 961 ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr 962 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr 963 ; CHECK: MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr 964 ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 965 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 966 ; CHECK: bb.3.for.cond.cleanup: 967 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 968 ; 969 ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP. 970 ; 971 bb.0.entry: 972 successors: %bb.1(0x80000000) 973 liveins: $r0, $r1, $r2, $r7, $lr 974 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 975 frame-setup CFI_INSTRUCTION def_cfa_offset 8 976 frame-setup CFI_INSTRUCTION offset $lr, -4 977 frame-setup CFI_INSTRUCTION offset $r7, -8 978 tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 979 t2IT 11, 8, implicit-def $itstate 980 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 981 982 bb.1.vector.ph: 983 successors: %bb.2(0x80000000) 984 liveins: $r0, $r1, $r2, $r7, $lr 985 986 renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg 987 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 988 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 989 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 990 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 991 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 992 renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg 993 $lr = t2DoLoopStart renamable $lr 994 995 bb.2.vector.body: 996 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 997 liveins: $lr, $q0, $r0, $r1, $r2, $r3 998 999 MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr 1000 renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr 1001 renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr 1002 MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr 1003 renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg 1004 renamable $lr = t2LoopDec killed renamable $lr, 1 1005 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 1006 tB %bb.3, 14 /* CC::al */, $noreg 1007 1008 bb.3.for.cond.cleanup: 1009 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1010... 1011--- 1012name: emptyblock 1013tracksRegLiveness: true 1014liveins: 1015 - { reg: '$r0', virtual-reg: '' } 1016 - { reg: '$r1', virtual-reg: '' } 1017 - { reg: '$r2', virtual-reg: '' } 1018stack: 1019 - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 1020 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 1021 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1022 - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1023 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1024 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1025 - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1026 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1027 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1028body: | 1029 ; CHECK-LABEL: name: emptyblock 1030 ; CHECK: bb.0: 1031 ; CHECK: successors: %bb.1(0x50000000), %bb.3(0x30000000) 1032 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1033 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1034 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1035 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1036 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1037 ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 1038 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 12 1039 ; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1040 ; CHECK: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 1041 ; CHECK: bb.1: 1042 ; CHECK: successors: %bb.2(0x80000000) 1043 ; CHECK: liveins: $r0, $r1, $r2 1044 ; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1045 ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr 1046 ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 1047 ; CHECK: renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg 1048 ; CHECK: renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg 1049 ; CHECK: $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg 1050 ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 1051 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r0 1052 ; CHECK: bb.2 (align 4): 1053 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1054 ; CHECK: liveins: $lr, $q0, $r1 1055 ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 1056 ; CHECK: MVE_VPST 8, implicit $vpr 1057 ; CHECK: renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1058 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 1059 ; CHECK: bb.3: 1060 ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg 1061 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 1062 bb.0: 1063 successors: %bb.1(0x50000000), %bb.3(0x30000000) 1064 liveins: $r0, $r1, $r2, $r7, $lr 1065 1066 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1067 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1068 frame-setup CFI_INSTRUCTION offset $lr, -4 1069 frame-setup CFI_INSTRUCTION offset $r7, -8 1070 $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg 1071 frame-setup CFI_INSTRUCTION def_cfa_offset 12 1072 tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1073 tBcc %bb.3, 11 /* CC::lt */, killed $cpsr 1074 1075 bb.1: 1076 successors: %bb.2(0x80000000) 1077 liveins: $r0, $r1, $r2 1078 1079 tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr 1080 renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr 1081 renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg 1082 renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 1083 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1084 renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg 1085 renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg 1086 renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1087 renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg 1088 renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg 1089 $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg 1090 VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0) 1091 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0 1092 1093 bb.2 (align 4): 1094 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1095 liveins: $lr, $q0, $r0, $r1 1096 1097 renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0) 1098 MVE_VPST 8, implicit $vpr 1099 renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr 1100 renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg 1101 MVE_VPST 8, implicit $vpr 1102 renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1103 renamable $lr = t2LoopDec killed renamable $lr, 1 1104 t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr 1105 tB %bb.3, 14 /* CC::al */, $noreg 1106 1107 bb.3: 1108 $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg 1109 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0 1110... 1111--- 1112name: predvcmp 1113alignment: 8 1114tracksRegLiveness: true 1115liveins: 1116 - { reg: '$r0', virtual-reg: '' } 1117 - { reg: '$r1', virtual-reg: '' } 1118 - { reg: '$r2', virtual-reg: '' } 1119stack: 1120 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1121 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1122 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1123 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1124 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1125 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1126constants: 1127 - id: 0 1128 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 1129 alignment: 8 1130 isTargetSpecific: false 1131body: | 1132 ; CHECK-LABEL: name: predvcmp 1133 ; CHECK: bb.0: 1134 ; CHECK: successors: %bb.1(0x80000000) 1135 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1136 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1137 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1138 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1139 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1140 ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1141 ; CHECK: t2IT 11, 8, implicit-def $itstate 1142 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1143 ; CHECK: bb.1: 1144 ; CHECK: successors: %bb.2(0x80000000) 1145 ; CHECK: liveins: $r0, $r1, $r2 1146 ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1147 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 1148 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) 1149 ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 1150 ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 1151 ; CHECK: bb.2 (align 4): 1152 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1153 ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1 1154 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1155 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1156 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 1157 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 1158 ; CHECK: bb.3: 1159 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1160 ; CHECK: bb.4 (align 8): 1161 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 1162 bb.0: 1163 successors: %bb.1(0x80000000) 1164 liveins: $r0, $r1, $r2, $r7, $lr 1165 1166 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1167 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1168 frame-setup CFI_INSTRUCTION offset $lr, -4 1169 frame-setup CFI_INSTRUCTION offset $r7, -8 1170 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1171 t2IT 11, 8, implicit-def $itstate 1172 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1173 1174 bb.1: 1175 successors: %bb.2(0x80000000) 1176 liveins: $r0, $r1, $r2 1177 1178 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1179 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1180 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1181 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 1182 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) 1183 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1184 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1185 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1186 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 1187 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 1188 1189 bb.2 (align 4): 1190 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1191 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1192 1193 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg 1194 MVE_VPST 4, implicit $vpr 1195 renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr 1196 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1197 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1198 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 1199 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr 1200 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1201 tB %bb.3, 14 /* CC::al */, $noreg 1202 1203 bb.3: 1204 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1205 1206 bb.4 (align 8): 1207 CONSTPOOL_ENTRY 0, %const.0, 16 1208 1209... 1210--- 1211name: predvpt 1212alignment: 8 1213tracksRegLiveness: true 1214liveins: 1215 - { reg: '$r0', virtual-reg: '' } 1216 - { reg: '$r1', virtual-reg: '' } 1217 - { reg: '$r2', virtual-reg: '' } 1218stack: 1219 - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 1220 stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 1221 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1222 - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 1223 stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 1224 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 1225constants: 1226 - id: 0 1227 value: '<4 x i32> <i32 0, i32 1, i32 2, i32 3>' 1228 alignment: 8 1229 isTargetSpecific: false 1230body: | 1231 ; CHECK-LABEL: name: predvpt 1232 ; CHECK: bb.0: 1233 ; CHECK: successors: %bb.1(0x80000000) 1234 ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 1235 ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1236 ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 1237 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 1238 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 1239 ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1240 ; CHECK: t2IT 11, 8, implicit-def $itstate 1241 ; CHECK: frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1242 ; CHECK: bb.1: 1243 ; CHECK: successors: %bb.2(0x80000000) 1244 ; CHECK: liveins: $r0, $r1, $r2 1245 ; CHECK: renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1246 ; CHECK: renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1247 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1248 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 1249 ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) 1250 ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1251 ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1252 ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1253 ; CHECK: renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 1254 ; CHECK: bb.2 (align 4): 1255 ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1256 ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1257 ; CHECK: MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1258 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr 1259 ; CHECK: MVE_VPST 8, implicit $vpr 1260 ; CHECK: renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1261 ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1262 ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 1263 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 1264 ; CHECK: bb.3: 1265 ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1266 ; CHECK: bb.4 (align 8): 1267 ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 1268 bb.0: 1269 successors: %bb.1(0x80000000) 1270 liveins: $r0, $r1, $r2, $r7, $lr 1271 1272 frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp 1273 frame-setup CFI_INSTRUCTION def_cfa_offset 8 1274 frame-setup CFI_INSTRUCTION offset $lr, -4 1275 frame-setup CFI_INSTRUCTION offset $r7, -8 1276 tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr 1277 t2IT 11, 8, implicit-def $itstate 1278 frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate 1279 1280 bb.1: 1281 successors: %bb.2(0x80000000) 1282 liveins: $r0, $r1, $r2 1283 1284 renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg 1285 renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg 1286 renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg 1287 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 1288 renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg :: (load (s128) from constant-pool, align 8) 1289 renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg 1290 renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 1291 renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg 1292 renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, undef renamable $q2 1293 renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2 1294 1295 bb.2 (align 4): 1296 successors: %bb.2(0x7c000000), %bb.3(0x04000000) 1297 liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2 1298 1299 MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr 1300 renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr 1301 MVE_VPST 8, implicit $vpr 1302 renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr :: (store (s128), align 4) 1303 renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg 1304 renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, undef renamable $q0 1305 renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr 1306 t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr 1307 tB %bb.3, 14 /* CC::al */, $noreg 1308 1309 bb.3: 1310 frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc 1311 1312 bb.4 (align 8): 1313 CONSTPOOL_ENTRY 0, %const.0, 16 1314... 1315