1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE 3; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE 4 5define arm_aapcs_vfpcc <4 x i32> @bitcast_to_v4i1(i4 %b, <4 x i32> %a) { 6; CHECK-LE-LABEL: bitcast_to_v4i1: 7; CHECK-LE: @ %bb.0: @ %entry 8; CHECK-LE-NEXT: .pad #4 9; CHECK-LE-NEXT: sub sp, #4 10; CHECK-LE-NEXT: and r0, r0, #15 11; CHECK-LE-NEXT: vmov.i8 q1, #0x0 12; CHECK-LE-NEXT: vmov.i8 q2, #0xff 13; CHECK-LE-NEXT: vmsr p0, r0 14; CHECK-LE-NEXT: vpsel q1, q2, q1 15; CHECK-LE-NEXT: vmov.u8 r0, q1[2] 16; CHECK-LE-NEXT: vmov.u8 r1, q1[0] 17; CHECK-LE-NEXT: vmov q2[2], q2[0], r1, r0 18; CHECK-LE-NEXT: vmov.u8 r0, q1[3] 19; CHECK-LE-NEXT: vmov.u8 r1, q1[1] 20; CHECK-LE-NEXT: vmov.i32 q1, #0x0 21; CHECK-LE-NEXT: vmov q2[3], q2[1], r1, r0 22; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr 23; CHECK-LE-NEXT: vpsel q0, q0, q1 24; CHECK-LE-NEXT: add sp, #4 25; CHECK-LE-NEXT: bx lr 26; 27; CHECK-BE-LABEL: bitcast_to_v4i1: 28; CHECK-BE: @ %bb.0: @ %entry 29; CHECK-BE-NEXT: .pad #4 30; CHECK-BE-NEXT: sub sp, #4 31; CHECK-BE-NEXT: rbit r0, r0 32; CHECK-BE-NEXT: vmov.i8 q1, #0x0 33; CHECK-BE-NEXT: vmov.i8 q2, #0xff 34; CHECK-BE-NEXT: lsrs r0, r0, #28 35; CHECK-BE-NEXT: vmsr p0, r0 36; CHECK-BE-NEXT: vpsel q1, q2, q1 37; CHECK-BE-NEXT: vmov.u8 r0, q1[2] 38; CHECK-BE-NEXT: vmov.u8 r1, q1[0] 39; CHECK-BE-NEXT: vmov q2[2], q2[0], r1, r0 40; CHECK-BE-NEXT: vmov.u8 r0, q1[3] 41; CHECK-BE-NEXT: vmov.u8 r1, q1[1] 42; CHECK-BE-NEXT: vrev64.32 q1, q0 43; CHECK-BE-NEXT: vmov q2[3], q2[1], r1, r0 44; CHECK-BE-NEXT: vmov.i32 q0, #0x0 45; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr 46; CHECK-BE-NEXT: vpsel q1, q1, q0 47; CHECK-BE-NEXT: vrev64.32 q0, q1 48; CHECK-BE-NEXT: add sp, #4 49; CHECK-BE-NEXT: bx lr 50entry: 51 %c = bitcast i4 %b to <4 x i1> 52 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer 53 ret <4 x i32> %s 54} 55 56define arm_aapcs_vfpcc <8 x i16> @bitcast_to_v8i1(i8 %b, <8 x i16> %a) { 57; CHECK-LE-LABEL: bitcast_to_v8i1: 58; CHECK-LE: @ %bb.0: @ %entry 59; CHECK-LE-NEXT: .pad #8 60; CHECK-LE-NEXT: sub sp, #8 61; CHECK-LE-NEXT: uxtb r0, r0 62; CHECK-LE-NEXT: vmov.i8 q1, #0x0 63; CHECK-LE-NEXT: vmov.i8 q2, #0xff 64; CHECK-LE-NEXT: vmsr p0, r0 65; CHECK-LE-NEXT: vpsel q2, q2, q1 66; CHECK-LE-NEXT: vmov.u8 r0, q2[0] 67; CHECK-LE-NEXT: vmov.16 q1[0], r0 68; CHECK-LE-NEXT: vmov.u8 r0, q2[1] 69; CHECK-LE-NEXT: vmov.16 q1[1], r0 70; CHECK-LE-NEXT: vmov.u8 r0, q2[2] 71; CHECK-LE-NEXT: vmov.16 q1[2], r0 72; CHECK-LE-NEXT: vmov.u8 r0, q2[3] 73; CHECK-LE-NEXT: vmov.16 q1[3], r0 74; CHECK-LE-NEXT: vmov.u8 r0, q2[4] 75; CHECK-LE-NEXT: vmov.16 q1[4], r0 76; CHECK-LE-NEXT: vmov.u8 r0, q2[5] 77; CHECK-LE-NEXT: vmov.16 q1[5], r0 78; CHECK-LE-NEXT: vmov.u8 r0, q2[6] 79; CHECK-LE-NEXT: vmov.16 q1[6], r0 80; CHECK-LE-NEXT: vmov.u8 r0, q2[7] 81; CHECK-LE-NEXT: vmov.16 q1[7], r0 82; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr 83; CHECK-LE-NEXT: vmov.i32 q1, #0x0 84; CHECK-LE-NEXT: vpsel q0, q0, q1 85; CHECK-LE-NEXT: add sp, #8 86; CHECK-LE-NEXT: bx lr 87; 88; CHECK-BE-LABEL: bitcast_to_v8i1: 89; CHECK-BE: @ %bb.0: @ %entry 90; CHECK-BE-NEXT: .pad #8 91; CHECK-BE-NEXT: sub sp, #8 92; CHECK-BE-NEXT: uxtb r0, r0 93; CHECK-BE-NEXT: vmov.i8 q1, #0x0 94; CHECK-BE-NEXT: rbit r0, r0 95; CHECK-BE-NEXT: vmov.i8 q2, #0xff 96; CHECK-BE-NEXT: lsrs r0, r0, #24 97; CHECK-BE-NEXT: vmsr p0, r0 98; CHECK-BE-NEXT: vpsel q2, q2, q1 99; CHECK-BE-NEXT: vmov.u8 r0, q2[0] 100; CHECK-BE-NEXT: vmov.16 q1[0], r0 101; CHECK-BE-NEXT: vmov.u8 r0, q2[1] 102; CHECK-BE-NEXT: vmov.16 q1[1], r0 103; CHECK-BE-NEXT: vmov.u8 r0, q2[2] 104; CHECK-BE-NEXT: vmov.16 q1[2], r0 105; CHECK-BE-NEXT: vmov.u8 r0, q2[3] 106; CHECK-BE-NEXT: vmov.16 q1[3], r0 107; CHECK-BE-NEXT: vmov.u8 r0, q2[4] 108; CHECK-BE-NEXT: vmov.16 q1[4], r0 109; CHECK-BE-NEXT: vmov.u8 r0, q2[5] 110; CHECK-BE-NEXT: vmov.16 q1[5], r0 111; CHECK-BE-NEXT: vmov.u8 r0, q2[6] 112; CHECK-BE-NEXT: vmov.16 q1[6], r0 113; CHECK-BE-NEXT: vmov.u8 r0, q2[7] 114; CHECK-BE-NEXT: vmov.16 q1[7], r0 115; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr 116; CHECK-BE-NEXT: vrev64.16 q1, q0 117; CHECK-BE-NEXT: vmov.i32 q0, #0x0 118; CHECK-BE-NEXT: vrev32.16 q0, q0 119; CHECK-BE-NEXT: vpsel q1, q1, q0 120; CHECK-BE-NEXT: vrev64.16 q0, q1 121; CHECK-BE-NEXT: add sp, #8 122; CHECK-BE-NEXT: bx lr 123entry: 124 %c = bitcast i8 %b to <8 x i1> 125 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer 126 ret <8 x i16> %s 127} 128 129define arm_aapcs_vfpcc <16 x i8> @bitcast_to_v16i1(i16 %b, <16 x i8> %a) { 130; CHECK-LE-LABEL: bitcast_to_v16i1: 131; CHECK-LE: @ %bb.0: @ %entry 132; CHECK-LE-NEXT: .save {r4, r6, r7, lr} 133; CHECK-LE-NEXT: push {r4, r6, r7, lr} 134; CHECK-LE-NEXT: .setfp r7, sp, #8 135; CHECK-LE-NEXT: add r7, sp, #8 136; CHECK-LE-NEXT: .pad #16 137; CHECK-LE-NEXT: sub sp, #16 138; CHECK-LE-NEXT: mov r4, sp 139; CHECK-LE-NEXT: bfc r4, #0, #4 140; CHECK-LE-NEXT: mov sp, r4 141; CHECK-LE-NEXT: sub.w r4, r7, #8 142; CHECK-LE-NEXT: vmsr p0, r0 143; CHECK-LE-NEXT: vmov.i32 q1, #0x0 144; CHECK-LE-NEXT: vpsel q0, q0, q1 145; CHECK-LE-NEXT: mov sp, r4 146; CHECK-LE-NEXT: pop {r4, r6, r7, pc} 147; 148; CHECK-BE-LABEL: bitcast_to_v16i1: 149; CHECK-BE: @ %bb.0: @ %entry 150; CHECK-BE-NEXT: .save {r4, r6, r7, lr} 151; CHECK-BE-NEXT: push {r4, r6, r7, lr} 152; CHECK-BE-NEXT: .setfp r7, sp, #8 153; CHECK-BE-NEXT: add r7, sp, #8 154; CHECK-BE-NEXT: .pad #16 155; CHECK-BE-NEXT: sub sp, #16 156; CHECK-BE-NEXT: mov r4, sp 157; CHECK-BE-NEXT: bfc r4, #0, #4 158; CHECK-BE-NEXT: mov sp, r4 159; CHECK-BE-NEXT: uxth r0, r0 160; CHECK-BE-NEXT: vrev64.8 q1, q0 161; CHECK-BE-NEXT: rbit r0, r0 162; CHECK-BE-NEXT: vmov.i32 q0, #0x0 163; CHECK-BE-NEXT: sub.w r4, r7, #8 164; CHECK-BE-NEXT: vrev32.8 q0, q0 165; CHECK-BE-NEXT: lsrs r0, r0, #16 166; CHECK-BE-NEXT: vmsr p0, r0 167; CHECK-BE-NEXT: vpsel q1, q1, q0 168; CHECK-BE-NEXT: vrev64.8 q0, q1 169; CHECK-BE-NEXT: mov sp, r4 170; CHECK-BE-NEXT: pop {r4, r6, r7, pc} 171entry: 172 %c = bitcast i16 %b to <16 x i1> 173 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer 174 ret <16 x i8> %s 175} 176 177define arm_aapcs_vfpcc <2 x i64> @bitcast_to_v2i1(i2 %b, <2 x i64> %a) { 178; CHECK-LE-LABEL: bitcast_to_v2i1: 179; CHECK-LE: @ %bb.0: @ %entry 180; CHECK-LE-NEXT: .pad #4 181; CHECK-LE-NEXT: sub sp, #4 182; CHECK-LE-NEXT: and r1, r0, #2 183; CHECK-LE-NEXT: and r0, r0, #1 184; CHECK-LE-NEXT: movs r2, #0 185; CHECK-LE-NEXT: rsbs r0, r0, #0 186; CHECK-LE-NEXT: sub.w r1, r2, r1, lsr #1 187; CHECK-LE-NEXT: vmov q1[2], q1[0], r0, r1 188; CHECK-LE-NEXT: vmov q1[3], q1[1], r0, r1 189; CHECK-LE-NEXT: vand q0, q0, q1 190; CHECK-LE-NEXT: add sp, #4 191; CHECK-LE-NEXT: bx lr 192; 193; CHECK-BE-LABEL: bitcast_to_v2i1: 194; CHECK-BE: @ %bb.0: @ %entry 195; CHECK-BE-NEXT: .pad #4 196; CHECK-BE-NEXT: sub sp, #4 197; CHECK-BE-NEXT: and r1, r0, #2 198; CHECK-BE-NEXT: and r0, r0, #1 199; CHECK-BE-NEXT: movs r2, #0 200; CHECK-BE-NEXT: rsbs r0, r0, #0 201; CHECK-BE-NEXT: sub.w r1, r2, r1, lsr #1 202; CHECK-BE-NEXT: vmov q1[2], q1[0], r1, r0 203; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r0 204; CHECK-BE-NEXT: vrev64.32 q2, q1 205; CHECK-BE-NEXT: vand q0, q0, q2 206; CHECK-BE-NEXT: add sp, #4 207; CHECK-BE-NEXT: bx lr 208entry: 209 %c = bitcast i2 %b to <2 x i1> 210 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> zeroinitializer 211 ret <2 x i64> %s 212} 213 214 215define arm_aapcs_vfpcc i4 @bitcast_from_v4i1(<4 x i32> %a) { 216; CHECK-LE-LABEL: bitcast_from_v4i1: 217; CHECK-LE: @ %bb.0: @ %entry 218; CHECK-LE-NEXT: .pad #4 219; CHECK-LE-NEXT: sub sp, #4 220; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr 221; CHECK-LE-NEXT: vmrs r1, p0 222; CHECK-LE-NEXT: and r0, r1, #1 223; CHECK-LE-NEXT: rsbs r2, r0, #0 224; CHECK-LE-NEXT: movs r0, #0 225; CHECK-LE-NEXT: bfi r0, r2, #0, #1 226; CHECK-LE-NEXT: ubfx r2, r1, #4, #1 227; CHECK-LE-NEXT: rsbs r2, r2, #0 228; CHECK-LE-NEXT: bfi r0, r2, #1, #1 229; CHECK-LE-NEXT: ubfx r2, r1, #8, #1 230; CHECK-LE-NEXT: ubfx r1, r1, #12, #1 231; CHECK-LE-NEXT: rsbs r2, r2, #0 232; CHECK-LE-NEXT: bfi r0, r2, #2, #1 233; CHECK-LE-NEXT: rsbs r1, r1, #0 234; CHECK-LE-NEXT: bfi r0, r1, #3, #1 235; CHECK-LE-NEXT: add sp, #4 236; CHECK-LE-NEXT: bx lr 237; 238; CHECK-BE-LABEL: bitcast_from_v4i1: 239; CHECK-BE: @ %bb.0: @ %entry 240; CHECK-BE-NEXT: .pad #4 241; CHECK-BE-NEXT: sub sp, #4 242; CHECK-BE-NEXT: vrev64.32 q1, q0 243; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr 244; CHECK-BE-NEXT: vmrs r1, p0 245; CHECK-BE-NEXT: ubfx r0, r1, #12, #1 246; CHECK-BE-NEXT: rsbs r2, r0, #0 247; CHECK-BE-NEXT: movs r0, #0 248; CHECK-BE-NEXT: bfi r0, r2, #0, #1 249; CHECK-BE-NEXT: ubfx r2, r1, #8, #1 250; CHECK-BE-NEXT: rsbs r2, r2, #0 251; CHECK-BE-NEXT: bfi r0, r2, #1, #1 252; CHECK-BE-NEXT: ubfx r2, r1, #4, #1 253; CHECK-BE-NEXT: and r1, r1, #1 254; CHECK-BE-NEXT: rsbs r2, r2, #0 255; CHECK-BE-NEXT: bfi r0, r2, #2, #1 256; CHECK-BE-NEXT: rsbs r1, r1, #0 257; CHECK-BE-NEXT: bfi r0, r1, #3, #1 258; CHECK-BE-NEXT: add sp, #4 259; CHECK-BE-NEXT: bx lr 260entry: 261 %c = icmp eq <4 x i32> %a, zeroinitializer 262 %b = bitcast <4 x i1> %c to i4 263 ret i4 %b 264} 265 266define arm_aapcs_vfpcc i8 @bitcast_from_v8i1(<8 x i16> %a) { 267; CHECK-LE-LABEL: bitcast_from_v8i1: 268; CHECK-LE: @ %bb.0: @ %entry 269; CHECK-LE-NEXT: .pad #8 270; CHECK-LE-NEXT: sub sp, #8 271; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr 272; CHECK-LE-NEXT: vmrs r1, p0 273; CHECK-LE-NEXT: and r0, r1, #1 274; CHECK-LE-NEXT: rsbs r2, r0, #0 275; CHECK-LE-NEXT: movs r0, #0 276; CHECK-LE-NEXT: bfi r0, r2, #0, #1 277; CHECK-LE-NEXT: ubfx r2, r1, #2, #1 278; CHECK-LE-NEXT: rsbs r2, r2, #0 279; CHECK-LE-NEXT: bfi r0, r2, #1, #1 280; CHECK-LE-NEXT: ubfx r2, r1, #4, #1 281; CHECK-LE-NEXT: rsbs r2, r2, #0 282; CHECK-LE-NEXT: bfi r0, r2, #2, #1 283; CHECK-LE-NEXT: ubfx r2, r1, #6, #1 284; CHECK-LE-NEXT: rsbs r2, r2, #0 285; CHECK-LE-NEXT: bfi r0, r2, #3, #1 286; CHECK-LE-NEXT: ubfx r2, r1, #8, #1 287; CHECK-LE-NEXT: rsbs r2, r2, #0 288; CHECK-LE-NEXT: bfi r0, r2, #4, #1 289; CHECK-LE-NEXT: ubfx r2, r1, #10, #1 290; CHECK-LE-NEXT: rsbs r2, r2, #0 291; CHECK-LE-NEXT: bfi r0, r2, #5, #1 292; CHECK-LE-NEXT: ubfx r2, r1, #12, #1 293; CHECK-LE-NEXT: ubfx r1, r1, #14, #1 294; CHECK-LE-NEXT: rsbs r2, r2, #0 295; CHECK-LE-NEXT: bfi r0, r2, #6, #1 296; CHECK-LE-NEXT: rsbs r1, r1, #0 297; CHECK-LE-NEXT: bfi r0, r1, #7, #1 298; CHECK-LE-NEXT: uxtb r0, r0 299; CHECK-LE-NEXT: add sp, #8 300; CHECK-LE-NEXT: bx lr 301; 302; CHECK-BE-LABEL: bitcast_from_v8i1: 303; CHECK-BE: @ %bb.0: @ %entry 304; CHECK-BE-NEXT: .pad #8 305; CHECK-BE-NEXT: sub sp, #8 306; CHECK-BE-NEXT: vrev64.16 q1, q0 307; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr 308; CHECK-BE-NEXT: vmrs r1, p0 309; CHECK-BE-NEXT: ubfx r0, r1, #14, #1 310; CHECK-BE-NEXT: rsbs r2, r0, #0 311; CHECK-BE-NEXT: movs r0, #0 312; CHECK-BE-NEXT: bfi r0, r2, #0, #1 313; CHECK-BE-NEXT: ubfx r2, r1, #12, #1 314; CHECK-BE-NEXT: rsbs r2, r2, #0 315; CHECK-BE-NEXT: bfi r0, r2, #1, #1 316; CHECK-BE-NEXT: ubfx r2, r1, #10, #1 317; CHECK-BE-NEXT: rsbs r2, r2, #0 318; CHECK-BE-NEXT: bfi r0, r2, #2, #1 319; CHECK-BE-NEXT: ubfx r2, r1, #8, #1 320; CHECK-BE-NEXT: rsbs r2, r2, #0 321; CHECK-BE-NEXT: bfi r0, r2, #3, #1 322; CHECK-BE-NEXT: ubfx r2, r1, #6, #1 323; CHECK-BE-NEXT: rsbs r2, r2, #0 324; CHECK-BE-NEXT: bfi r0, r2, #4, #1 325; CHECK-BE-NEXT: ubfx r2, r1, #4, #1 326; CHECK-BE-NEXT: rsbs r2, r2, #0 327; CHECK-BE-NEXT: bfi r0, r2, #5, #1 328; CHECK-BE-NEXT: ubfx r2, r1, #2, #1 329; CHECK-BE-NEXT: and r1, r1, #1 330; CHECK-BE-NEXT: rsbs r2, r2, #0 331; CHECK-BE-NEXT: bfi r0, r2, #6, #1 332; CHECK-BE-NEXT: rsbs r1, r1, #0 333; CHECK-BE-NEXT: bfi r0, r1, #7, #1 334; CHECK-BE-NEXT: uxtb r0, r0 335; CHECK-BE-NEXT: add sp, #8 336; CHECK-BE-NEXT: bx lr 337entry: 338 %c = icmp eq <8 x i16> %a, zeroinitializer 339 %b = bitcast <8 x i1> %c to i8 340 ret i8 %b 341} 342 343define arm_aapcs_vfpcc i16 @bitcast_from_v16i1(<16 x i8> %a) { 344; CHECK-LE-LABEL: bitcast_from_v16i1: 345; CHECK-LE: @ %bb.0: @ %entry 346; CHECK-LE-NEXT: .save {r4, r6, r7, lr} 347; CHECK-LE-NEXT: push {r4, r6, r7, lr} 348; CHECK-LE-NEXT: .setfp r7, sp, #8 349; CHECK-LE-NEXT: add r7, sp, #8 350; CHECK-LE-NEXT: .pad #16 351; CHECK-LE-NEXT: sub sp, #16 352; CHECK-LE-NEXT: mov r4, sp 353; CHECK-LE-NEXT: bfc r4, #0, #4 354; CHECK-LE-NEXT: mov sp, r4 355; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr 356; CHECK-LE-NEXT: sub.w r4, r7, #8 357; CHECK-LE-NEXT: vmrs r0, p0 358; CHECK-LE-NEXT: uxth r0, r0 359; CHECK-LE-NEXT: mov sp, r4 360; CHECK-LE-NEXT: pop {r4, r6, r7, pc} 361; 362; CHECK-BE-LABEL: bitcast_from_v16i1: 363; CHECK-BE: @ %bb.0: @ %entry 364; CHECK-BE-NEXT: .save {r4, r6, r7, lr} 365; CHECK-BE-NEXT: push {r4, r6, r7, lr} 366; CHECK-BE-NEXT: .setfp r7, sp, #8 367; CHECK-BE-NEXT: add r7, sp, #8 368; CHECK-BE-NEXT: .pad #16 369; CHECK-BE-NEXT: sub sp, #16 370; CHECK-BE-NEXT: mov r4, sp 371; CHECK-BE-NEXT: bfc r4, #0, #4 372; CHECK-BE-NEXT: mov sp, r4 373; CHECK-BE-NEXT: vrev64.8 q1, q0 374; CHECK-BE-NEXT: sub.w r4, r7, #8 375; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr 376; CHECK-BE-NEXT: vmrs r0, p0 377; CHECK-BE-NEXT: rbit r0, r0 378; CHECK-BE-NEXT: lsrs r0, r0, #16 379; CHECK-BE-NEXT: mov sp, r4 380; CHECK-BE-NEXT: pop {r4, r6, r7, pc} 381entry: 382 %c = icmp eq <16 x i8> %a, zeroinitializer 383 %b = bitcast <16 x i1> %c to i16 384 ret i16 %b 385} 386 387define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) { 388; CHECK-LE-LABEL: bitcast_from_v2i1: 389; CHECK-LE: @ %bb.0: @ %entry 390; CHECK-LE-NEXT: .pad #4 391; CHECK-LE-NEXT: sub sp, #4 392; CHECK-LE-NEXT: vmov r0, r1, d0 393; CHECK-LE-NEXT: orrs r0, r1 394; CHECK-LE-NEXT: vmov r1, r2, d1 395; CHECK-LE-NEXT: cset r0, eq 396; CHECK-LE-NEXT: orrs r1, r2 397; CHECK-LE-NEXT: cset r1, eq 398; CHECK-LE-NEXT: cmp r1, #0 399; CHECK-LE-NEXT: it ne 400; CHECK-LE-NEXT: mvnne r1, #1 401; CHECK-LE-NEXT: bfi r1, r0, #0, #1 402; CHECK-LE-NEXT: and r0, r1, #3 403; CHECK-LE-NEXT: add sp, #4 404; CHECK-LE-NEXT: bx lr 405; 406; CHECK-BE-LABEL: bitcast_from_v2i1: 407; CHECK-BE: @ %bb.0: @ %entry 408; CHECK-BE-NEXT: .pad #4 409; CHECK-BE-NEXT: sub sp, #4 410; CHECK-BE-NEXT: vrev64.32 q1, q0 411; CHECK-BE-NEXT: vmov r0, r1, d3 412; CHECK-BE-NEXT: orrs r0, r1 413; CHECK-BE-NEXT: vmov r1, r2, d2 414; CHECK-BE-NEXT: cset r0, eq 415; CHECK-BE-NEXT: orrs r1, r2 416; CHECK-BE-NEXT: cset r1, eq 417; CHECK-BE-NEXT: cmp r1, #0 418; CHECK-BE-NEXT: it ne 419; CHECK-BE-NEXT: mvnne r1, #1 420; CHECK-BE-NEXT: bfi r1, r0, #0, #1 421; CHECK-BE-NEXT: and r0, r1, #3 422; CHECK-BE-NEXT: add sp, #4 423; CHECK-BE-NEXT: bx lr 424entry: 425 %c = icmp eq <2 x i64> %a, zeroinitializer 426 %b = bitcast <2 x i1> %c to i2 427 ret i2 %b 428} 429