1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4; The fundamental problem: an add separated from other arithmetic by a sign or
5; zero extension can't be combined with the later instructions. However, if the
6; first add is 'nsw' or 'nuw' respectively, then we can promote the extension
7; ahead of that add to allow optimizations.
8
9define i64 @add_nsw_consts(i32 %i) {
10; CHECK-LABEL: add_nsw_consts:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    movslq %edi, %rax
13; CHECK-NEXT:    addq $12, %rax
14; CHECK-NEXT:    retq
15
16  %add = add nsw i32 %i, 5
17  %ext = sext i32 %add to i64
18  %idx = add i64 %ext, 7
19  ret i64 %idx
20}
21
22; An x86 bonus: If we promote the sext ahead of the 'add nsw',
23; we allow LEA formation and eliminate an add instruction.
24
25define i64 @add_nsw_sext_add(i32 %i, i64 %x) {
26; CHECK-LABEL: add_nsw_sext_add:
27; CHECK:       # %bb.0:
28; CHECK-NEXT:    movslq %edi, %rax
29; CHECK-NEXT:    leaq 5(%rax,%rsi), %rax
30; CHECK-NEXT:    retq
31
32  %add = add nsw i32 %i, 5
33  %ext = sext i32 %add to i64
34  %idx = add i64 %x, %ext
35  ret i64 %idx
36}
37
38; Throw in a scale (left shift) because an LEA can do that too.
39; Use a negative constant (LEA displacement) to verify that's handled correctly.
40
41define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) {
42; CHECK-LABEL: add_nsw_sext_lsh_add:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    movslq %edi, %rax
45; CHECK-NEXT:    leaq -40(%rsi,%rax,8), %rax
46; CHECK-NEXT:    retq
47
48  %add = add nsw i32 %i, -5
49  %ext = sext i32 %add to i64
50  %shl = shl i64 %ext, 3
51  %idx = add i64 %x, %shl
52  ret i64 %idx
53}
54
55; Don't promote the sext if it has no users. The wider add instruction needs an
56; extra byte to encode.
57
58define i64 @add_nsw_sext(i32 %i, i64 %x) {
59; CHECK-LABEL: add_nsw_sext:
60; CHECK:       # %bb.0:
61; CHECK-NEXT:    addl $5, %edi
62; CHECK-NEXT:    movslq %edi, %rax
63; CHECK-NEXT:    retq
64
65  %add = add nsw i32 %i, 5
66  %ext = sext i32 %add to i64
67  ret i64 %ext
68}
69
70; The typical use case: a 64-bit system where an 'int' is used as an index into an array.
71
72define i8* @gep8(i32 %i, i8* %x) {
73; CHECK-LABEL: gep8:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    movslq %edi, %rax
76; CHECK-NEXT:    leaq 5(%rax,%rsi), %rax
77; CHECK-NEXT:    retq
78
79  %add = add nsw i32 %i, 5
80  %ext = sext i32 %add to i64
81  %idx = getelementptr i8, i8* %x, i64 %ext
82  ret i8* %idx
83}
84
85define i16* @gep16(i32 %i, i16* %x) {
86; CHECK-LABEL: gep16:
87; CHECK:       # %bb.0:
88; CHECK-NEXT:    movslq %edi, %rax
89; CHECK-NEXT:    leaq -10(%rsi,%rax,2), %rax
90; CHECK-NEXT:    retq
91
92  %add = add nsw i32 %i, -5
93  %ext = sext i32 %add to i64
94  %idx = getelementptr i16, i16* %x, i64 %ext
95  ret i16* %idx
96}
97
98define i32* @gep32(i32 %i, i32* %x) {
99; CHECK-LABEL: gep32:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    movslq %edi, %rax
102; CHECK-NEXT:    leaq 20(%rsi,%rax,4), %rax
103; CHECK-NEXT:    retq
104
105  %add = add nsw i32 %i, 5
106  %ext = sext i32 %add to i64
107  %idx = getelementptr i32, i32* %x, i64 %ext
108  ret i32* %idx
109}
110
111define i64* @gep64(i32 %i, i64* %x) {
112; CHECK-LABEL: gep64:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    movslq %edi, %rax
115; CHECK-NEXT:    leaq -40(%rsi,%rax,8), %rax
116; CHECK-NEXT:    retq
117
118  %add = add nsw i32 %i, -5
119  %ext = sext i32 %add to i64
120  %idx = getelementptr i64, i64* %x, i64 %ext
121  ret i64* %idx
122}
123
124; LEA can't scale by 16, but the adds can still be combined into an LEA.
125
126define i128* @gep128(i32 %i, i128* %x) {
127; CHECK-LABEL: gep128:
128; CHECK:       # %bb.0:
129; CHECK-NEXT:    movslq %edi, %rax
130; CHECK-NEXT:    shlq $4, %rax
131; CHECK-NEXT:    leaq 80(%rax,%rsi), %rax
132; CHECK-NEXT:    retq
133
134  %add = add nsw i32 %i, 5
135  %ext = sext i32 %add to i64
136  %idx = getelementptr i128, i128* %x, i64 %ext
137  ret i128* %idx
138}
139
140; A bigger win can be achieved when there is more than one use of the
141; sign extended value. In this case, we can eliminate sign extension
142; instructions plus use more efficient addressing modes for memory ops.
143
144define void @PR20134(i32* %a, i32 %i) {
145; CHECK-LABEL: PR20134:
146; CHECK:       # %bb.0:
147; CHECK-NEXT:    movslq %esi, %rax
148; CHECK-NEXT:    movl 4(%rdi,%rax,4), %ecx
149; CHECK-NEXT:    addl 8(%rdi,%rax,4), %ecx
150; CHECK-NEXT:    movl %ecx, (%rdi,%rax,4)
151; CHECK-NEXT:    retq
152
153  %add1 = add nsw i32 %i, 1
154  %idx1 = sext i32 %add1 to i64
155  %gep1 = getelementptr i32, i32* %a, i64 %idx1
156  %load1 = load i32, i32* %gep1, align 4
157
158  %add2 = add nsw i32 %i, 2
159  %idx2 = sext i32 %add2 to i64
160  %gep2 = getelementptr i32, i32* %a, i64 %idx2
161  %load2 = load i32, i32* %gep2, align 4
162
163  %add3 = add i32 %load1, %load2
164  %idx3 = sext i32 %i to i64
165  %gep3 = getelementptr i32, i32* %a, i64 %idx3
166  store i32 %add3, i32* %gep3, align 4
167  ret void
168}
169
170; The same as @PR20134 but sign extension is replaced with zero extension
171define void @PR20134_zext(i32* %a, i32 %i) {
172; CHECK-LABEL: PR20134_zext:
173; CHECK:       # %bb.0:
174; CHECK-NEXT:    movl %esi, %eax
175; CHECK-NEXT:    movl 4(%rdi,%rax,4), %ecx
176; CHECK-NEXT:    addl 8(%rdi,%rax,4), %ecx
177; CHECK-NEXT:    movl %ecx, (%rdi,%rax,4)
178; CHECK-NEXT:    retq
179
180  %add1 = add nuw i32 %i, 1
181  %idx1 = zext i32 %add1 to i64
182  %gep1 = getelementptr i32, i32* %a, i64 %idx1
183  %load1 = load i32, i32* %gep1, align 4
184
185  %add2 = add nuw i32 %i, 2
186  %idx2 = zext i32 %add2 to i64
187  %gep2 = getelementptr i32, i32* %a, i64 %idx2
188  %load2 = load i32, i32* %gep2, align 4
189
190  %add3 = add i32 %load1, %load2
191  %idx3 = zext i32 %i to i64
192  %gep3 = getelementptr i32, i32* %a, i64 %idx3
193  store i32 %add3, i32* %gep3, align 4
194  ret void
195}
196