1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown -disable-cgp-select2branch -x86-cmov-converter=false | FileCheck %s
3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
4
5define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
6; CHECK-LABEL: test1:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    btl %esi, %edi
9; CHECK-NEXT:    movl $12, %eax
10; CHECK-NEXT:    cmovael (%rcx), %eax
11; CHECK-NEXT:    retq
12entry:
13	%0 = lshr i32 %x, %n
14	%1 = and i32 %0, 1
15	%toBool = icmp eq i32 %1, 0
16        %v = load i32, i32* %vp
17	%.0 = select i1 %toBool, i32 %v, i32 12
18	ret i32 %.0
19}
20
21define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
22; CHECK-LABEL: test2:
23; CHECK:       # %bb.0: # %entry
24; CHECK-NEXT:    btl %esi, %edi
25; CHECK-NEXT:    movl $12, %eax
26; CHECK-NEXT:    cmovbl (%rcx), %eax
27; CHECK-NEXT:    retq
28entry:
29	%0 = lshr i32 %x, %n
30	%1 = and i32 %0, 1
31	%toBool = icmp eq i32 %1, 0
32        %v = load i32, i32* %vp
33	%.0 = select i1 %toBool, i32 12, i32 %v
34	ret i32 %.0
35}
36
37
38; x86's 32-bit cmov zeroes the high 32 bits of the destination. Make
39; sure CodeGen takes advantage of that to avoid an unnecessary
40; zero-extend (movl) after the cmov.
41
42declare void @bar(i64) nounwind
43
44define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
45; CHECK-LABEL: test3:
46; CHECK:       # %bb.0:
47; CHECK-NEXT:    pushq %rax
48; CHECK-NEXT:    testb $1, %dl
49; CHECK-NEXT:    cmovel %esi, %edi
50; CHECK-NEXT:    callq bar@PLT
51; CHECK-NEXT:    popq %rax
52; CHECK-NEXT:    retq
53  %c = trunc i64 %a to i32
54  %d = trunc i64 %b to i32
55  %e = select i1 %p, i32 %c, i32 %d
56  %f = zext i32 %e to i64
57  call void @bar(i64 %f)
58  ret void
59}
60
61
62
63; CodeGen shouldn't try to do a setne after an expanded 8-bit conditional
64; move without recomputing EFLAGS, because the expansion of the conditional
65; move with control flow may clobber EFLAGS (e.g., with xor, to set the
66; register to zero).
67
68; The test is a little awkward; the important part is that there's a test before the
69; setne.
70; PR4814
71
72
73@g_3 = external dso_local global i8
74@g_96 = external dso_local global i8
75@g_100 = external dso_local global i8
76@_2E_str = external dso_local constant [15 x i8], align 1
77
78define i1 @test4() nounwind {
79; CHECK-LABEL: test4:
80; CHECK:       # %bb.0: # %entry
81; CHECK-NEXT:    pushq %rbx
82; CHECK-NEXT:    movsbl g_3(%rip), %edx
83; CHECK-NEXT:    movzbl %dl, %ecx
84; CHECK-NEXT:    shrl $7, %ecx
85; CHECK-NEXT:    xorb $1, %cl
86; CHECK-NEXT:    # kill: def $cl killed $cl killed $ecx
87; CHECK-NEXT:    sarl %cl, %edx
88; CHECK-NEXT:    movb g_96(%rip), %al
89; CHECK-NEXT:    testb %al, %al
90; CHECK-NEXT:    je .LBB3_2
91; CHECK-NEXT:  # %bb.1: # %bb.i.i.i
92; CHECK-NEXT:    movb g_100(%rip), %cl
93; CHECK-NEXT:  .LBB3_2: # %func_4.exit.i
94; CHECK-NEXT:    xorl %esi, %esi
95; CHECK-NEXT:    testb %dl, %dl
96; CHECK-NEXT:    setne %bl
97; CHECK-NEXT:    movzbl %al, %ecx
98; CHECK-NEXT:    cmovnel %esi, %ecx
99; CHECK-NEXT:    testb %al, %al
100; CHECK-NEXT:    je .LBB3_5
101; CHECK-NEXT:  # %bb.3: # %func_4.exit.i
102; CHECK-NEXT:    testb %bl, %bl
103; CHECK-NEXT:    jne .LBB3_5
104; CHECK-NEXT:  # %bb.4: # %bb.i.i
105; CHECK-NEXT:    movb g_100(%rip), %cl
106; CHECK-NEXT:    xorl %ebx, %ebx
107; CHECK-NEXT:    movl %eax, %ecx
108; CHECK-NEXT:  .LBB3_5: # %func_1.exit
109; CHECK-NEXT:    movb %cl, g_96(%rip)
110; CHECK-NEXT:    movzbl %cl, %esi
111; CHECK-NEXT:    movl $_2E_str, %edi
112; CHECK-NEXT:    xorl %eax, %eax
113; CHECK-NEXT:    callq printf@PLT
114; CHECK-NEXT:    movl %ebx, %eax
115; CHECK-NEXT:    popq %rbx
116; CHECK-NEXT:    retq
117entry:
118  %0 = load i8, i8* @g_3, align 1
119  %1 = sext i8 %0 to i32
120  %.lobit.i = lshr i8 %0, 7
121  %tmp.i = zext i8 %.lobit.i to i32
122  %tmp.not.i = xor i32 %tmp.i, 1
123  %iftmp.17.0.i.i = ashr i32 %1, %tmp.not.i
124  %retval56.i.i = trunc i32 %iftmp.17.0.i.i to i8
125  %2 = icmp eq i8 %retval56.i.i, 0
126  %g_96.promoted.i = load i8, i8* @g_96
127  %3 = icmp eq i8 %g_96.promoted.i, 0
128  br i1 %3, label %func_4.exit.i, label %bb.i.i.i
129
130bb.i.i.i:
131  %4 = load volatile i8, i8* @g_100, align 1
132  br label %func_4.exit.i
133
134func_4.exit.i:
135  %.not.i = xor i1 %2, true
136  %brmerge.i = or i1 %3, %.not.i
137  %.mux.i = select i1 %2, i8 %g_96.promoted.i, i8 0
138  br i1 %brmerge.i, label %func_1.exit, label %bb.i.i
139
140bb.i.i:
141  %5 = load volatile i8, i8* @g_100, align 1
142  br label %func_1.exit
143
144func_1.exit:
145  %g_96.tmp.0.i = phi i8 [ %g_96.promoted.i, %bb.i.i ], [ %.mux.i, %func_4.exit.i ]
146  %ret = phi i1 [ 0, %bb.i.i ], [ %.not.i, %func_4.exit.i ]
147  store i8 %g_96.tmp.0.i, i8* @g_96
148  %6 = zext i8 %g_96.tmp.0.i to i32
149  %7 = tail call i32 (i8*, ...) @printf(i8* noalias getelementptr ([15 x i8], [15 x i8]* @_2E_str, i64 0, i64 0), i32 %6) nounwind
150  ret i1 %ret
151}
152
153declare i32 @printf(i8* nocapture, ...) nounwind
154
155
156; Should compile to setcc | -2.
157; rdar://6668608
158define i32 @test5(i32* nocapture %P) nounwind readonly {
159; CHECK-LABEL: test5:
160; CHECK:       # %bb.0: # %entry
161; CHECK-NEXT:    xorl %eax, %eax
162; CHECK-NEXT:    cmpl $42, (%rdi)
163; CHECK-NEXT:    setge %al
164; CHECK-NEXT:    orl $-2, %eax
165; CHECK-NEXT:    retq
166entry:
167	%0 = load i32, i32* %P, align 4
168	%1 = icmp sgt i32 %0, 41
169	%iftmp.0.0 = select i1 %1, i32 -1, i32 -2
170	ret i32 %iftmp.0.0
171}
172
173define i32 @test6(i32* nocapture %P) nounwind readonly {
174; CHECK-LABEL: test6:
175; CHECK:       # %bb.0: # %entry
176; CHECK-NEXT:    xorl %eax, %eax
177; CHECK-NEXT:    cmpl $42, (%rdi)
178; CHECK-NEXT:    setl %al
179; CHECK-NEXT:    leal 4(%rax,%rax,8), %eax
180; CHECK-NEXT:    retq
181entry:
182	%0 = load i32, i32* %P, align 4
183	%1 = icmp sgt i32 %0, 41
184	%iftmp.0.0 = select i1 %1, i32 4, i32 13
185	ret i32 %iftmp.0.0
186}
187
188
189define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
190; CHECK-LABEL: test7:
191; CHECK:       # %bb.0:
192; CHECK-NEXT:    movl %esi, %eax
193; CHECK-NEXT:    testb $1, %dil
194; CHECK-NEXT:    cmovel %edx, %eax
195; CHECK-NEXT:    # kill: def $al killed $al killed $eax
196; CHECK-NEXT:    retq
197  %d = select i1 %c, i8 %a, i8 %b
198  ret i8 %d
199}
200
201define i64 @test8(i64 %0, i64 %1, i64 %2) {
202; CHECK-LABEL: test8:
203; CHECK:       # %bb.0:
204; CHECK-NEXT:    movq %rsi, %rax
205; CHECK-NEXT:    cmpq $-2147483648, %rdi # imm = 0x80000000
206; CHECK-NEXT:    cmovlq %rdx, %rax
207; CHECK-NEXT:    retq
208  %4 = icmp sgt i64 %0, -2147483649
209  %5 = select i1 %4, i64 %1, i64 %2
210  ret i64 %5
211}
212
213define i32 @smin(i32 %x) {
214; CHECK-LABEL: smin:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    notl %edi
217; CHECK-NEXT:    testl %edi, %edi
218; CHECK-NEXT:    movl $-1, %eax
219; CHECK-NEXT:    cmovsl %edi, %eax
220; CHECK-NEXT:    retq
221  %not_x = xor i32 %x, -1
222  %1 = icmp slt i32 %not_x, -1
223  %sel = select i1 %1, i32 %not_x, i32 -1
224  ret i32 %sel
225}
226
227define i32 @pr47049_1(i32 %0) {
228; CHECK-LABEL: pr47049_1:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    testl %edi, %edi
231; CHECK-NEXT:    movl $1, %eax
232; CHECK-NEXT:    cmovlel %edi, %eax
233; CHECK-NEXT:    retq
234  %2 = icmp slt i32 %0, 1
235  %3 = select i1 %2, i32 %0, i32 1
236  ret i32 %3
237}
238
239define i32 @pr47049_2(i32 %0) {
240; CHECK-LABEL: pr47049_2:
241; CHECK:       # %bb.0:
242; CHECK-NEXT:    testl %edi, %edi
243; CHECK-NEXT:    movl $-1, %eax
244; CHECK-NEXT:    cmovnsl %edi, %eax
245; CHECK-NEXT:    retq
246  %2 = icmp sgt i32 %0, -1
247  %3 = select i1 %2, i32 %0, i32 -1
248  ret i32 %3
249}
250
251define i32 @pr47049_3(i32 %0) {
252; CHECK-LABEL: pr47049_3:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    testl %edi, %edi
255; CHECK-NEXT:    movl $1, %eax
256; CHECK-NEXT:    cmovgl %edi, %eax
257; CHECK-NEXT:    retq
258  %2 = icmp sgt i32 %0, 1
259  %3 = select i1 %2, i32 %0, i32 1
260  ret i32 %3
261}
262
263define i32 @pr47049_4(i32 %0) {
264; CHECK-LABEL: pr47049_4:
265; CHECK:       # %bb.0:
266; CHECK-NEXT:    testl %edi, %edi
267; CHECK-NEXT:    movl $1, %eax
268; CHECK-NEXT:    cmovnel %edi, %eax
269; CHECK-NEXT:    retq
270  %2 = icmp ugt i32 %0, 1
271  %3 = select i1 %2, i32 %0, i32 1
272  ret i32 %3
273}
274