1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -verify-machineinstrs -no-integrated-as | FileCheck %s 3 4; There should be no stack manipulations between the inline asm and ret. 5define x86_fp80 @test1() { 6; CHECK-LABEL: test1: 7; CHECK: ## %bb.0: 8; CHECK-NEXT: ## InlineAsm Start 9; CHECK-NEXT: fld0 10; CHECK-NEXT: ## InlineAsm End 11; CHECK-NEXT: retl 12 %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"() 13 ret x86_fp80 %tmp85 14} 15 16define double @test2() { 17; CHECK-LABEL: test2: 18; CHECK: ## %bb.0: 19; CHECK-NEXT: ## InlineAsm Start 20; CHECK-NEXT: fld0 21; CHECK-NEXT: ## InlineAsm End 22; CHECK-NEXT: retl 23 %tmp85 = call double asm sideeffect "fld0", "={st(0)}"() 24 ret double %tmp85 25} 26 27; Setting up argument in st(0) should be a single fld. 28; Asm consumes stack, nothing should be popped. 29define void @test3(x86_fp80 %X) { 30; CHECK-LABEL: test3: 31; CHECK: ## %bb.0: 32; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 33; CHECK-NEXT: ## InlineAsm Start 34; CHECK-NEXT: frob 35; CHECK-NEXT: ## InlineAsm End 36; CHECK-NEXT: retl 37 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X) 38 ret void 39} 40 41define void @test4(double %X) { 42; CHECK-LABEL: test4: 43; CHECK: ## %bb.0: 44; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 45; CHECK-NEXT: ## InlineAsm Start 46; CHECK-NEXT: frob 47; CHECK-NEXT: ## InlineAsm End 48; CHECK-NEXT: retl 49 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %X) 50 ret void 51} 52 53; Same as test3/4, but using value from fadd. 54; The fadd can be done in xmm or x87 regs - we don't test that. 55define void @test5(double %X) { 56; CHECK-LABEL: test5: 57; CHECK: ## %bb.0: 58; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 59; CHECK-NEXT: fadds {{\.?LCPI[0-9]+_[0-9]+}} 60; CHECK-NEXT: ## InlineAsm Start 61; CHECK-NEXT: frob 62; CHECK-NEXT: ## InlineAsm End 63; CHECK-NEXT: retl 64 %Y = fadd double %X, 123.0 65 call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %Y) 66 ret void 67} 68 69define void @test6(double %A, double %B, double %C, double %D, double %E) nounwind { 70; CHECK-LABEL: test6: 71; CHECK: ## %bb.0: ## %entry 72; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 73; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 74; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 75; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 76; CHECK-NEXT: fldl {{[0-9]+}}(%esp) 77; CHECK-NEXT: ## InlineAsm Start 78; CHECK-NEXT: foo %st %st 79; CHECK-NEXT: ## InlineAsm End 80; CHECK-NEXT: fstp %st(0) 81; CHECK-NEXT: ## InlineAsm Start 82; CHECK-NEXT: bar %st(1) %st 83; CHECK-NEXT: ## InlineAsm End 84; CHECK-NEXT: fstp %st(1) 85; CHECK-NEXT: fstp %st(0) 86; CHECK-NEXT: ## InlineAsm Start 87; CHECK-NEXT: baz %st(1) %st 88; CHECK-NEXT: ## InlineAsm End 89; CHECK-NEXT: fstp %st(0) 90; CHECK-NEXT: ## InlineAsm Start 91; CHECK-NEXT: baz %st 92; CHECK-NEXT: ## InlineAsm End 93; CHECK-NEXT: fstp %st(0) 94; CHECK-NEXT: retl 95entry: 96; Uses the same value twice, should have one fstp after the asm. 97 tail call void asm sideeffect "foo $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %A, double %A ) nounwind 98; Uses two different values, should be in st(0)/st(1) and both be popped. 99 tail call void asm sideeffect "bar $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %B, double %C ) nounwind 100; Uses two different values, one of which isn't killed in this asm, it should not be popped after the asm. 101 tail call void asm sideeffect "baz $0 $1", "f,f,~{dirflag},~{fpsr},~{flags}"( double %D, double %E ) nounwind 102; This is the last use of %D, so it should be popped after. 103 tail call void asm sideeffect "baz $0", "f,~{dirflag},~{fpsr},~{flags}"( double %D ) nounwind 104 ret void 105} 106 107; PR4185 108; Passing a non-killed value to asm in {st}. 109; Make sure it is duped before. 110; asm kills st(0), so we shouldn't pop anything 111; A valid alternative would be to remat the constant pool load before each 112; inline asm. 113define void @testPR4185() { 114; CHECK-LABEL: testPR4185: 115; CHECK: ## %bb.0: ## %return 116; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 117; CHECK-NEXT: fld %st(0) 118; CHECK-NEXT: ## InlineAsm Start 119; CHECK-NEXT: fistpl %st 120; CHECK-NEXT: ## InlineAsm End 121; CHECK-NEXT: ## InlineAsm Start 122; CHECK-NEXT: fistpl %st 123; CHECK-NEXT: ## InlineAsm End 124; CHECK-NEXT: retl 125return: 126 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 127 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 128 ret void 129} 130 131; Passing a non-killed value through asm in {st}. 132; Make sure it is not duped before. 133; Second asm kills st(0), so we shouldn't pop anything 134; A valid alternative would be to remat the constant pool load before each inline asm. 135define void @testPR4185b() { 136; CHECK-LABEL: testPR4185b: 137; CHECK: ## %bb.0: ## %return 138; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 139; CHECK-NEXT: ## InlineAsm Start 140; CHECK-NEXT: fistl %st 141; CHECK-NEXT: ## InlineAsm End 142; CHECK-NEXT: ## InlineAsm Start 143; CHECK-NEXT: fistpl %st 144; CHECK-NEXT: ## InlineAsm End 145; CHECK-NEXT: retl 146return: 147 call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06) 148 call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) 149 ret void 150} 151 152; PR4459 153; The return value from ceil must be duped before being consumed by asm. 154define void @testPR4459(x86_fp80 %a) { 155; CHECK-LABEL: testPR4459: 156; CHECK: ## %bb.0: ## %entry 157; CHECK-NEXT: subl $28, %esp 158; CHECK-NEXT: .cfi_def_cfa_offset 32 159; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 160; CHECK-NEXT: fstpt (%esp) 161; CHECK-NEXT: calll _ceil 162; CHECK-NEXT: fld %st(0) 163; CHECK-NEXT: fxch %st(1) 164; CHECK-NEXT: ## InlineAsm Start 165; CHECK-NEXT: fistpl %st 166; CHECK-NEXT: ## InlineAsm End 167; CHECK-NEXT: fstpt (%esp) 168; CHECK-NEXT: calll _test3 169; CHECK-NEXT: addl $28, %esp 170; CHECK-NEXT: retl 171entry: 172 %0 = call x86_fp80 @ceil(x86_fp80 %a) 173 call void asm sideeffect "fistpl $0", "{st},~{st}"( x86_fp80 %0) 174 call void @test3(x86_fp80 %0 ) 175 ret void 176} 177declare x86_fp80 @ceil(x86_fp80) 178 179; PR4484 180; test1 leaves a value on the stack that is needed after the asm. 181; Load %a from stack after ceil 182; Set up call to test. 183define void @testPR4484(x86_fp80 %a) { 184; CHECK-LABEL: testPR4484: 185; CHECK: ## %bb.0: ## %entry 186; CHECK-NEXT: subl $28, %esp 187; CHECK-NEXT: .cfi_def_cfa_offset 32 188; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 189; CHECK-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill 190; CHECK-NEXT: calll _test1 191; CHECK-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload 192; CHECK-NEXT: ## InlineAsm Start 193; CHECK-NEXT: fistpl %st 194; CHECK-NEXT: ## InlineAsm End 195; CHECK-NEXT: fstpt (%esp) 196; CHECK-NEXT: calll _test3 197; CHECK-NEXT: addl $28, %esp 198; CHECK-NEXT: retl 199entry: 200 %0 = call x86_fp80 @test1() 201 call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a) 202 call void @test3(x86_fp80 %0) 203 ret void 204} 205 206; PR4485 207define void @testPR4485(x86_fp80* %a) { 208; CHECK-LABEL: testPR4485: 209; CHECK: ## %bb.0: ## %entry 210; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 211; CHECK-NEXT: fldt (%eax) 212; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 213; CHECK-NEXT: fmul %st, %st(1) 214; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 215; CHECK-NEXT: fmul %st, %st(2) 216; CHECK-NEXT: fxch %st(2) 217; CHECK-NEXT: ## InlineAsm Start 218; CHECK-NEXT: fistpl %st 219; CHECK-NEXT: ## InlineAsm End 220; CHECK-NEXT: fldt (%eax) 221; CHECK-NEXT: fmulp %st, %st(1) 222; CHECK-NEXT: fmulp %st, %st(1) 223; CHECK-NEXT: ## InlineAsm Start 224; CHECK-NEXT: fistpl %st 225; CHECK-NEXT: ## InlineAsm End 226; CHECK-NEXT: retl 227entry: 228 %0 = load x86_fp80, x86_fp80* %a, align 16 229 %1 = fmul x86_fp80 %0, 0xK4006B400000000000000 230 %2 = fmul x86_fp80 %1, 0xK4012F424000000000000 231 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2) 232 %3 = load x86_fp80, x86_fp80* %a, align 16 233 %4 = fmul x86_fp80 %3, 0xK4006B400000000000000 234 %5 = fmul x86_fp80 %4, 0xK4012F424000000000000 235 tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) 236 ret void 237} 238 239; An input argument in a fixed position is implicitly popped by the asm only if 240; the input argument is tied to an output register, or it is in the clobber list. 241; The clobber list case is tested above. 242; 243; This doesn't implicitly pop the stack: 244; 245; void fist1(long double x, int *p) { 246; asm volatile ("fistl %1" : : "t"(x), "m"(*p)); 247; } 248define void @fist1(x86_fp80 %x, i32* %p) nounwind ssp { 249; CHECK-LABEL: fist1: 250; CHECK: ## %bb.0: ## %entry 251; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 252; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 253; CHECK-NEXT: ## InlineAsm Start 254; CHECK-NEXT: fistl (%eax) 255; CHECK-NEXT: ## InlineAsm End 256; CHECK-NEXT: fstp %st(0) 257; CHECK-NEXT: retl 258entry: 259 tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind 260 ret void 261} 262 263; Here, the input operand is tied to an output which means that is is 264; implicitly popped (and then the output is implicitly pushed). 265; 266; long double fist2(long double x, int *p) { 267; long double y; 268; asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory"); 269; return y; 270; } 271define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp { 272; CHECK-LABEL: fist2: 273; CHECK: ## %bb.0: ## %entry 274; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 275; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 276; CHECK-NEXT: ## InlineAsm Start 277; CHECK-NEXT: fistl (%eax) 278; CHECK-NEXT: ## InlineAsm End 279; CHECK-NEXT: retl 280entry: 281 %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind 282 ret x86_fp80 %0 283} 284 285; An 'f' constraint is never implicitly popped: 286; 287; void fucomp1(long double x, long double y) { 288; asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st"); 289; } 290define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 291; CHECK-LABEL: fucomp1: 292; CHECK: ## %bb.0: ## %entry 293; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 294; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 295; CHECK-NEXT: fxch %st(1) 296; CHECK-NEXT: ## InlineAsm Start 297; CHECK-NEXT: fucomp %st(1) 298; CHECK-NEXT: ## InlineAsm End 299; CHECK-NEXT: fstp %st(0) 300; CHECK-NEXT: retl 301entry: 302 tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 303 ret void 304} 305 306; The 'u' constraint is only popped implicitly when clobbered: 307; 308; void fucomp2(long double x, long double y) { 309; asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st"); 310; } 311; 312; void fucomp3(long double x, long double y) { 313; asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)"); 314; } 315; 316define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 317; CHECK-LABEL: fucomp2: 318; CHECK: ## %bb.0: ## %entry 319; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 320; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 321; CHECK-NEXT: fxch %st(1) 322; CHECK-NEXT: ## InlineAsm Start 323; CHECK-NEXT: fucomp %st(1) 324; CHECK-NEXT: ## InlineAsm End 325; CHECK-NEXT: fstp %st(0) 326; CHECK-NEXT: retl 327entry: 328 tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 329 ret void 330} 331 332define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp { 333; CHECK-LABEL: fucomp3: 334; CHECK: ## %bb.0: ## %entry 335; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 336; CHECK-NEXT: fldt {{[0-9]+}}(%esp) 337; CHECK-NEXT: fxch %st(1) 338; CHECK-NEXT: ## InlineAsm Start 339; CHECK-NEXT: fucompp %st(1) 340; CHECK-NEXT: ## InlineAsm End 341; CHECK-NEXT: retl 342entry: 343 tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind 344 ret void 345} 346 347; One input, two outputs, one dead output. 348%complex = type { float, float } 349define float @sincos1(float %x) nounwind ssp { 350; CHECK-LABEL: sincos1: 351; CHECK: ## %bb.0: ## %entry 352; CHECK-NEXT: flds {{[0-9]+}}(%esp) 353; CHECK-NEXT: ## InlineAsm Start 354; CHECK-NEXT: sincos 355; CHECK-NEXT: ## InlineAsm End 356; CHECK-NEXT: fstp %st(1) 357; CHECK-NEXT: retl 358entry: 359 %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 360 %asmresult = extractvalue %complex %0, 0 361 ret float %asmresult 362} 363 364; Same thing, swapped output operands. 365define float @sincos2(float %x) nounwind ssp { 366; CHECK-LABEL: sincos2: 367; CHECK: ## %bb.0: ## %entry 368; CHECK-NEXT: flds {{[0-9]+}}(%esp) 369; CHECK-NEXT: ## InlineAsm Start 370; CHECK-NEXT: sincos 371; CHECK-NEXT: ## InlineAsm End 372; CHECK-NEXT: fstp %st(1) 373; CHECK-NEXT: retl 374entry: 375 %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 376 %asmresult = extractvalue %complex %0, 1 377 ret float %asmresult 378} 379 380; Clobber st(0) after it was live-out/dead from the previous asm. 381; Load x, make a copy for the second asm. 382; Discard dead result in st(0), bring x to the top. 383; x is now in st(0) for the second asm 384; Discard both results. 385define float @sincos3(float %x) nounwind ssp { 386; CHECK-LABEL: sincos3: 387; CHECK: ## %bb.0: ## %entry 388; CHECK-NEXT: flds {{[0-9]+}}(%esp) 389; CHECK-NEXT: fld %st(0) 390; CHECK-NEXT: ## InlineAsm Start 391; CHECK-NEXT: sincos 392; CHECK-NEXT: ## InlineAsm End 393; CHECK-NEXT: fstp %st(0) 394; CHECK-NEXT: fxch %st(1) 395; CHECK-NEXT: ## InlineAsm Start 396; CHECK-NEXT: sincos 397; CHECK-NEXT: ## InlineAsm End 398; CHECK-NEXT: fstp %st(1) 399; CHECK-NEXT: fstp %st(0) 400; CHECK-NEXT: retl 401entry: 402 %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 403 %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind 404 %asmresult = extractvalue %complex %0, 0 405 ret float %asmresult 406} 407 408; Pass the same value in two fixed stack slots. 409define i32 @PR10602() nounwind ssp { 410; CHECK-LABEL: PR10602: 411; CHECK: ## %bb.0: ## %entry 412; CHECK-NEXT: flds {{\.?LCPI[0-9]+_[0-9]+}} 413; CHECK-NEXT: fld %st(0) 414; CHECK-NEXT: fxch %st(1) 415; CHECK-NEXT: ## InlineAsm Start 416; CHECK-NEXT: fcomi %st(1), %st; pushf; pop %eax 417; CHECK-NEXT: ## InlineAsm End 418; CHECK-NEXT: fstp %st(0) 419; CHECK-NEXT: fstp %st(0) 420; CHECK-NEXT: retl 421entry: 422 %0 = tail call i32 asm "fcomi $2, $1; pushf; pop $0", "=r,{st},{st(1)},~{dirflag},~{fpsr},~{flags}"(double 2.000000e+00, double 2.000000e+00) nounwind 423 ret i32 %0 424} 425 426; <rdar://problem/16952634> 427; X87 stackifier asserted when there was an ST register defined by an 428; inline-asm instruction and the ST register was live across another 429; inline-asm instruction. 430; 431; INLINEASM $frndint [sideeffect] [attdialect], $0:[regdef], %st0<imp-def,tied5>, $1:[reguse tiedto:$0], %st0<tied3>, $2:[clobber], early-clobber implicit dead %eflags 432; INLINEASM $fldcw $0 [sideeffect] [mayload] [attdialect], $0:[mem], undef %eax, 1, %noreg, 0, %noreg, $1:[clobber], early-clobber implicit dead %eflags 433; %fp0 = COPY %st0 434 435%struct.fpu_t = type { [8 x x86_fp80], x86_fp80, %struct.anon1, %struct.anon2, i32, i8, [15 x i8] } 436%struct.anon1 = type { i32, i32, i32 } 437%struct.anon2 = type { i32, i32, i32, i32 } 438 439@fpu = external global %struct.fpu_t, align 16 440 441; Function Attrs: ssp 442define void @test_live_st(i32 %a1) { 443; CHECK-LABEL: test_live_st: 444; CHECK: ## %bb.0: ## %entry 445; CHECK-NEXT: subl $12, %esp 446; CHECK-NEXT: .cfi_def_cfa_offset 16 447; CHECK-NEXT: fldt (%eax) 448; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp) 449; CHECK-NEXT: jne LBB20_2 450; CHECK-NEXT: ## %bb.1: ## %sw.bb4.i 451; CHECK-NEXT: ## InlineAsm Start 452; CHECK-NEXT: frndint 453; CHECK-NEXT: ## InlineAsm End 454; CHECK-NEXT: ## InlineAsm Start 455; CHECK-NEXT: fldcw (%eax) 456; CHECK-NEXT: ## InlineAsm End 457; CHECK-NEXT: LBB20_2: ## %_Z5tointRKe.exit 458; CHECK-NEXT: fnstcw (%esp) 459; CHECK-NEXT: movzwl (%esp), %eax 460; CHECK-NEXT: orl $3072, %eax ## imm = 0xC00 461; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp) 462; CHECK-NEXT: fldcw {{[0-9]+}}(%esp) 463; CHECK-NEXT: fistpl {{[0-9]+}}(%esp) 464; CHECK-NEXT: fldcw (%esp) 465; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax 466; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) 467; CHECK-NEXT: fildl {{[0-9]+}}(%esp) 468; CHECK-NEXT: movl L_fpu$non_lazy_ptr, %eax 469; CHECK-NEXT: fstpt 128(%eax) 470; CHECK-NEXT: addl $12, %esp 471; CHECK-NEXT: retl 472entry: 473 %0 = load x86_fp80, x86_fp80* undef, align 16 474 %cond = icmp eq i32 %a1, 1 475 br i1 %cond, label %sw.bb4.i, label %_Z5tointRKe.exit 476 477sw.bb4.i: 478 %1 = call x86_fp80 asm sideeffect "frndint", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %0) 479 call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"(i32* undef) 480 br label %_Z5tointRKe.exit 481 482_Z5tointRKe.exit: 483 %result.0.i = phi x86_fp80 [ %1, %sw.bb4.i ], [ %0, %entry ] 484 %conv.i1814 = fptosi x86_fp80 %result.0.i to i32 485 %conv626 = sitofp i32 %conv.i1814 to x86_fp80 486 store x86_fp80 %conv626, x86_fp80* getelementptr inbounds (%struct.fpu_t, %struct.fpu_t* @fpu, i32 0, i32 1) 487 br label %return 488 489return: 490 ret void 491} 492 493; Check that x87 stackifier is correctly rewriting FP registers to ST registers. 494define double @test_operand_rewrite() { 495; CHECK-LABEL: test_operand_rewrite: 496; CHECK: ## %bb.0: ## %entry 497; CHECK-NEXT: ## InlineAsm Start 498; CHECK-NEXT: foo %st, %st(1) 499; CHECK-NEXT: ## InlineAsm End 500; CHECK-NEXT: fsubp %st, %st(1) 501; CHECK-NEXT: retl 502entry: 503 %0 = tail call { double, double } asm sideeffect "foo $0, $1", "={st},={st(1)},~{dirflag},~{fpsr},~{flags}"() 504 %asmresult = extractvalue { double, double } %0, 0 505 %asmresult1 = extractvalue { double, double } %0, 1 506 %sub = fsub double %asmresult, %asmresult1 507 ret double %sub 508} 509