1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=haswell | FileCheck %s 3 4define void @WhileWithLoopInvariantOperation.21() { 5; CHECK-LABEL: WhileWithLoopInvariantOperation.21: 6; CHECK: # %bb.0: # %while.1.body.preheader 7; CHECK-NEXT: movq (%rax), %rax 8; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 9; CHECK-NEXT: vmovaps %xmm0, 32(%rax) 10; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,4294967295,0,0] 11; CHECK-NEXT: vmaskmovps %ymm0, %ymm0, (%rax) 12while.1.body.preheader: 13 %0 = load i8*, i8** undef, align 8, !invariant.load !0, !dereferenceable !1, !align !2 14 %1 = getelementptr inbounds i8, i8* %0, i64 32 15 tail call void @llvm.memset.p0i8.i64(i8* nonnull align 16 dereferenceable(16) %1, i8 0, i64 16, i1 false) 16 %2 = tail call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 4, <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x float> <float undef, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>) 17 %3 = tail call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 4, <16 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x float> <float undef, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>) 18 tail call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* nonnull undef, i32 4, <16 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>) 19 unreachable 20} 21 22declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg) 23 24declare <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>*, i32 immarg, <8 x i1>, <8 x float>) 25 26declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32 immarg, <16 x i1>, <16 x float>) 27 28declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32 immarg, <16 x i1>) 29 30!0 = !{} 31!1 = !{i64 65} 32!2 = !{i64 16} 33 34