1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null 3 4; Verify that DAGCombiner doesn't crash with an assertion failure in the 5; attempt to cast a ISD::UNDEF node to a ConstantSDNode. 6 7; During type legalization, the vector shift operation in function @test1 is 8; split into two legal shifts that work on <2 x i64> elements. 9; The first shift of the legalized sequence would be a shift by all undefs. 10; DAGCombiner will then try to simplify the vector shift and check if the 11; vector of shift counts is a splat. Make sure that llc doesn't crash 12; at that stage. 13 14 15define <4 x i64> @test1(<4 x i64> %A) { 16 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2> 17 ret <4 x i64> %shl 18} 19 20; Also, verify that DAGCombiner doesn't crash when trying to combine shifts 21; with different combinations of undef elements in the vector shift count. 22 23define <4 x i64> @test2(<4 x i64> %A) { 24 %shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef> 25 ret <4 x i64> %shl 26} 27 28define <4 x i64> @test3(<4 x i64> %A) { 29 %shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef> 30 ret <4 x i64> %shl 31} 32 33define <4 x i64> @test4(<4 x i64> %A) { 34 %shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3> 35 ret <4 x i64> %shl 36} 37 38define <4 x i64> @test5(<4 x i64> %A) { 39 %shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef> 40 ret <4 x i64> %shl 41} 42 43define <4 x i64> @test6(<4 x i64> %A) { 44 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef> 45 ret <4 x i64> %shl 46} 47 48define <4 x i64> @test7(<4 x i64> %A) { 49 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3> 50 ret <4 x i64> %shl 51} 52 53define <4 x i64> @test8(<4 x i64> %A) { 54 %shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef> 55 ret <4 x i64> %shl 56} 57 58 59