1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s 3; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s 4 5define <4 x i64> @autogen_SD88863() { 6; CHECK-LABEL: autogen_SD88863: 7; CHECK: # %bb.0: # %BB 8; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,2,3] 9; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 10; CHECK-NEXT: vxorps %xmm1, %xmm1, %xmm1 11; CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5],ymm1[6,7] 12; CHECK-NEXT: movb $1, %al 13; CHECK-NEXT: .p2align 4, 0x90 14; CHECK-NEXT: .LBB0_1: # %CF 15; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 16; CHECK-NEXT: testb %al, %al 17; CHECK-NEXT: jne .LBB0_1 18; CHECK-NEXT: # %bb.2: # %CF240 19; CHECK-NEXT: ret{{[l|q]}} 20BB: 21 %I26 = insertelement <4 x i64> undef, i64 undef, i32 2 22 br label %CF 23 24CF: 25 %E66 = extractelement <4 x i64> %I26, i32 1 26 %I68 = insertelement <4 x i64> zeroinitializer, i64 %E66, i32 2 27 %Cmp72 = icmp eq i32 0, 0 28 br i1 %Cmp72, label %CF, label %CF240 29 30CF240: 31 ret <4 x i64> %I68 32} 33