1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=i386-apple-darwin10 -mattr=+avx | FileCheck %s
3
4define <8 x float> @cvt_v8i8_v8f32(<8 x i8> %src) {
5; CHECK-LABEL: cvt_v8i8_v8f32:
6; CHECK:       ## %bb.0:
7; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm1
8; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
9; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm0
10; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
11; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
12; CHECK-NEXT:    retl
13  %res = sitofp <8 x i8> %src to <8 x float>
14  ret <8 x float> %res
15}
16
17define <8 x float> @cvt_v8i16_v8f32(<8 x i16> %src) {
18; CHECK-LABEL: cvt_v8i16_v8f32:
19; CHECK:       ## %bb.0:
20; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm1
21; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
22; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
23; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
24; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
25; CHECK-NEXT:    retl
26  %res = sitofp <8 x i16> %src to <8 x float>
27  ret <8 x float> %res
28}
29
30define <4 x float> @cvt_v4i8_v4f32(<4 x i8> %src) {
31; CHECK-LABEL: cvt_v4i8_v4f32:
32; CHECK:       ## %bb.0:
33; CHECK-NEXT:    vpmovsxbd %xmm0, %xmm0
34; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
35; CHECK-NEXT:    retl
36  %res = sitofp <4 x i8> %src to <4 x float>
37  ret <4 x float> %res
38}
39
40define <4 x float> @cvt_v4i16_v4f32(<4 x i16> %src) {
41; CHECK-LABEL: cvt_v4i16_v4f32:
42; CHECK:       ## %bb.0:
43; CHECK-NEXT:    vpmovsxwd %xmm0, %xmm0
44; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
45; CHECK-NEXT:    retl
46  %res = sitofp <4 x i16> %src to <4 x float>
47  ret <4 x float> %res
48}
49
50define <8 x float> @cvt_v8u8_v8f32(<8 x i8> %src) {
51; CHECK-LABEL: cvt_v8u8_v8f32:
52; CHECK:       ## %bb.0:
53; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
54; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
55; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
56; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
57; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
58; CHECK-NEXT:    retl
59  %res = uitofp <8 x i8> %src to <8 x float>
60  ret <8 x float> %res
61}
62
63define <8 x float> @cvt_v8u16_v8f32(<8 x i16> %src) {
64; CHECK-LABEL: cvt_v8u16_v8f32:
65; CHECK:       ## %bb.0:
66; CHECK-NEXT:    vpxor %xmm1, %xmm1, %xmm1
67; CHECK-NEXT:    vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
68; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
69; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
70; CHECK-NEXT:    vcvtdq2ps %ymm0, %ymm0
71; CHECK-NEXT:    retl
72  %res = uitofp <8 x i16> %src to <8 x float>
73  ret <8 x float> %res
74}
75
76define <4 x float> @cvt_v4u8_v4f32(<4 x i8> %src) {
77; CHECK-LABEL: cvt_v4u8_v4f32:
78; CHECK:       ## %bb.0:
79; CHECK-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
80; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
81; CHECK-NEXT:    retl
82  %res = uitofp <4 x i8> %src to <4 x float>
83  ret <4 x float> %res
84}
85
86define <4 x float> @cvt_v4u16_v4f32(<4 x i16> %src) {
87; CHECK-LABEL: cvt_v4u16_v4f32:
88; CHECK:       ## %bb.0:
89; CHECK-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
90; CHECK-NEXT:    vcvtdq2ps %xmm0, %xmm0
91; CHECK-NEXT:    retl
92  %res = uitofp <4 x i16> %src to <4 x float>
93  ret <4 x float> %res
94}
95
96define <8 x i8> @cvt_v8f32_v8i8(<8 x float> %src) {
97; CHECK-LABEL: cvt_v8f32_v8i8:
98; CHECK:       ## %bb.0:
99; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
100; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
101; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
102; CHECK-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
103; CHECK-NEXT:    vzeroupper
104; CHECK-NEXT:    retl
105  %res = fptosi <8 x float> %src to <8 x i8>
106  ret <8 x i8> %res
107}
108
109define <8 x i16> @cvt_v8f32_v8i16(<8 x float> %src) {
110; CHECK-LABEL: cvt_v8f32_v8i16:
111; CHECK:       ## %bb.0:
112; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
113; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
114; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
115; CHECK-NEXT:    vzeroupper
116; CHECK-NEXT:    retl
117  %res = fptosi <8 x float> %src to <8 x i16>
118  ret <8 x i16> %res
119}
120
121define <4 x i8> @cvt_v4f32_v4i8(<4 x float> %src) {
122; CHECK-LABEL: cvt_v4f32_v4i8:
123; CHECK:       ## %bb.0:
124; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
125; CHECK-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
126; CHECK-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
127; CHECK-NEXT:    retl
128  %res = fptosi <4 x float> %src to <4 x i8>
129  ret <4 x i8> %res
130}
131
132define <4 x i16> @cvt_v4f32_v4i16(<4 x float> %src) {
133; CHECK-LABEL: cvt_v4f32_v4i16:
134; CHECK:       ## %bb.0:
135; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
136; CHECK-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
137; CHECK-NEXT:    retl
138  %res = fptosi <4 x float> %src to <4 x i16>
139  ret <4 x i16> %res
140}
141
142define <8 x i8> @cvt_v8f32_v8u8(<8 x float> %src) {
143; CHECK-LABEL: cvt_v8f32_v8u8:
144; CHECK:       ## %bb.0:
145; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
146; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
147; CHECK-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
148; CHECK-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
149; CHECK-NEXT:    vzeroupper
150; CHECK-NEXT:    retl
151  %res = fptoui <8 x float> %src to <8 x i8>
152  ret <8 x i8> %res
153}
154
155define <8 x i16> @cvt_v8f32_v8u16(<8 x float> %src) {
156; CHECK-LABEL: cvt_v8f32_v8u16:
157; CHECK:       ## %bb.0:
158; CHECK-NEXT:    vcvttps2dq %ymm0, %ymm0
159; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
160; CHECK-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
161; CHECK-NEXT:    vzeroupper
162; CHECK-NEXT:    retl
163  %res = fptoui <8 x float> %src to <8 x i16>
164  ret <8 x i16> %res
165}
166
167define <4 x i8> @cvt_v4f32_v4u8(<4 x float> %src) {
168; CHECK-LABEL: cvt_v4f32_v4u8:
169; CHECK:       ## %bb.0:
170; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
171; CHECK-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
172; CHECK-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
173; CHECK-NEXT:    retl
174  %res = fptoui <4 x float> %src to <4 x i8>
175  ret <4 x i8> %res
176}
177
178define <4 x i16> @cvt_v4f32_v4u16(<4 x float> %src) {
179; CHECK-LABEL: cvt_v4f32_v4u16:
180; CHECK:       ## %bb.0:
181; CHECK-NEXT:    vcvttps2dq %xmm0, %xmm0
182; CHECK-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
183; CHECK-NEXT:    retl
184  %res = fptoui <4 x float> %src to <4 x i16>
185  ret <4 x i16> %res
186}
187
188