1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse4.2 < %s | FileCheck %s
3; RUN: llc -mtriple=i686-unknown-unknown -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
4
5; Scheduler causes produce a different instruction order
6
7; bitcast a v4i16 to v2i32
8
9define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
10; CHECK-LABEL: convert:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    pushl %eax
13; CHECK-NEXT:    movl $0, (%esp)
14; CHECK-NEXT:    pcmpeqd %xmm0, %xmm0
15; CHECK-NEXT:    cmpl $3, (%esp)
16; CHECK-NEXT:    jg .LBB0_3
17; CHECK-NEXT:    .p2align 4, 0x90
18; CHECK-NEXT:  .LBB0_2: # %forbody
19; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
20; CHECK-NEXT:    movl (%esp), %eax
21; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
22; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
23; CHECK-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
24; CHECK-NEXT:    psubw %xmm0, %xmm1
25; CHECK-NEXT:    movq %xmm1, (%ecx,%eax,8)
26; CHECK-NEXT:    incl (%esp)
27; CHECK-NEXT:    cmpl $3, (%esp)
28; CHECK-NEXT:    jle .LBB0_2
29; CHECK-NEXT:  .LBB0_3: # %afterfor
30; CHECK-NEXT:    popl %eax
31; CHECK-NEXT:    retl
32;
33; ATOM-LABEL: convert:
34; ATOM:       # %bb.0: # %entry
35; ATOM-NEXT:    pushl %eax
36; ATOM-NEXT:    pcmpeqd %xmm0, %xmm0
37; ATOM-NEXT:    movl $0, (%esp)
38; ATOM-NEXT:    cmpl $3, (%esp)
39; ATOM-NEXT:    jg .LBB0_3
40; ATOM-NEXT:    .p2align 4, 0x90
41; ATOM-NEXT:  .LBB0_2: # %forbody
42; ATOM-NEXT:    # =>This Inner Loop Header: Depth=1
43; ATOM-NEXT:    movl (%esp), %eax
44; ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
45; ATOM-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
46; ATOM-NEXT:    movl {{[0-9]+}}(%esp), %ecx
47; ATOM-NEXT:    psubw %xmm0, %xmm1
48; ATOM-NEXT:    movq %xmm1, (%ecx,%eax,8)
49; ATOM-NEXT:    incl (%esp)
50; ATOM-NEXT:    cmpl $3, (%esp)
51; ATOM-NEXT:    jle .LBB0_2
52; ATOM-NEXT:  .LBB0_3: # %afterfor
53; ATOM-NEXT:    popl %eax
54; ATOM-NEXT:    retl
55entry:
56	%dst.addr = alloca <2 x i32>*
57	%src.addr = alloca <4 x i16>*
58	%i = alloca i32, align 4
59	store <2 x i32>* %dst, <2 x i32>** %dst.addr
60	store <4 x i16>* %src, <4 x i16>** %src.addr
61	store i32 0, i32* %i
62	br label %forcond
63
64forcond:
65	%tmp = load i32, i32* %i
66	%cmp = icmp slt i32 %tmp, 4
67	br i1 %cmp, label %forbody, label %afterfor
68
69forbody:
70	%tmp1 = load i32, i32* %i
71	%tmp2 = load <2 x i32>*, <2 x i32>** %dst.addr
72	%arrayidx = getelementptr <2 x i32>, <2 x i32>* %tmp2, i32 %tmp1
73	%tmp3 = load i32, i32* %i
74	%tmp4 = load <4 x i16>*, <4 x i16>** %src.addr
75	%arrayidx5 = getelementptr <4 x i16>, <4 x i16>* %tmp4, i32 %tmp3
76	%tmp6 = load <4 x i16>, <4 x i16>* %arrayidx5
77	%add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 >
78	%conv = bitcast <4 x i16> %add to <2 x i32>
79	store <2 x i32> %conv, <2 x i32>* %arrayidx
80	br label %forinc
81
82forinc:
83	%tmp7 = load i32, i32* %i
84	%inc = add i32 %tmp7, 1
85	store i32 %inc, i32* %i
86	br label %forcond
87
88afterfor:
89	ret void
90}
91