1@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
2@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
3
4         vadd.f16  s0, s1, s0
5@ CHECK: instruction requires: full half-float
6
7         vsub.f16  s0, s1, s0
8@ CHECK: instruction requires: full half-float
9
10         vdiv.f16  s0, s1, s0
11@ CHECK: instruction requires: full half-float
12
13         vmul.f16  s0, s1, s0
14@ CHECK: instruction requires: full half-float
15
16         vnmul.f16       s0, s1, s0
17@ CHECK: instruction requires: full half-float
18
19         vmla.f16        s1, s2, s0
20@ CHECK: instruction requires: full half-float
21
22         vmls.f16        s1, s2, s0
23@ CHECK: instruction requires: full half-float
24
25         vnmla.f16       s1, s2, s0
26@ CHECK: instruction requires: full half-float
27
28         vnmls.f16       s1, s2, s0
29@ CHECK: instruction requires: full half-float
30
31         vcmp.f16 s0, s1
32@ CHECK: instruction requires: full half-float
33
34         vcmp.f16 s2, #0
35@ CHECK: instruction requires: full half-float
36
37         vcmpe.f16       s1, s0
38@ CHECK: instruction requires: full half-float
39
40         vcmpe.f16       s0, #0
41@ CHECK: instruction requires: full half-float
42
43         vabs.f16        s0, s0
44@ CHECK: instruction requires: full half-float
45
46         vneg.f16        s0, s0
47@ CHECK: instruction requires: full half-float
48
49         vsqrt.f16       s0, s0
50@ CHECK: instruction requires: full half-float
51
52         vcvt.f16.s32    s0, s0
53         vcvt.f16.u32    s0, s0
54         vcvt.s32.f16    s0, s0
55         vcvt.u32.f16    s0, s0
56@ CHECK: instruction requires: full half-float
57@ CHECK: instruction requires: full half-float
58@ CHECK: instruction requires: full half-float
59@ CHECK: instruction requires: full half-float
60
61         vcvtr.s32.f16  s0, s1
62         vcvtr.u32.f16  s0, s1
63@ CHECK: instruction requires: full half-float
64@ CHECK: instruction requires: full half-float
65
66         vcvt.f16.u32 s0, s0, #20
67         vcvt.f16.u16 s0, s0, #1
68         vcvt.f16.s32 s1, s1, #20
69         vcvt.f16.s16 s17, s17, #1
70         vcvt.u32.f16 s12, s12, #20
71         vcvt.u16.f16 s28, s28, #1
72         vcvt.s32.f16 s1, s1, #20
73         vcvt.s16.f16 s17, s17, #1
74@ CHECK: instruction requires: full half-float
75@ CHECK: instruction requires: full half-float
76@ CHECK: instruction requires: full half-float
77@ CHECK: instruction requires: full half-float
78@ CHECK: instruction requires: full half-float
79@ CHECK: instruction requires: full half-float
80@ CHECK: instruction requires: full half-float
81@ CHECK: instruction requires: full half-float
82
83  vcvta.s32.f16 s2, s3
84@ CHECK: instruction requires: full half-float
85
86  vcvtn.s32.f16 s6, s23
87@ CHECK: instruction requires: full half-float
88
89  vcvtp.s32.f16 s0, s4
90@ CHECK: instruction requires: full half-float
91
92  vcvtm.s32.f16 s17, s8
93@ CHECK: instruction requires: full half-float
94
95  vcvta.u32.f16 s2, s3
96@ CHECK: instruction requires: full half-float
97
98  vcvtn.u32.f16 s6, s23
99@ CHECK: instruction requires: full half-float
100
101  vcvtp.u32.f16 s0, s4
102@ CHECK: instruction requires: full half-float
103
104  vcvtm.u32.f16 s17, s8
105@ CHECK: instruction requires: full half-float
106
107  vselge.f16 s4, s1, s23
108@ CHECK: instruction requires: full half-float
109
110  vselgt.f16 s0, s1, s0
111@ CHECK: instruction requires: full half-float
112
113  vseleq.f16 s30, s28, s23
114@ CHECK: instruction requires: full half-float
115
116  vselvs.f16 s21, s16, s14
117@ CHECK: instruction requires: full half-float
118
119  vmaxnm.f16 s5, s12, s0
120@ CHECK: instruction requires: full half-float
121
122  vminnm.f16 s0, s0, s12
123@ CHECK: instruction requires: full half-float
124
125  vrintz.f16 s3, s24
126@ CHECK: instruction requires: full half-float
127
128  vrintr.f16 s0, s9
129@ CHECK: instruction requires: full half-float
130
131  vrintx.f16 s10, s14
132@ CHECK: instruction requires: full half-float
133
134  vrinta.f16 s12, s1
135@ CHECK: instruction requires: full half-float
136
137  vrintn.f16 s12, s1
138@ CHECK: instruction requires: full half-float
139
140  vrintp.f16 s12, s1
141@ CHECK: instruction requires: full half-float
142
143  vrintm.f16 s12, s1
144@ CHECK: instruction requires: full half-float
145
146  vfma.f16 s2, s7, s4
147@ CHECK: instruction requires: full half-float
148
149  vfms.f16 s2, s7, s4
150@ CHECK: instruction requires: full half-float
151
152  vfnma.f16 s2, s7, s4
153@ CHECK: instruction requires: full half-float
154
155  vfnms.f16 s2, s7, s4
156@ CHECK: instruction requires: full half-float
157
158  vmovx.f16 s2, s5
159  vins.f16 s2, s5
160@ CHECK: instruction requires: full half-float
161@ CHECK: instruction requires: full half-float
162
163
164  vldr.16 s1, [pc, #6]
165  vldr.16 s2, [pc, #510]
166  vldr.16 s3, [pc, #-510]
167  vldr.16 s4, [r4, #-18]
168@ CHECK: instruction requires: 16-bit fp registers
169@ CHECK: instruction requires: 16-bit fp registers
170@ CHECK: instruction requires: 16-bit fp registers
171@ CHECK: instruction requires: 16-bit fp registers
172
173
174  vstr.16 s1, [pc, #6]
175  vstr.16 s2, [pc, #510]
176  vstr.16 s3, [pc, #-510]
177  vstr.16 s4, [r4, #-18]
178@ CHECK: instruction requires: 16-bit fp registers
179@ CHECK: instruction requires: 16-bit fp registers
180@ CHECK: instruction requires: 16-bit fp registers
181@ CHECK: instruction requires: 16-bit fp registers
182
183  vmov.f16 s0, #1.0
184@ CHECK: instruction requires: full half-float
185
186  vmov.f16 s1, r2
187  vmov.f16 r3, s4
188@ CHECK: instruction requires: 16-bit fp registers
189@ CHECK: instruction requires: 16-bit fp registers
190