1// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s 2 3include "llvm/Target/Target.td" 4include "GlobalISelEmitterCommon.td" 5 6let Namespace = "MyTarget" in { 7 8def lo8 : SubRegIndex<8>; 9def hi8 : SubRegIndex<8, 8>; 10def lo16 : SubRegIndex<16>; 11def hi16 : SubRegIndex<16, 16>; 12 13def a0bl : Register<"a0bl">; 14def a0bh : Register<"a0bh">; 15def a0wh : Register<"a0wh">; 16 17} // Namespace = "MyTarget" 18 19def a0wl: RegisterWithSubRegs<"a0", [a0bh, a0bl]> { 20 let SubRegIndices = [hi8, lo8]; 21 let CoveredBySubRegs = 1; 22} 23 24def a0: RegisterWithSubRegs<"a0", [a0wh, a0wl]> { 25 let SubRegIndices = [hi16, lo16]; 26 let CoveredBySubRegs = 1; 27} 28 29def A0b : RegisterClass<"MyTarget", [i8], 8, (add a0bl)>; 30def A0w : RegisterClass<"MyTarget", [i16], 16, (add a0wl)>; 31def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; 32 33// CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 34// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT, 35// CHECK-NEXT: // MIs[0] dst 36// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, 37// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::A0RegClassID, 38// CHECK-NEXT: // MIs[0] src 39// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 40// CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] }) 41// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 42// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 43// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 44// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 45// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 46// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 47// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 48// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 49// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 50// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/3, 51// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, MyTarget::A0RegClassID, 52// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, MyTarget::A0RegClassID, 53// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, MyTarget::A0bRegClassID, 54// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 55// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 56// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo16, 57// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, 58// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::A0wRegClassID, 59// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, MyTarget::A0RegClassID, 60def : Pat<(i16 (anyext i8:$src)), 61 (i16 (EXTRACT_SUBREG 62 (i32 (INSERT_SUBREG 63 (i32 (IMPLICIT_DEF)), 64 A0b:$src, 65 lo8)), 66 lo16))>; 67