1 //===- MachineInstrTest.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/CodeGen/MachineInstr.h"
10 #include "llvm/ADT/Triple.h"
11 #include "llvm/CodeGen/MachineBasicBlock.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/CodeGen/MachineMemOperand.h"
14 #include "llvm/CodeGen/MachineModuleInfo.h"
15 #include "llvm/CodeGen/TargetFrameLowering.h"
16 #include "llvm/CodeGen/TargetInstrInfo.h"
17 #include "llvm/CodeGen/TargetLowering.h"
18 #include "llvm/CodeGen/TargetSubtargetInfo.h"
19 #include "llvm/IR/DebugInfoMetadata.h"
20 #include "llvm/IR/IRBuilder.h"
21 #include "llvm/IR/ModuleSlotTracker.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/TargetSelect.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "gtest/gtest.h"
29
30 using namespace llvm;
31
32 namespace {
33 // Include helper functions to ease the manipulation of MachineFunctions.
34 #include "MFCommon.inc"
35
createMCContext(MCAsmInfo * AsmInfo)36 std::unique_ptr<MCContext> createMCContext(MCAsmInfo *AsmInfo) {
37 Triple TheTriple(/*ArchStr=*/"", /*VendorStr=*/"", /*OSStr=*/"",
38 /*EnvironmentStr=*/"elf");
39 return std::make_unique<MCContext>(TheTriple, AsmInfo, nullptr, nullptr,
40 nullptr, nullptr, false);
41 }
42
43 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
44 // for various combinations of IgnoreDefs, and also that it is symmetrical.
TEST(IsIdenticalToTest,DifferentDefs)45 TEST(IsIdenticalToTest, DifferentDefs) {
46 LLVMContext Ctx;
47 Module Mod("Module", Ctx);
48 auto MF = createMachineFunction(Ctx, Mod);
49
50 unsigned short NumOps = 2;
51 unsigned char NumDefs = 1;
52 MCOperandInfo OpInfo[] = {
53 {0, 0, MCOI::OPERAND_REGISTER, 0},
54 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
55 MCInstrDesc MCID = {
56 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
57 0, nullptr, nullptr, OpInfo};
58
59 // Create two MIs with different virtual reg defs and the same uses.
60 unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
61 unsigned VirtualDef2 = -43;
62 unsigned VirtualUse = -44;
63
64 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
65 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
66 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
67
68 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
69 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
70 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
71
72 // Check that they are identical when we ignore virtual register defs, but not
73 // when we check defs.
74 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
75 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
76
77 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
78 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
79
80 // Create two MIs with different virtual reg defs, and a def or use of a
81 // sentinel register.
82 unsigned SentinelReg = 0;
83
84 auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
85 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
86 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
87
88 auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
89 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
90 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
91
92 // Check that they are never identical.
93 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
94 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
95
96 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
97 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
98 }
99
100 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
101 // MachineInstrExpressionTrait::getHashValue
checkHashAndIsEqualMatch(MachineInstr * MI1,MachineInstr * MI2)102 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
103 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
104 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
105
106 ASSERT_EQ(IsEqual1, IsEqual2);
107
108 auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
109 auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
110
111 ASSERT_EQ(IsEqual1, Hash1 == Hash2);
112 }
113
114 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
115 // with MachineInstrExpressionTraits::getHashValue.
TEST(MachineInstrExpressionTraitTest,IsEqualAgreesWithGetHashValue)116 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
117 LLVMContext Ctx;
118 Module Mod("Module", Ctx);
119 auto MF = createMachineFunction(Ctx, Mod);
120
121 unsigned short NumOps = 2;
122 unsigned char NumDefs = 1;
123 MCOperandInfo OpInfo[] = {
124 {0, 0, MCOI::OPERAND_REGISTER, 0},
125 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
126 MCInstrDesc MCID = {
127 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
128 0, nullptr, nullptr, OpInfo};
129
130 // Define a series of instructions with different kinds of operands and make
131 // sure that the hash function is consistent with isEqual for various
132 // combinations of them.
133 unsigned VirtualDef1 = -42;
134 unsigned VirtualDef2 = -43;
135 unsigned VirtualReg = -44;
136 unsigned SentinelReg = 0;
137 unsigned PhysicalReg = 45;
138
139 auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
140 VD1VU->addOperand(*MF,
141 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
142 VD1VU->addOperand(*MF,
143 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
144
145 auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
146 VD2VU->addOperand(*MF,
147 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
148 VD2VU->addOperand(*MF,
149 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
150
151 auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
152 VD1SU->addOperand(*MF,
153 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
154 VD1SU->addOperand(*MF,
155 MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
156
157 auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
158 VD1SD->addOperand(*MF,
159 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
160 VD1SD->addOperand(*MF,
161 MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
162
163 auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
164 VD2PU->addOperand(*MF,
165 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
166 VD2PU->addOperand(*MF,
167 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
168
169 auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
170 VD2PD->addOperand(*MF,
171 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
172 VD2PD->addOperand(*MF,
173 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
174
175 checkHashAndIsEqualMatch(VD1VU, VD2VU);
176 checkHashAndIsEqualMatch(VD1VU, VD1SU);
177 checkHashAndIsEqualMatch(VD1VU, VD1SD);
178 checkHashAndIsEqualMatch(VD1VU, VD2PU);
179 checkHashAndIsEqualMatch(VD1VU, VD2PD);
180
181 checkHashAndIsEqualMatch(VD2VU, VD1SU);
182 checkHashAndIsEqualMatch(VD2VU, VD1SD);
183 checkHashAndIsEqualMatch(VD2VU, VD2PU);
184 checkHashAndIsEqualMatch(VD2VU, VD2PD);
185
186 checkHashAndIsEqualMatch(VD1SU, VD1SD);
187 checkHashAndIsEqualMatch(VD1SU, VD2PU);
188 checkHashAndIsEqualMatch(VD1SU, VD2PD);
189
190 checkHashAndIsEqualMatch(VD1SD, VD2PU);
191 checkHashAndIsEqualMatch(VD1SD, VD2PD);
192
193 checkHashAndIsEqualMatch(VD2PU, VD2PD);
194 }
195
TEST(MachineInstrPrintingTest,DebugLocPrinting)196 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
197 LLVMContext Ctx;
198 Module Mod("Module", Ctx);
199 auto MF = createMachineFunction(Ctx, Mod);
200
201 MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
202 MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo};
203
204 DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
205 DISubprogram *DIS = DISubprogram::getDistinct(
206 Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
207 DISubprogram::SPFlagZero, nullptr);
208 DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
209 DebugLoc DL(DIL);
210 MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
211 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
212
213 std::string str;
214 raw_string_ostream OS(str);
215 MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
216 /*AddNewLine*/false);
217 ASSERT_TRUE(
218 StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
219 ASSERT_TRUE(
220 StringRef(OS.str()).endswith("filename:1:5"));
221 }
222
TEST(MachineInstrSpan,DistanceBegin)223 TEST(MachineInstrSpan, DistanceBegin) {
224 LLVMContext Ctx;
225 Module Mod("Module", Ctx);
226 auto MF = createMachineFunction(Ctx, Mod);
227 auto MBB = MF->CreateMachineBasicBlock();
228
229 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
230
231 auto MII = MBB->begin();
232 MachineInstrSpan MIS(MII, MBB);
233 ASSERT_TRUE(MIS.empty());
234
235 auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
236 MBB->insert(MII, MI);
237 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
238 }
239
TEST(MachineInstrSpan,DistanceEnd)240 TEST(MachineInstrSpan, DistanceEnd) {
241 LLVMContext Ctx;
242 Module Mod("Module", Ctx);
243 auto MF = createMachineFunction(Ctx, Mod);
244 auto MBB = MF->CreateMachineBasicBlock();
245
246 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
247
248 auto MII = MBB->end();
249 MachineInstrSpan MIS(MII, MBB);
250 ASSERT_TRUE(MIS.empty());
251
252 auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
253 MBB->insert(MII, MI);
254 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
255 }
256
TEST(MachineInstrExtraInfo,AddExtraInfo)257 TEST(MachineInstrExtraInfo, AddExtraInfo) {
258 LLVMContext Ctx;
259 Module Mod("Module", Ctx);
260 auto MF = createMachineFunction(Ctx, Mod);
261 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
262
263 auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
264 auto MAI = MCAsmInfo();
265 auto MC = createMCContext(&MAI);
266 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
267 MachineMemOperand::MOLoad, 8, Align(8));
268 SmallVector<MachineMemOperand *, 2> MMOs;
269 MMOs.push_back(MMO);
270 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
271 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
272 MDNode *MDN = MDNode::getDistinct(Ctx, None);
273
274 ASSERT_TRUE(MI->memoperands_empty());
275 ASSERT_FALSE(MI->getPreInstrSymbol());
276 ASSERT_FALSE(MI->getPostInstrSymbol());
277 ASSERT_FALSE(MI->getHeapAllocMarker());
278
279 MI->setMemRefs(*MF, MMOs);
280 ASSERT_TRUE(MI->memoperands().size() == 1);
281 ASSERT_FALSE(MI->getPreInstrSymbol());
282 ASSERT_FALSE(MI->getPostInstrSymbol());
283 ASSERT_FALSE(MI->getHeapAllocMarker());
284
285 MI->setPreInstrSymbol(*MF, Sym1);
286 ASSERT_TRUE(MI->memoperands().size() == 1);
287 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
288 ASSERT_FALSE(MI->getPostInstrSymbol());
289 ASSERT_FALSE(MI->getHeapAllocMarker());
290
291 MI->setPostInstrSymbol(*MF, Sym2);
292 ASSERT_TRUE(MI->memoperands().size() == 1);
293 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
294 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
295 ASSERT_FALSE(MI->getHeapAllocMarker());
296
297 MI->setHeapAllocMarker(*MF, MDN);
298 ASSERT_TRUE(MI->memoperands().size() == 1);
299 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
300 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
301 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
302 }
303
TEST(MachineInstrExtraInfo,ChangeExtraInfo)304 TEST(MachineInstrExtraInfo, ChangeExtraInfo) {
305 LLVMContext Ctx;
306 Module Mod("Module", Ctx);
307 auto MF = createMachineFunction(Ctx, Mod);
308 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
309
310 auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
311 auto MAI = MCAsmInfo();
312 auto MC = createMCContext(&MAI);
313 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
314 MachineMemOperand::MOLoad, 8, Align(8));
315 SmallVector<MachineMemOperand *, 2> MMOs;
316 MMOs.push_back(MMO);
317 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
318 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
319 MDNode *MDN = MDNode::getDistinct(Ctx, None);
320
321 MI->setMemRefs(*MF, MMOs);
322 MI->setPreInstrSymbol(*MF, Sym1);
323 MI->setPostInstrSymbol(*MF, Sym2);
324 MI->setHeapAllocMarker(*MF, MDN);
325
326 MMOs.push_back(MMO);
327
328 MI->setMemRefs(*MF, MMOs);
329 ASSERT_TRUE(MI->memoperands().size() == 2);
330 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
331 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2);
332 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
333
334 MI->setPostInstrSymbol(*MF, Sym1);
335 ASSERT_TRUE(MI->memoperands().size() == 2);
336 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
337 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1);
338 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
339 }
340
TEST(MachineInstrExtraInfo,RemoveExtraInfo)341 TEST(MachineInstrExtraInfo, RemoveExtraInfo) {
342 LLVMContext Ctx;
343 Module Mod("Module", Ctx);
344 auto MF = createMachineFunction(Ctx, Mod);
345 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr};
346
347 auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
348 auto MAI = MCAsmInfo();
349 auto MC = createMCContext(&MAI);
350 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(),
351 MachineMemOperand::MOLoad, 8, Align(8));
352 SmallVector<MachineMemOperand *, 2> MMOs;
353 MMOs.push_back(MMO);
354 MMOs.push_back(MMO);
355 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false);
356 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false);
357 MDNode *MDN = MDNode::getDistinct(Ctx, None);
358
359 MI->setMemRefs(*MF, MMOs);
360 MI->setPreInstrSymbol(*MF, Sym1);
361 MI->setPostInstrSymbol(*MF, Sym2);
362 MI->setHeapAllocMarker(*MF, MDN);
363
364 MI->setPostInstrSymbol(*MF, nullptr);
365 ASSERT_TRUE(MI->memoperands().size() == 2);
366 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
367 ASSERT_FALSE(MI->getPostInstrSymbol());
368 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN);
369
370 MI->setHeapAllocMarker(*MF, nullptr);
371 ASSERT_TRUE(MI->memoperands().size() == 2);
372 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1);
373 ASSERT_FALSE(MI->getPostInstrSymbol());
374 ASSERT_FALSE(MI->getHeapAllocMarker());
375
376 MI->setPreInstrSymbol(*MF, nullptr);
377 ASSERT_TRUE(MI->memoperands().size() == 2);
378 ASSERT_FALSE(MI->getPreInstrSymbol());
379 ASSERT_FALSE(MI->getPostInstrSymbol());
380 ASSERT_FALSE(MI->getHeapAllocMarker());
381
382 MI->setMemRefs(*MF, {});
383 ASSERT_TRUE(MI->memoperands_empty());
384 ASSERT_FALSE(MI->getPreInstrSymbol());
385 ASSERT_FALSE(MI->getPostInstrSymbol());
386 ASSERT_FALSE(MI->getHeapAllocMarker());
387 }
388
389 static_assert(std::is_trivially_copyable<MCOperand>::value,
390 "trivially copyable");
391
392 } // end namespace
393