1//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Addressing modes for load/store instructions
11class AddrModeType<bits<3> value> {
12  bits<3> Value = value;
13}
14
15def NoAddrMode     : AddrModeType<0>;  // No addressing mode
16def Absolute       : AddrModeType<1>;  // Absolute addressing mode
17def AbsoluteSet    : AddrModeType<2>;  // Absolute set addressing mode
18def BaseImmOffset  : AddrModeType<3>;  // Indirect with offset
19def BaseLongOffset : AddrModeType<4>;  // Indirect with long offset
20def BaseRegOffset  : AddrModeType<5>;  // Indirect with register offset
21def PostInc        : AddrModeType<6>;  // Post increment addressing mode
22
23class MemAccessSize<bits<4> value> {
24  bits<4> Value = value;
25}
26
27// These numbers must match the MemAccessSize enumeration values in
28// HexagonBaseInfo.h.
29def NoMemAccess      : MemAccessSize<0>;
30def ByteAccess       : MemAccessSize<1>;
31def HalfWordAccess   : MemAccessSize<2>;
32def WordAccess       : MemAccessSize<3>;
33def DoubleWordAccess : MemAccessSize<4>;
34def HVXVectorAccess  : MemAccessSize<5>;
35
36
37//===----------------------------------------------------------------------===//
38//                         Instruction Class Declaration +
39//===----------------------------------------------------------------------===//
40
41class OpcodeHexagon {
42  field bits<32> Inst = ?; // Default to an invalid insn.
43  bits<4> IClass = 0; // ICLASS
44  bits<1> zero = 0;
45
46  let Inst{31-28} = IClass;
47}
48
49class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
50                  string cstr, InstrItinClass itin, IType type>
51  : Instruction {
52  let Namespace = "Hexagon";
53
54  dag OutOperandList = outs;
55  dag InOperandList = ins;
56  let AsmString = asmstr;
57  let Pattern = pattern;
58  let Constraints = cstr;
59  let Itinerary = itin;
60  let Size = 4;
61
62  // SoftFail is a field the disassembler can use to provide a way for
63  // instructions to not match without killing the whole decode process. It is
64  // mainly used for ARM, but Tablegen expects this field to exist or it fails
65  // to build the decode table.
66  field bits<32> SoftFail = 0;
67
68  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
69
70  // Instruction type according to the ISA.
71  IType Type = type;
72  let TSFlags{5-0} = Type.Value;
73
74  // Solo instructions, i.e., those that cannot be in a packet with others.
75  bits<1> isSolo = 0;
76  let TSFlags{6} = isSolo;
77  // Packed only with A or X-type instructions.
78  bits<1> isSoloAX = 0;
79  let TSFlags{7} = isSoloAX;
80  // Restricts slot 1 to ALU-only instructions.
81  bits<1> isRestrictSlot1AOK = 0;
82  let TSFlags{8} = isRestrictSlot1AOK;
83
84  // Predicated instructions.
85  bits<1> isPredicated = 0;
86  let TSFlags{9} = isPredicated;
87  bits<1> isPredicatedFalse = 0;
88  let TSFlags{10} = isPredicatedFalse;
89  bits<1> isPredicatedNew = 0;
90  let TSFlags{11} = isPredicatedNew;
91  bits<1> isPredicateLate = 0;
92  let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
93
94  // New-value insn helper fields.
95  bits<1> isNewValue = 0;
96  let TSFlags{13} = isNewValue; // New-value consumer insn.
97  bits<1> hasNewValue = 0;
98  let TSFlags{14} = hasNewValue; // New-value producer insn.
99  bits<3> opNewValue = 0;
100  let TSFlags{17-15} = opNewValue; // New-value produced operand.
101  bits<1> isNVStorable = 0;
102  let TSFlags{18} = isNVStorable; // Store that can become new-value store.
103  bits<1> isNVStore = 0;
104  let TSFlags{19} = isNVStore; // New-value store insn.
105  bits<1> isCVLoadable = 0;
106  let TSFlags{20} = isCVLoadable; // Load that can become cur-value load.
107  bits<1> isCVLoad = 0;
108  let TSFlags{21} = isCVLoad; // Cur-value load insn.
109
110  // Immediate extender helper fields.
111  bits<1> isExtendable = 0;
112  let TSFlags{22} = isExtendable; // Insn may be extended.
113  bits<1> isExtended = 0;
114  let TSFlags{23} = isExtended; // Insn must be extended.
115  bits<3> opExtendable = 0;
116  let TSFlags{26-24} = opExtendable; // Which operand may be extended.
117  bits<1> isExtentSigned = 0;
118  let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
119  bits<5> opExtentBits = 0;
120  let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending.
121  bits<2> opExtentAlign = 0;
122  let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
123
124  bit cofMax1 = 0;
125  let TSFlags{35} = cofMax1;
126  bit cofRelax1 = 0;
127  let TSFlags{36} = cofRelax1;
128  bit cofRelax2 = 0;
129  let TSFlags{37} = cofRelax2;
130
131  bit isRestrictNoSlot1Store = 0;
132  let TSFlags{38} = isRestrictNoSlot1Store;
133
134  // Addressing mode for load/store instructions.
135  AddrModeType addrMode = NoAddrMode;
136  let TSFlags{43-41} = addrMode.Value;
137
138  // Memory access size for mem access instructions (load/store)
139  MemAccessSize accessSize = NoMemAccess;
140  let TSFlags{47-44} = accessSize.Value;
141
142  bits<1> isTaken = 0;
143  let TSFlags {48} = isTaken; // Branch prediction.
144
145  bits<1> isFP = 0;
146  let TSFlags {49} = isFP; // Floating-point.
147
148  bits<1> isSomeOK = 0;
149  let TSFlags {50} = isSomeOK; // Relax some grouping constraints.
150
151  bits<1> hasNewValue2 = 0;
152  let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
153  bits<3> opNewValue2 = 0;
154  let TSFlags{54-52} = opNewValue2; // Second New-value produced operand.
155
156  bits<1> isAccumulator = 0;
157  let TSFlags{55} = isAccumulator;
158
159  bits<1> prefersSlot3 = 0;
160  let TSFlags{56} = prefersSlot3; // Complex XU
161
162  bits<1> hasTmpDst = 0;
163  let TSFlags{59} = hasTmpDst;  // v65 : 'fake" register VTMP is set
164
165  bit CVINew = 0;
166  let TSFlags{61} = CVINew;
167
168  // Fields used for relation models.
169  bit isNonTemporal = 0;
170  string isNT = ""; // set to "true" for non-temporal vector stores.
171  string BaseOpcode = "";
172  string CextOpcode = "";
173  string PredSense = "";
174  string PNewValue = "";
175  string NValueST  = "";    // Set to "true" for new-value stores.
176  string InputType = "";    // Input is "imm" or "reg" type.
177  string isFloat = "false"; // Set to "true" for the floating-point load/store.
178  string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
179
180  let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
181                                    "");
182  let PNewValue = !if(isPredicatedNew, "new", "");
183  let NValueST = !if(isNVStore, "true", "false");
184  let isNT = !if(isNonTemporal, "true", "false");
185
186  let hasSideEffects = 0;
187  // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
188}
189
190class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
191      InstHexagon<outs, ins, asmstr, [], "", itin, type>;
192
193//===----------------------------------------------------------------------===//
194//                         Instruction Classes Definitions +
195//===----------------------------------------------------------------------===//
196
197// LD Instruction Class in V2/V3/V4.
198// Definition of the instruction class NOT CHANGED.
199let mayLoad = 1 in
200class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
201             string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
202  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
203
204class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
205             string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
206  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
207
208// ST Instruction Class in V2/V3 can take SLOT0 only.
209// ST Instruction Class in V4    can take SLOT0 & SLOT1.
210// Definition of the instruction class CHANGED from V2/V3 to V4.
211let mayStore = 1 in
212class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213             string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
214  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
215
216let isCodeGenOnly = 1, isPseudo = 1 in
217class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
218              string cstr = "", InstrItinClass itin = tc_ENDLOOP>
219  : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
220    OpcodeHexagon;
221
222let isCodeGenOnly = 1, isPseudo = 1 in
223class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
224             string cstr = "">
225  : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
226    OpcodeHexagon;
227
228let isCodeGenOnly = 1, isPseudo = 1 in
229class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
230              string cstr="">
231  : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
232    OpcodeHexagon;
233
234//===----------------------------------------------------------------------===//
235//                         Instruction Classes Definitions -
236//===----------------------------------------------------------------------===//
237
238//===----------------------------------------------------------------------===//
239// V4 Instruction Format Definitions +
240//===----------------------------------------------------------------------===//
241
242include "HexagonInstrFormatsV4.td"
243
244//===----------------------------------------------------------------------===//
245// V60+ Instruction Format Definitions +
246//===----------------------------------------------------------------------===//
247
248include "HexagonInstrFormatsV60.td"
249include "HexagonInstrFormatsV65.td"
250