1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
2
3; The memory operand was dropped from the buffer_load_dword_offset
4; when replaced with the addr64 during operand legalization, resulting
5; in the global loads not being scheduled together.
6
7; GCN-LABEL: {{^}}reschedule_global_load_lds_store:
8; GCN: buffer_load_dword
9; GCN: buffer_load_dword
10; GCN: ds_write2_b32
11; GCN: s_endpgm
12define amdgpu_kernel void @reschedule_global_load_lds_store(i32 addrspace(1)* noalias %gptr0, i32 addrspace(1)* noalias %gptr1, i32 addrspace(3)* noalias %lptr, i32 %c) #0 {
13entry:
14  %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1
15  %idx = shl i32 %tid, 2
16  %gep0 = getelementptr i32, i32 addrspace(1)* %gptr0, i32 %idx
17  %gep1 = getelementptr i32, i32 addrspace(1)* %gptr1, i32 %idx
18  %gep2 = getelementptr i32, i32 addrspace(3)* %lptr, i32 %tid
19  %cmp0 = icmp eq i32 %c, 0
20  br i1 %cmp0, label %for.body, label %exit
21
22for.body:                                         ; preds = %for.body, %entry
23  %i = phi i32 [ 0, %entry ], [ %i.inc, %for.body ]
24  %gptr0.phi = phi i32 addrspace(1)* [ %gep0, %entry ], [ %gep0.inc, %for.body ]
25  %gptr1.phi = phi i32 addrspace(1)* [ %gep1, %entry ], [ %gep1.inc, %for.body ]
26  %lptr0.phi = phi i32 addrspace(3)* [ %gep2, %entry ], [ %gep2.inc, %for.body ]
27  %lptr1 = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 2
28  %val0 = load i32, i32 addrspace(1)* %gep0
29  store i32 %val0, i32 addrspace(3)* %lptr0.phi
30  %val1 = load i32, i32 addrspace(1)* %gep1
31  store i32 %val1, i32 addrspace(3)* %lptr1
32  %gep0.inc = getelementptr i32, i32 addrspace(1)* %gptr0.phi, i32 4
33  %gep1.inc = getelementptr i32, i32 addrspace(1)* %gptr1.phi, i32 4
34  %gep2.inc = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 4
35  %i.inc = add nsw i32 %i, 1
36  %cmp1 = icmp ne i32 %i, 256
37  br i1 %cmp1, label %for.body, label %exit
38
39exit:                                             ; preds = %for.body, %entry
40  ret void
41}
42
43; Function Attrs: nounwind readnone
44declare i32 @llvm.amdgcn.workitem.id.x() #1
45
46attributes #0 = { nounwind }
47attributes #1 = { nounwind readnone }
48attributes #2 = { convergent nounwind }
49