1; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
2
3; Make sure high constant 0 isn't pointlessly materialized
4; GCN-LABEL: {{^}}trunc_bitcast_i64_lshr_32_i16:
5; GCN: s_waitcnt
6; GCN-NEXT: v_mov_b32_e32 v0, v1
7; GCN-NEXT: s_setpc_b64
8define i16 @trunc_bitcast_i64_lshr_32_i16(i64 %bar) {
9  %srl = lshr i64 %bar, 32
10  %trunc = trunc i64 %srl to i16
11  ret i16 %trunc
12}
13
14; GCN-LABEL: {{^}}trunc_bitcast_i64_lshr_32_i32:
15; GCN: s_waitcnt
16; GCN-NEXT: v_mov_b32_e32 v0, v1
17; GCN-NEXT: s_setpc_b64
18define i32 @trunc_bitcast_i64_lshr_32_i32(i64 %bar) {
19  %srl = lshr i64 %bar, 32
20  %trunc = trunc i64 %srl to i32
21  ret i32 %trunc
22}
23
24; GCN-LABEL: {{^}}trunc_bitcast_v2i32_to_i16:
25; GCN: _load_dword
26; GCN-NOT: _load_dword
27; GCN-NOT: v_mov_b32
28; GCN: v_add_u32_e32 v0, vcc, 4, v0
29define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
30  %load0 = load i32, i32 addrspace(1)* undef
31  %load1 = load i32, i32 addrspace(1)* null
32  %insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
33  %insert.1 = insertelement <2 x i32> %insert.0, i32 99, i32 1
34  %bc = bitcast <2 x i32> %insert.1 to i64
35  %trunc = trunc i64 %bc to i16
36  %add = add i16 %trunc, 4
37  ret i16 %add
38}
39
40; Make sure there's no crash if the source vector type is FP
41; GCN-LABEL: {{^}}trunc_bitcast_v2f32_to_i16:
42; GCN: _load_dword
43; GCN-NOT: _load_dword
44; GCN-NOT: v_mov_b32
45; GCN: v_add_u32_e32 v0, vcc, 4, v0
46define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
47  %load0 = load float, float addrspace(1)* undef
48  %load1 = load float, float addrspace(1)* null
49  %insert.0 = insertelement <2 x float> undef, float %load0, i32 0
50  %insert.1 = insertelement <2 x float> %insert.0, float 4.0, i32 1
51  %bc = bitcast <2 x float> %insert.1 to i64
52  %trunc = trunc i64 %bc to i16
53  %add = add i16 %trunc, 4
54  ret i16 %add
55}
56
57; GCN-LABEL: {{^}}truncate_high_elt_extract_vector:
58; GCN: s_load_dword s
59; GCN: s_load_dword s
60; GCN: s_sext_i32_i16
61; GCN: s_sext_i32_i16
62; GCN: v_mul_i32_i24
63; GCN: v_lshrrev_b32_e32
64define amdgpu_kernel void @truncate_high_elt_extract_vector(<2 x i16> addrspace(1)* nocapture readonly %arg, <2 x i16> addrspace(1)* nocapture readonly %arg1, <2 x i16> addrspace(1)* nocapture %arg2) local_unnamed_addr {
65bb:
66  %tmp = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg, i64 undef
67  %tmp3 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp, align 4
68  %tmp4 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg1, i64 undef
69  %tmp5 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp4, align 4
70  %tmp6 = sext <2 x i16> %tmp3 to <2 x i32>
71  %tmp7 = sext <2 x i16> %tmp5 to <2 x i32>
72  %tmp8 = extractelement <2 x i32> %tmp6, i64 0
73  %tmp9 = extractelement <2 x i32> %tmp7, i64 0
74  %tmp10 = mul nsw i32 %tmp9, %tmp8
75  %tmp11 = insertelement <2 x i32> undef, i32 %tmp10, i32 0
76  %tmp12 = insertelement <2 x i32> %tmp11, i32 undef, i32 1
77  %tmp13 = lshr <2 x i32> %tmp12, <i32 16, i32 16>
78  %tmp14 = trunc <2 x i32> %tmp13 to <2 x i16>
79  %tmp15 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg2, i64 undef
80  store <2 x i16> %tmp14, <2 x i16> addrspace(1)* %tmp15, align 4
81  ret void
82}
83