1; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
2
3target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
4target triple = "armv7-eabi"
5
6%foo = type { <4 x float> }
7
8define arm_aapcs_vfpcc void @bar(%foo* noalias sret %agg.result, <4 x float> %quat.0) nounwind {
9entry:
10  %quat_addr = alloca %foo, align 16              ; <%foo*> [#uses=2]
11  %0 = getelementptr inbounds %foo, %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
12  store <4 x float> %quat.0, <4 x float>* %0
13  %1 = call arm_aapcs_vfpcc  <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3]
14  %2 = fmul <4 x float> %1, %1                    ; <<4 x float>> [#uses=2]
15  %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 0, i32 1> ; <<2 x float>> [#uses=1]
16  %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> <i32 2, i32 3> ; <<2 x float>> [#uses=1]
17;CHECK-NOT: vmov
18;CHECK: vpadd
19  %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2]
20  %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2]
21  %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2]
22;CHECK: vorr
23  %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3]
24  %9 = fmul <4 x float> %8, %8                    ; <<4 x float>> [#uses=1]
25  %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
26  %11 = fmul <4 x float> %10, %8                  ; <<4 x float>> [#uses=1]
27  %12 = fmul <4 x float> %11, %1                  ; <<4 x float>> [#uses=1]
28  %13 = call arm_aapcs_vfpcc  %foo* @baz(%foo* %agg.result, <4 x float> %12) nounwind ; <%foo*> [#uses=0]
29  ret void
30}
31
32declare arm_aapcs_vfpcc %foo* @baz(%foo*, <4 x float>) nounwind
33
34declare arm_aapcs_vfpcc <4 x float> @quux(%foo* nocapture) nounwind readonly
35
36declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
37
38declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
39
40declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
41