1; RUN: llc -O1 -mattr=+splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs -disable-a15-sd-optimization < %s | FileCheck -check-prefixes=CHECK,CHECK-DISABLED %s
2; RUN: llc -O1 -mattr=-splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs                              < %s | FileCheck -check-prefixes=CHECK,CHECK-DISABLED %s
3; RUN: llc -O1 -mattr=+splat-vfp-neon -mtriple=armv7-linux-gnueabi -verify-machineinstrs                              < %s | FileCheck -check-prefixes=CHECK,CHECK-ENABLED  %s
4
5; CHECK-LABEL: t1:
6define <2 x float> @t1(float %f) {
7  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
8  ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
9  %i1 = insertelement <2 x float> undef, float %f, i32 1
10  %i2 = fadd <2 x float> %i1, %i1
11  ret <2 x float> %i2
12}
13
14; CHECK-LABEL: t2:
15define <4 x float> @t2(float %g, float %f) {
16  ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
17  ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
18  %i1 = insertelement <4 x float> undef, float %f, i32 1
19  %i2 = fadd <4 x float> %i1, %i1
20  ret <4 x float> %i2
21}
22
23; CHECK-LABEL: t3:
24define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
25  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
26  ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
27  %i1 = insertelement <2 x float> undef, float %f, i32 1
28  %i2 = fadd <2 x float> %i1, %i1
29  ret <2 x float> %i2
30}
31
32; CHECK-LABEL: t4:
33define <2 x float> @t4(float %f) {
34  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
35  ; CHECK-DISABLED-NOT: vdup
36  %i1 = insertelement <2 x float> undef, float %f, i32 1
37  br label %b
38
39  ; Block %b has an S-reg as live-in.
40b:
41  %i2 = fadd <2 x float> %i1, %i1
42  ret <2 x float> %i2
43}
44
45; CHECK-LABEL: t5:
46define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
47  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
48  ; CHECK-ENABLED: vadd.f32
49  ; CHECK-ENABLED-NEXT: bx lr
50  ; CHECK-DISABLED-NOT: vdup
51  %i1 = insertelement <4 x float> %q, float %f, i32 1
52  %i2 = fadd <4 x float> %i1, %i1
53  ret <4 x float> %i2
54}
55
56; Test that DPair can be successfully passed as QPR.
57; CHECK-LABEL: test_DPair1:
58define void @test_DPair1(i32 %vsout, i8* nocapture %out, float %x, float %y) {
59entry:
60  %0 = insertelement <4 x float> undef, float %x, i32 1
61  %1 = insertelement <4 x float> %0, float %y, i32 0
62  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
63  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
64  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
65  ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[1]
66  ; CHECK-DISABLED-NOT: vdup
67  switch i32 %vsout, label %sw.epilog [
68    i32 1, label %sw.bb
69    i32 0, label %sw.bb6
70  ]
71
72sw.bb:                                            ; preds = %entry
73  %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 0
74  br label %sw.bb6
75
76sw.bb6:                                           ; preds = %sw.bb, %entry
77  %sum.0 = phi <4 x float> [ %1, %entry ], [ %2, %sw.bb ]
78  %3 = extractelement <4 x float> %sum.0, i32 0
79  %conv = fptoui float %3 to i8
80  store i8 %conv, i8* %out, align 1
81  ret void
82
83sw.epilog:                                        ; preds = %entry
84  ret void
85}
86
87; CHECK-LABEL: test_DPair2:
88define void @test_DPair2(i32 %vsout, i8* nocapture %out, float %x) {
89entry:
90  %0 = insertelement <4 x float> undef, float %x, i32 0
91  ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d{{[0-9]*}}[0]
92  ; CHECK-DISABLED-NOT: vdup
93  switch i32 %vsout, label %sw.epilog [
94    i32 1, label %sw.bb
95    i32 0, label %sw.bb1
96  ]
97
98sw.bb:                                            ; preds = %entry
99  %1 = insertelement <4 x float> %0, float 0.000000e+00, i32 0
100  br label %sw.bb1
101
102sw.bb1:                                           ; preds = %entry, %sw.bb
103  %sum.0 = phi <4 x float> [ %0, %entry ], [ %1, %sw.bb ]
104  %2 = extractelement <4 x float> %sum.0, i32 0
105  %conv = fptoui float %2 to i8
106  store i8 %conv, i8* %out, align 1
107  br label %sw.epilog
108
109sw.epilog:                                        ; preds = %entry, %sw.bb1
110  ret void
111}
112