1; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-NODSP 2; RUN: llc -mtriple=thumbv7em %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP 3; RUN: llc -mtriple=thumbv8 %s -arm-disable-cgp=false -arm-enable-scalar-dsp=true -arm-enable-scalar-dsp-imms=true -o - | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-DSP-IMM 4 5; CHECK-COMMON-LABEL: test_ult_254_inc_imm: 6; CHECK-DSP: adds r0, #1 7; CHECK-DSP-NEXT: uxtb r1, r0 8; CHECK-DSP-NEXT: movs r0, #47 9; CHECK-DSP-NEXT: cmp r1, #254 10; CHECK-DSP-NEXT: it lo 11; CHECK-DSP-NEXT: movlo r0, #35 12 13; CHECK-DSP-IMM: movs r1, #1 14; CHECK-DSP-IMM-NEXT: uadd8 r1, r0, r1 15; CHECK-DSP-IMM-NEXT: movs r0, #47 16; CHECK-DSP-IMM-NEXT: cmp r1, #254 17; CHECK-DSP-IMM-NEXT: it lo 18; CHECK-DSP-IMM-NEXT: movlo r0, #35 19define i32 @test_ult_254_inc_imm(i8 zeroext %x) { 20entry: 21 %add = add i8 %x, 1 22 %cmp = icmp ult i8 %add, 254 23 %res = select i1 %cmp, i32 35, i32 47 24 ret i32 %res 25} 26 27; CHECK-COMMON-LABEL: test_slt_254_inc_imm 28; CHECK-COMMON: adds 29; CHECK-COMMON: sxtb 30define i32 @test_slt_254_inc_imm(i8 signext %x) { 31entry: 32 %add = add i8 %x, 1 33 %cmp = icmp slt i8 %add, 254 34 %res = select i1 %cmp, i32 35, i32 47 35 ret i32 %res 36} 37 38; CHECK-COMMON-LABEL: test_ult_254_inc_var: 39; CHECK-NODSP: add r0, r1 40; CHECK-NODSP-NEXT: uxtb r1, r0 41; CHECK-NODSP-NEXT: movs r0, #47 42; CHECK-NODSP-NEXT: cmp r1, #254 43; CHECK-NODSP-NEXT: it lo 44; CHECK-NODSP-NEXT: movlo r0, #35 45 46; CHECK-DSP: uadd8 r1, r0, r1 47; CHECK-DSP-NEXT: movs r0, #47 48; CHECK-DSP-NEXT: cmp r1, #254 49; CHECK-DSP-NEXT: it lo 50; CHECK-DSP-NEXT: movlo r0, #35 51define i32 @test_ult_254_inc_var(i8 zeroext %x, i8 zeroext %y) { 52entry: 53 %add = add i8 %x, %y 54 %cmp = icmp ult i8 %add, 254 55 %res = select i1 %cmp, i32 35, i32 47 56 ret i32 %res 57} 58 59; CHECK-COMMON-LABEL: test_sle_254_inc_var 60; CHECK-COMMON: add 61; CHECK-COMMON: sxtb 62; CHECK-COMMON: cmp 63define i32 @test_sle_254_inc_var(i8 %x, i8 %y) { 64entry: 65 %add = add i8 %x, %y 66 %cmp = icmp sle i8 %add, 254 67 %res = select i1 %cmp, i32 35, i32 47 68 ret i32 %res 69} 70 71; CHECK-COMMON-LABEL: test_ugt_1_dec_imm: 72; CHECK-COMMON: subs r1, r0, #1 73; CHECK-COMMON-NEXT: movs r0, #47 74; CHECK-COMMON-NEXT: cmp r1, #1 75; CHECK-COMMON-NEXT: it hi 76; CHECK-COMMON-NEXT: movhi r0, #35 77define i32 @test_ugt_1_dec_imm(i8 zeroext %x) { 78entry: 79 %add = add i8 %x, -1 80 %cmp = icmp ugt i8 %add, 1 81 %res = select i1 %cmp, i32 35, i32 47 82 ret i32 %res 83} 84 85; CHECK-COMMON-LABEL: test_sgt_1_dec_imm 86; CHECK-COMMON: subs 87; CHECK-COMMON: sxtb 88; CHECK-COMMON: cmp 89define i32 @test_sgt_1_dec_imm(i8 %x) { 90entry: 91 %add = add i8 %x, -1 92 %cmp = icmp sgt i8 %add, 1 93 %res = select i1 %cmp, i32 35, i32 47 94 ret i32 %res 95} 96 97; CHECK-COMMON-LABEL: test_ugt_1_dec_var: 98; CHECK-NODSP: subs r0, r0, r1 99; CHECK-NODSP-NEXT: uxtb r1, r0 100; CHECK-NODSP-NEXT: movs r0, #47 101; CHECK-NODSP-NEXT: cmp r1, #1 102; CHECK-NODSP-NEXT: it hi 103; CHECK-NODSP-NEXT: movhi r0, #35 104 105; CHECK-DSP: usub8 r1, r0, r1 106; CHECK-DSP-NEXT: movs r0, #47 107; CHECK-DSP-NEXT: cmp r1, #1 108; CHECK-DSP-NEXT: it hi 109; CHECK-DSP-NEXT: movhi r0, #35 110define i32 @test_ugt_1_dec_var(i8 zeroext %x, i8 zeroext %y) { 111entry: 112 %sub = sub i8 %x, %y 113 %cmp = icmp ugt i8 %sub, 1 114 %res = select i1 %cmp, i32 35, i32 47 115 ret i32 %res 116} 117 118; CHECK-COMMON-LABEL: test_sge_1_dec_var 119; CHECK-COMMON: sub 120; CHECK-COMMON: sxtb 121; CHECK-COMMON: cmp 122define i32 @test_sge_1_dec_var(i8 %x, i8 %y) { 123entry: 124 %sub = sub i8 %x, %y 125 %cmp = icmp sge i8 %sub, 1 126 %res = select i1 %cmp, i32 35, i32 47 127 ret i32 %res 128} 129 130; CHECK-COMMON-LABEL: dsp_imm1: 131; CHECK-DSP: eors r1, r0 132; CHECK-DSP-NEXT: and r0, r0, #7 133; CHECK-DSP-NEXT: subs r0, r0, r1 134; CHECK-DSP-NEXT: adds r0, #1 135; CHECK-DSP-NEXT: uxtb r1, r0 136; CHECK-DSP-NEXT: movs r0, #47 137; CHECK-DSP-NEXT: cmp r1, #254 138; CHECK-DSP-NEXT: it lo 139; CHECK-DSP-NEXT: movlo r0, #35 140 141; CHECK-DSP-IMM: eors r1, r0 142; CHECK-DSP-IMM-NEXT: and r0, r0, #7 143; CHECK-DSP-IMM-NEXT: usub8 r0, r0, r1 144; CHECK-DSP-IMM-NEXT: movs r1, #1 145; CHECK-DSP-IMM-NEXT: uadd8 r1, r0, r1 146; CHECK-DSP-IMM-NEXT: movs r0, #47 147; CHECK-DSP-IMM-NEXT: cmp r1, #254 148; CHECK-DSP-IMM-NEXT: it lo 149; CHECK-DSP-IMM-NEXT: movlo r0, #35 150define i32 @dsp_imm1(i8 zeroext %x, i8 zeroext %y) { 151entry: 152 %xor = xor i8 %x, %y 153 %and = and i8 %x, 7 154 %sub = sub i8 %and, %xor 155 %add = add i8 %sub, 1 156 %cmp = icmp ult i8 %add, 254 157 %res = select i1 %cmp, i32 35, i32 47 158 ret i32 %res 159} 160 161; CHECK-COMMON-LABEL: dsp_imm2 162; CHECK-COMMON: add r0, r1 163; CHECK-DSP-NEXT: ldrh r1, [r3] 164; CHECK-DSP-NEXT: ldrh r2, [r2] 165; CHECK-DSP-NEXT: subs r1, r1, r0 166; CHECK-DSP-NEXT: add r0, r2 167; CHECK-DSP-NEXT: uxth r3, r1 168; CHECK-DSP-NEXT: uxth r2, r0 169; CHECK-DSP-NEXT: cmp r2, r3 170 171; CHECK-DSP-IMM: movs r1, #0 172; CHECK-DSP-IMM-NEXT: uxth r0, r0 173; CHECK-DSP-IMM-NEXT: usub16 r1, r1, r0 174; CHECK-DSP-IMM-NEXT: ldrh r0, [r2] 175; CHECK-DSP-IMM-NEXT: ldrh r3, [r3] 176; CHECK-DSP-IMM-NEXT: usub16 r0, r0, r1 177; CHECK-DSP-IMM-NEXT: uadd16 r1, r3, r1 178; CHECK-DSP-IMM-NEXT: cmp r0, r1 179 180define i16 @dsp_imm2(i32 %arg0, i32 %arg1, i16* %gep0, i16* %gep1) { 181entry: 182 %add0 = add i32 %arg0, %arg1 183 %conv0 = trunc i32 %add0 to i16 184 %sub0 = sub i16 0, %conv0 185 %load0 = load i16, i16* %gep0, align 2 186 %load1 = load i16, i16* %gep1, align 2 187 %sub1 = sub i16 %load0, %sub0 188 %add1 = add i16 %load1, %sub0 189 %cmp = icmp ult i16 %sub1, %add1 190 %res = select i1 %cmp, i16 %add1, i16 %sub1 191 ret i16 %res 192} 193 194; CHECK-COMMON-LABEL: dsp_var: 195; CHECK-COMMON: eors r1, r0 196; CHECK-COMMON: and r2, r0, #7 197; CHECK-NODSP: subs r1, r2, r1 198; CHECK-NODSP: add.w r0, r1, r0, lsl #1 199; CHECK-NODSP: uxtb r1, r0 200; CHECK-DSP: usub8 r1, r2, r1 201; CHECK-DSP: lsls r0, r0, #1 202; CHECK-DSP: uadd8 r1, r1, r0 203; CHECK-DSP-NOT: uxt 204; CHECK-COMMON: movs r0, #47 205; CHECK-COMMON: cmp r1, #254 206; CHECK-COMMON: it lo 207; CHECK-COMMON: movlo r0, #35 208define i32 @dsp_var(i8 zeroext %x, i8 zeroext %y) { 209 %xor = xor i8 %x, %y 210 %and = and i8 %x, 7 211 %sub = sub i8 %and, %xor 212 %mul = shl nuw i8 %x, 1 213 %add = add i8 %sub, %mul 214 %cmp = icmp ult i8 %add, 254 215 %res = select i1 %cmp, i32 35, i32 47 216 ret i32 %res 217} 218 219; CHECK-COMMON-LABEL: store_dsp_res 220; CHECK-DSP: usub8 221; CHECK-DSP: strb 222define void @store_dsp_res(i8* %in, i8* %out, i8 %compare) { 223 %first = getelementptr inbounds i8, i8* %in, i32 0 224 %second = getelementptr inbounds i8, i8* %in, i32 1 225 %ld0 = load i8, i8* %first 226 %ld1 = load i8, i8* %second 227 %xor = xor i8 %ld0, -1 228 %cmp = icmp ult i8 %compare, %ld1 229 %select = select i1 %cmp, i8 %compare, i8 %xor 230 %sub = sub i8 %ld0, %select 231 store i8 %sub, i8* %out, align 1 232 ret void 233} 234 235; CHECK-COMMON-LABEL: ugt_1_dec_imm: 236; CHECK-COMMON: subs r1, r0, #1 237; CHECK-COMMON-NEXT: movs r0, #47 238; CHECK-COMMON-NEXT: cmp r1, #1 239; CHECK-COMMON-NEXT: it hi 240; CHECK-COMMON-NEXT: movhi r0, #35 241define i32 @ugt_1_dec_imm(i8 zeroext %x) { 242entry: 243 %add = add i8 %x, -1 244 %cmp = icmp ugt i8 %add, 1 245 %res = select i1 %cmp, i32 35, i32 47 246 ret i32 %res 247} 248 249; CHECK-COMMON-LABEL: ugt_1_dec_var: 250; CHECK-NODSP: subs r0, r0, r1 251; CHECK-NODSP-NEXT: uxtb r1, r0 252; CHECK-NODSP-NEXT: movs r0, #47 253; CHECK-NODSP-NEXT: cmp r1, #1 254; CHECK-NODSP-NEXT: it hi 255; CHECK-NODSP-NEXT: movhi r0, #35 256 257; CHECK-DSP: usub8 r1, r0, r1 258; CHECK-DSP-NEXT: movs r0, #47 259; CHECK-DSP-NEXT: cmp r1, #1 260; CHECK-DSP-NEXT: it hi 261; CHECK-DSP-NEXT: movhi r0, #35 262define i32 @ugt_1_dec_var(i8 zeroext %x, i8 zeroext %y) { 263entry: 264 %sub = sub i8 %x, %y 265 %cmp = icmp ugt i8 %sub, 1 266 %res = select i1 %cmp, i32 35, i32 47 267 ret i32 %res 268} 269 270; CHECK-COMMON-LABEL: icmp_i32_zext: 271; CHECK-COMMON: ldrb [[LD:r[^ ]+]], [r0] 272; CHECK-COMMON: subs [[SUB:r[^ ]+]], [[LD]], #1 273; CHECK-COMMON-NOT: uxt 274; CHECK-COMMON: cmp [[LD]], [[SUB]] 275; CHECK-COMMON-NOT: uxt 276define i8 @icmp_i32_zext(i8* %ptr) { 277entry: 278 %gep = getelementptr inbounds i8, i8* %ptr, i32 0 279 %0 = load i8, i8* %gep, align 1 280 %1 = sub nuw nsw i8 %0, 1 281 %conv44 = zext i8 %0 to i32 282 br label %preheader 283 284preheader: 285 br label %body 286 287body: 288 %2 = phi i8 [ %1, %preheader ], [ %3, %if.end ] 289 %si.0274 = phi i32 [ %conv44, %preheader ], [ %inc, %if.end ] 290 %conv51266 = zext i8 %2 to i32 291 %cmp52267 = icmp eq i32 %si.0274, %conv51266 292 br i1 %cmp52267, label %if.end, label %exit 293 294if.end: 295 %inc = add i32 %si.0274, 1 296 %gep1 = getelementptr inbounds i8, i8* %ptr, i32 %inc 297 %3 = load i8, i8* %gep1, align 1 298 br label %body 299 300exit: 301 ret i8 %2 302} 303 304@d_uch = hidden local_unnamed_addr global [16 x i8] zeroinitializer, align 1 305@sh1 = hidden local_unnamed_addr global i16 0, align 2 306@d_sh = hidden local_unnamed_addr global [16 x i16] zeroinitializer, align 2 307 308; CHECK-COMMON-LABEL: icmp_sext_zext_store_i8_i16 309; CHECK-NODSP: ldrb [[BYTE:r[^ ]+]], 310; CHECK-NODSP: strh [[BYTE]], 311; CHECK-NODSP: ldrsh.w 312define i32 @icmp_sext_zext_store_i8_i16() { 313entry: 314 %0 = load i8, i8* getelementptr inbounds ([16 x i8], [16 x i8]* @d_uch, i32 0, i32 2), align 1 315 %conv = zext i8 %0 to i16 316 store i16 %conv, i16* @sh1, align 2 317 %conv1 = zext i8 %0 to i32 318 %1 = load i16, i16* getelementptr inbounds ([16 x i16], [16 x i16]* @d_sh, i32 0, i32 2), align 2 319 %conv2 = sext i16 %1 to i32 320 %cmp = icmp eq i32 %conv1, %conv2 321 %conv3 = zext i1 %cmp to i32 322 ret i32 %conv3 323} 324 325; CHECK-COMMON-LABEL: or_icmp_ugt: 326; CHECK-COMMON: ldrb [[LD:r[^ ]+]], [r1] 327; CHECK-COMMON: subs [[SUB:r[^ ]+]], #1 328; CHECK-COMMON-NOT: uxtb 329; CHECK-COMMON: cmp [[SUB]], #3 330define i1 @or_icmp_ugt(i32 %arg, i8* %ptr) { 331entry: 332 %0 = load i8, i8* %ptr 333 %1 = zext i8 %0 to i32 334 %mul = shl nuw nsw i32 %1, 1 335 %add0 = add nuw nsw i32 %mul, 6 336 %cmp0 = icmp ne i32 %arg, %add0 337 %add1 = add i8 %0, -1 338 %cmp1 = icmp ugt i8 %add1, 3 339 %or = or i1 %cmp0, %cmp1 340 ret i1 %or 341} 342 343; CHECK-COMMON-LABEL: icmp_switch_trunc: 344; CHECK-COMMON-NOT: uxt 345define i16 @icmp_switch_trunc(i16 zeroext %arg) { 346entry: 347 %conv = add nuw i16 %arg, 15 348 %mul = mul nuw nsw i16 %conv, 3 349 %trunc = trunc i16 %arg to i3 350 switch i3 %trunc, label %default [ 351 i3 0, label %sw.bb 352 i3 1, label %sw.bb.i 353 ] 354 355sw.bb: 356 %cmp0 = icmp ult i16 %mul, 127 357 %select = select i1 %cmp0, i16 %mul, i16 127 358 br label %exit 359 360sw.bb.i: 361 %cmp1 = icmp ugt i16 %mul, 34 362 %select.i = select i1 %cmp1, i16 %mul, i16 34 363 br label %exit 364 365default: 366 br label %exit 367 368exit: 369 %res = phi i16 [ %select, %sw.bb ], [ %select.i, %sw.bb.i ], [ %mul, %default ] 370 ret i16 %res 371} 372 373; CHECK-COMMON-LABEL: icmp_eq_minus_one 374; CHECK-COMMON: cmp r0, #255 375define i32 @icmp_eq_minus_one(i8* %ptr) { 376 %load = load i8, i8* %ptr, align 1 377 %conv = zext i8 %load to i32 378 %cmp = icmp eq i8 %load, -1 379 %ret = select i1 %cmp, i32 %conv, i32 -1 380 ret i32 %ret 381} 382 383; CHECK-COMMON-LABEL: icmp_not 384; CHECK-COMMON: movw r2, #65535 385; CHECK-COMMON: eors r2, r0 386; CHECK-COMMON: movs r0, #32 387; CHECK-COMMON: cmp r2, r1 388define i32 @icmp_not(i16 zeroext %arg0, i16 zeroext %arg1) { 389 %not = xor i16 %arg0, -1 390 %cmp = icmp eq i16 %not, %arg1 391 %res = select i1 %cmp, i32 16, i32 32 392 ret i32 %res 393} 394 395; CHECK-COMMON-LABEL: mul_wrap 396; CHECK-COMMON: mul 397; CHECK-COMMON: uxth 398; CHECK-COMMON: cmp 399define i16 @mul_wrap(i16 %arg0, i16 %arg1) { 400 %mul = mul i16 %arg0, %arg1 401 %cmp = icmp eq i16 %mul, 1 402 %res = select i1 %cmp, i16 %arg0, i16 47 403 ret i16 %res 404} 405 406; CHECK-COMMON-LABEL: shl_wrap 407; CHECK-COMMON: lsl 408; CHECK-COMMON: uxth 409; CHECK-COMMON: cmp 410define i16 @shl_wrap(i16 %arg0) { 411 %mul = shl i16 %arg0, 4 412 %cmp = icmp eq i16 %mul, 1 413 %res = select i1 %cmp, i16 %arg0, i16 47 414 ret i16 %res 415} 416 417; CHECK-COMMON-LABEL: add_wrap 418; CHECK-COMMON: add 419; CHECK-COMMON: uxth 420; CHECK-COMMON: cmp 421define i16 @add_wrap(i16 %arg0, i16 %arg1) { 422 %add = add i16 %arg0, 128 423 %cmp = icmp eq i16 %add, %arg1 424 %res = select i1 %cmp, i16 %arg0, i16 1 425 ret i16 %res 426} 427 428; CHECK-COMMON-LABEL: sub_wrap 429; CHECK-COMMON: sub 430; CHECK-COMMON: uxth 431; CHECK-COMMON: cmp 432define i16 @sub_wrap(i16 %arg0, i16 %arg1, i16 %arg2) { 433 %sub = sub i16 %arg0, %arg2 434 %cmp = icmp eq i16 %sub, %arg1 435 %res = select i1 %cmp, i16 %arg0, i16 1 436 ret i16 %res 437} 438 439; CHECK-COMMON-LABEL: urem_trunc_icmps 440; CHECK-COMMON-NOT: uxt 441define void @urem_trunc_icmps(i16** %in, i32* %g, i32* %k) { 442entry: 443 %ptr = load i16*, i16** %in, align 4 444 %ld = load i16, i16* %ptr, align 2 445 %cmp.i = icmp eq i16 %ld, 0 446 br i1 %cmp.i, label %exit, label %cond.false.i 447 448cond.false.i: 449 %rem = urem i16 5, %ld 450 %extract.t = trunc i16 %rem to i8 451 br label %body 452 453body: 454 %cond.in.i.off0 = phi i8 [ %extract.t, %cond.false.i ], [ %add, %for.inc ] 455 %cmp = icmp ugt i8 %cond.in.i.off0, 7 456 %conv5 = zext i1 %cmp to i32 457 store i32 %conv5, i32* %g, align 4 458 %.pr = load i32, i32* %k, align 4 459 %tobool13150 = icmp eq i32 %.pr, 0 460 br i1 %tobool13150, label %for.inc, label %exit 461 462for.inc: 463 %add = add nuw i8 %cond.in.i.off0, 1 464 br label %body 465 466exit: 467 ret void 468} 469