1; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s 2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s 3; check if regs are passing correctly 4define void @i64_write(i64* %p, i64 %val) nounwind { 5; CHECK-LABEL: i64_write: 6; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 7; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} 8 %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind 9 ret void 10} 11 12; check if register allocation can reuse the registers 13define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind { 14entry: 15; CHECK-LABEL: multi_writes: 16; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 17; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 18; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 19; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 20; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 21; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 22 23; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 24; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 25; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 26; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 27; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 28; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 29 30; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 31; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 32; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 33; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 34; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 35; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 36 37 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind 38 %incdec.ptr = getelementptr inbounds i64, i64* %p, i32 1 39 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind 40 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind 41 ret void 42} 43 44 45; check if callee-saved registers used by inline asm are saved/restored 46define void @foo(i64* %p, i64 %i) nounwind { 47; CHECK-LABEL:foo: 48; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}} 49; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}] 50; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} 51; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}} 52 %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind 53 ret void 54} 55 56; return *p; 57define i64 @ldrd_test(i64* %p) nounwind { 58; CHECK-LABEL: ldrd_test: 59 %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind 60 ret i64 %1 61} 62 63define i64 @QR_test(i64* %p) nounwind { 64; CHECK-LABEL: QR_test: 65; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} 66 %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind 67 ret i64 %1 68} 69 70define i64 @defuse_test(i64 %p) nounwind { 71; CHECK-LABEL: defuse_test: 72; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1 73 %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind 74 ret i64 %1 75} 76 77; *p = (hi << 32) | lo; 78define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind { 79; CHECK-LABEL: strd_test: 80; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} 81 %1 = zext i32 %hi to i64 82 %2 = shl nuw i64 %1, 32 83 %3 = sext i32 %lo to i64 84 %4 = or i64 %2, %3 85 tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind 86 ret void 87} 88 89; Make sure we don't untie operands by mistake. 90define i64 @tied_64bit_test(i64 %in) nounwind { 91; CHECK-LABEL: tied_64bit_test: 92; CHECK: OUT([[OUTREG:r[0-9]+]]), IN([[OUTREG]]) 93 %addr = alloca i64 94 call void asm "OUT($0), IN($1)", "=*rm,0"(i64* %addr, i64 %in) 95 ret i64 %in 96} 97 98; If we explicitly name a tied operand, then the code should lookup the operand 99; we were tied to for information about register class and so on. 100define i64 @tied_64bit_lookback_test(i64 %in) nounwind { 101; CHECK-LABEL: tied_64bit_lookback_test: 102; CHECK: OUTLO([[LO:r[0-9]+]]) OUTHI([[HI:r[0-9]+]]) INLO([[LO]]) INHI([[HI]]) 103 %vars = call {i64, i32, i64} asm "OUTLO(${2:Q}) OUTHI(${2:R}) INLO(${3:Q}) INHI(${3:R})", "=r,=r,=r,2"(i64 %in) 104 %res = extractvalue {i64, i32, i64} %vars, 2 105 ret i64 %res 106} 107 108; Check access to low and high part with a specific register pair constraint 109define i64 @low_high_specific_reg_pair(i64 %in) nounwind { 110; CHECK-LABEL: low_high_specific_reg_pair 111; CHECK: mov r3, r2 112 %res = call i64 asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(i64 %in) 113 ret i64 %res 114} 115