1; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
2
3define void @coproc(i8* %i) nounwind {
4entry:
5  ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
6  %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
7  ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
8  tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
9  ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
10  %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
11  ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
12  tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
13  ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
14  tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
15  ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
16  tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
17  ; CHECK: cdp p7, #3, c1, c1, c1, #5
18  tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
19  ; CHECK: cdp2 p7, #3, c1, c1, c1, #5
20  tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
21  ; CHECK: ldc p7, c3, [r{{[0-9]+}}]
22  tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
23  ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
24  tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
25  ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
26  tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
27  ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
28  tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
29  ; CHECK: stc p7, c3, [r{{[0-9]+}}]
30  tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
31  ; CHECK: stcl p7, c3, [r{{[0-9]+}}]
32  tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
33  ; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
34  tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
35  ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
36  tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
37  ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
38  %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
39  ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
40  %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
41  ret void
42}
43
44declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
45
46declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
47
48declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
49
50declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
51
52declare void @llvm.arm.stc(i32, i32, i8*) nounwind
53
54declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
55
56declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
57
58declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
59
60declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
61
62declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
63
64declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
65
66declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
67
68declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
69
70declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
71
72declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
73
74declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
75
76declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
77
78declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
79