1; REQUIRES: asserts
2; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \
3; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
4; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \
5; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
6; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \
7; RUN:   /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
8;
9; Check the latency of instructions for processors with sched-models
10;
11; Function Attrs: norecurse nounwind readnone
12define i32 @foo(float %a, float %b, float %c, i32 %d) local_unnamed_addr #0 {
13entry:
14;
15; CHECK:       ********** MI Scheduling **********
16; CHECK_A9:    VADDS
17; CHECK_SWIFT: VADDfd
18; CHECK_R52:   VADDS
19; CHECK_A9:    Latency    : 5
20; CHECK_SWIFT: Latency    : 4
21; CHECK_R52:   Latency    : 6
22;
23; CHECK_A9:    VMULS
24; CHECK_SWIFT: VMULfd
25; CHECK_R52:   VMULS
26; CHECK_SWIFT: Latency    : 4
27; CHECK_A9:    Latency    : 6
28; CHECK_R52:   Latency    : 6
29;
30; CHECK:       VDIVS
31; CHECK_SWIFT: Latency    : 17
32; CHECK_A9:    Latency    : 16
33; CHECK_R52:   Latency    : 7
34;
35; CHECK:       VCVTDS
36; CHECK_SWIFT: Latency    : 4
37; CHECK_A9:    Latency    : 5
38; CHECK_R52:   Latency    : 6
39;
40; CHECK:       VADDD
41; CHECK_SWIFT: Latency    : 6
42; CHECK_A9:    Latency    : 5
43; CHECK_R52:   Latency    : 6
44;
45; CHECK:       VMULD
46; CHECK_SWIFT: Latency    : 6
47; CHECK_A9:    Latency    : 7
48; CHECK_R52:   Latency    : 6
49;
50; CHECK:       VDIVD
51; CHECK_SWIFT: Latency    : 32
52; CHECK_A9:    Latency    : 26
53; CHECK_R52:   Latency    : 17
54;
55; CHECK:       VTOSIZD
56; CHECK_SWIFT: Latency    : 4
57; CHECK_A9:    Latency    : 5
58; CHECK_R52:   Latency    : 6
59;
60  %add = fadd float %a, %b
61  %mul = fmul float %add, %add
62  %div = fdiv float %mul, %b
63  %conv1 = fpext float %div to double
64  %add3 = fadd double %conv1, %conv1
65  %mul4 = fmul double %add3, %add3
66  %div5 = fdiv double %mul4, %conv1
67  %conv6 = fptosi double %div5 to i32
68  ret i32 %conv6
69}
70