1; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding -t2-reduce-limit=0 -t2-reduce-limit2=0 %s | FileCheck %s
2; RUN: llc -mtriple=thumbv7-linux-gnueabihf -o - -show-mc-encoding %s | FileCheck %s --check-prefix=CHECK-OPT
3
4define i32 @and(i32 %a, i32 %b) nounwind readnone {
5; CHECK-LABEL: and:
6; CHECK: and.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
7; CHECK-OPT: ands r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
8entry:
9  %and = and i32 %b, %a
10  ret i32 %and
11}
12
13define i32 @asr-imm(i32 %a) nounwind readnone {
14; CHECK-LABEL: "asr-imm":
15; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
16; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}}, #13 @ encoding: [{{0x..,0x..}}]
17entry:
18  %shr = ashr i32 %a, 13
19  ret i32 %shr
20}
21
22define i32 @asr-reg(i32 %a, i32 %b) nounwind readnone {
23; CHECK-LABEL: "asr-reg":
24; CHECK: asr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
25; CHECK-OPT: asrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
26entry:
27  %shr = ashr i32 %a, %b
28  ret i32 %shr
29}
30
31define i32 @bic(i32 %a, i32 %b) nounwind readnone {
32; CHECK-LABEL: bic:
33; CHECK: bic.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
34; CHECK-OPT: bics r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
35entry:
36  %neg = xor i32 %b, -1
37  %and = and i32 %neg, %a
38  ret i32 %and
39}
40
41define i32 @eor(i32 %a, i32 %b) nounwind readnone {
42; CHECK-LABEL: eor:
43; CHECK: eor.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
44; CHECK-OPT: eors r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
45entry:
46  %eor = xor i32 %a, %b
47  ret i32 %eor
48}
49
50define i32 @lsl-imm(i32 %a) nounwind readnone {
51; CHECK-LABEL: "lsl-imm":
52; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
53; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}}, #13  @ encoding: [{{0x..,0x..}}]
54entry:
55  %shl = shl i32 %a, 13
56  ret i32 %shl
57}
58
59define i32 @lsl-reg(i32 %a, i32 %b) nounwind readnone {
60; CHECK-LABEL: "lsl-reg":
61; CHECK: lsl.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
62; CHECK-OPT: lsls r{{[0-7]}}, r{{[0-7]}}  @ encoding: [{{0x..,0x..}}]
63entry:
64  %shl = shl i32 %a, %b
65  ret i32 %shl
66}
67
68define i32 @lsr-imm(i32 %a) nounwind readnone {
69; CHECK-LABEL: "lsr-imm":
70; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, #13 @ encoding: [{{0x..,0x..,0x..,0x..}}]
71; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}, #13  @ encoding: [{{0x..,0x..}}]
72entry:
73  %shr = lshr i32 %a, 13
74  ret i32 %shr
75}
76
77define i32 @lsr-reg(i32 %a, i32 %b) nounwind readnone {
78; CHECK-LABEL: "lsr-reg":
79; CHECK: lsr.w r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} @ encoding: [{{0x..,0x..,0x..,0x..}}]
80; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}}  @ encoding: [{{0x..,0x..}}]
81entry:
82  %shr = lshr i32 %a, %b
83  ret i32 %shr
84}
85
86define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize {
87; CHECK-LABEL: bundled_instruction:
88; CHECK: iteee	ne
89; CHECK: ldmeq	r0!, {{{r[0-9]+}}}
90  br i1 %tst, label %true, label %false
91
92true:
93  ret i32 0
94
95false:
96  %res = load i32, i32* %addr, align 4
97  %next = getelementptr i32, i32* %addr, i32 1
98  store i32* %next, i32** %addr2
99  ret i32 %res
100}
101
102; ldm instructions fault on misaligned accesses so we mustn't convert
103; this post-indexed ldr into one.
104define i32* @misaligned_post(i32* %src, i32* %dest) minsize {
105; CHECK-LABEL: misaligned_post:
106; CHECK: ldr [[VAL:.*]], [r0], #4
107; CHECK: str [[VAL]], [r1]
108
109  %val = load i32, i32* %src, align 1
110  store i32 %val, i32* %dest
111  %next = getelementptr i32, i32* %src, i32 1
112  ret i32* %next
113}
114