1# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
2# ARM load store optimizer was dealing with a sequence like:
3#     s1 = VLDRS [r0, 1], implicit-def Q0
4#     s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
5#     s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
6#     s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
7#
8# It decided to combine the {s0, s1} loads into a single instruction in the
9# third position. However, this leaves the instruction defining s3 with a stray
10# imp-use of Q0, which is undefined.
11#
12# The verifier catches this, so this test just makes sure that appropriate
13# liveness flags are added.
14--- |
15  target triple = "thumbv7-apple-ios"
16  define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
17    ret <4 x float> undef
18  }
19...
20---
21name:            foo
22alignment:       1
23liveins:
24  - { reg: '$r0' }
25body:             |
26  bb.0 (%ir-block.0):
27    liveins: $r0
28
29    $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4)
30    $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
31    ; CHECK: $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4)
32
33    $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
34    ; CHECK: VLDMSIA $r0, 14, $noreg, def $s0, def $s1, implicit-def $noreg
35
36    $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
37    ; CHECK: $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4)
38
39    tBX_RET 14, $noreg, implicit $q0
40...
41